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comparison src/cs/system/template/gsm_ds_amd8_tango.template @ 674:0ccda9c065bc

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gsm_ds_amd8_tango.template for tangomdm and luna targets
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 29 May 2020 04:33:30 +0000
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673:62a5285e014a 674:0ccda9c065bc
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 */
9
10 -c /* Autoinitialize variables at runtime */
11
12 /*********************************/
13 /* SPECIFY THE SYSTEM MEMORY MAP */
14 /*********************************/
15
16 MEMORY
17 {
18 /* CS0: Flash 8 Mbytes ****************************************************/
19 /* Interrupt Vectors Table */
20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
21
22 /* Boot Sector */
23 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
24
25 /* Magic Word for Calypso Boot ROM */
26 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
27
28 /* Program Memory */
29 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
30 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
31 P_MEM3 (RXI) : org = 0x00004704 len = 0x00400000
32
33 /* FFS Area */
34 FFS_MEM (RX) : org = 0x00700000 len = 0x00100000
35 /**************************************************************************/
36
37 /* CS1: External SRAM 2 Mbytes ********************************************/
38 /* Data Memory */
39 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
40 D_MEM2 (RW) : org = 0x01100000 len = 0x00100000
41 /**************************************************************************/
42
43 /* CS6: Calypso Internal SRAM 256 kbytes **********************************/
44 /* Code & Variables Memory */
45 S_MEM (RXW) : org = 0x00800000 len = 0x00040000
46 /**************************************************************************/
47 }
48
49 /***********************************************/
50 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
51 /***********************************************/
52
53 /*
54 * Since the bootloader directly calls the INT_Initialize() routine located
55 * in int.s, this int.s code must always be mapped at the same address
56 * (usually in the second flash sector). Its length is about 0x500 bytes.
57 * Then comes the code that need to be loaded into the internal RAM.
58 */
59
60 SECTIONS
61 {
62 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
63 .monitor : > B_MEM /* Monitor Constants & Code */
64 {
65 $(CONST_BOOT_LIB)
66 }
67
68 .inttext : {} > P_MEM1 /* int.s Code */
69
70 .bss_dar : > D_MEM1 /* DAR SWE Variables */
71 {
72 $(BSS_DAR_LIB)
73 }
74
75 /*
76 * The .bss section should not be split to ensure it is initialized to 0
77 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
78 * or in D_MEM2.
79 */
80
81 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
82 {
83 $(BSS_BOOT_LIB)
84 }
85
86 /*
87 * All .bss sections, which must be mapped in internal RAM must be
88 * grouped in order to initialized the corresponding memory to 0.
89 * This initialization is done in int.s file before calling the Nucleus
90 * routine.
91 */
92
93 GROUP
94 {
95 S_D_Mem /* Label of start address of .bss section in Int. RAM */
96 .DintMem
97 {
98
99 /*
100 * .bss sections of the application
101 */
102
103 $(BSS_LIBS)
104
105 }
106
107 API_HISR_stack : {}
108
109 E_D_Mem /* Label of end address of .bss section in Int. RAM */
110 } > S_MEM
111
112 /*
113 * .text and .const sections which must be mapped in internal RAM.
114 */
115
116 .ldfl : {} > P_MEM2 /* Used to know the start load address */
117 GROUP load = P_MEM3, run = S_MEM
118 {
119 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
120 .PIntMem
121 {
122 /*
123 * .text and .const sections of the application.
124 *
125 * The .veneer sections correspond exactly to .text:v&n sections
126 * implementing the veneer functions. The .text:v$n -> .veneer
127 * translation is performed by PTOOL software when PTOOL_OPTIONS
128 * environement variable is set to veneer_section.
129 */
130
131 $(CONST_LIBS)
132
133 }
134 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
135 }
136
137 /*
138 * The rest of the code is mapped in flash, however the trampolines
139 * load address should be consistent with .text.
140 */
141 COMMENT2START
142 `trampolines load = P_MEM3, run = S_MEM
143 COMMENT2END
144
145 .text : {} > P_MEM3 /* Code */
146
147 /*
148 * The rest of the constants is mapped in flash.
149 * The .cinit section should not be split.
150 */
151
152 .cinit : {} > P_MEM3 /* Initialization Tables */
153 .const : {} > P_MEM3 /* Constant Data */
154 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
155
156 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
157
158 .stackandheap : > D_MEM1 /* System Stacks, etc... */
159 {
160 /* Leave 20 32bit words for register pushes. */
161 . = align(8);
162 . += 20 * 4;
163
164 /* Stack for abort and/or undefined modes. */
165 exception_stack = .;
166
167 /* Leave 38 32bit words for state saving on exceptions. */
168 _xdump_buffer = .;
169 . += 38 * 4;
170 . = align(8);
171
172 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
173 stack_segment = .;
174 . += 0xB00;
175 }
176
177 .data : {} > D_MEM1 /* Initialized Data */
178 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
179
180 }