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comparison src/cs/layer1/cfile/l1_func.c @ 69:50a15a54801e

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src/cs/layer1: import from tcs211-l1-reconst project
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 01 Oct 2016 23:45:38 +0000
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68:838717193e09 69:50a15a54801e
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_FUNC.C
4 *
5 * Filename l1_func.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_FUNC_C
11
12 #include "l1_macro.h"
13 #include "l1_confg.h"
14
15 #if (CODE_VERSION == SIMULATION)
16 #include <string.h>
17 #include "l1_types.h"
18 #include "sys_types.h"
19 #include "l1_const.h"
20 #include "l1_time.h"
21 #include "l1_signa.h"
22 #if TESTMODE
23 #include "l1tm_defty.h"
24 #endif
25 #if (AUDIO_TASK == 1)
26 #include "l1audio_const.h"
27 #include "l1audio_cust.h"
28 #include "l1audio_defty.h"
29 #endif
30 #if (L1_GTT == 1)
31 #include "l1gtt_const.h"
32 #include "l1gtt_defty.h"
33 #endif
34 #if (L1_MP3 == 1)
35 #include "l1mp3_defty.h"
36 #endif
37 #if (L1_MIDI == 1)
38 #include "l1midi_defty.h"
39 #endif
40 //ADDED FOR AAC
41 #if (L1_AAC == 1)
42 #include "l1aac_defty.h"
43 #endif
44 #include "l1_defty.h"
45 #include "cust_os.h"
46 #include "l1_msgty.h"
47 #include "l1_varex.h"
48 #include "l1_proto.h"
49 #include "l1_mftab.h"
50 #include "l1_tabs.h"
51 #include "l1_ver.h"
52
53 #if L1_GPRS
54 #include "l1p_cons.h"
55 #include "l1p_msgt.h"
56 #include "l1p_deft.h"
57 #include "l1p_vare.h"
58 #include "l1p_tabs.h"
59 #include "l1p_macr.h"
60 #endif
61
62 #include "l1_rf2.h"
63 #include <stdio.h>
64 #include "sim_cfg.h"
65 #include "sim_cons.h"
66 #include "sim_def.h"
67 #include "sim_var.h"
68
69 #else
70
71 #include <string.h>
72 #include "l1_types.h"
73 #include "sys_types.h"
74 #include "l1_const.h"
75 #if (RF_FAM == 12)
76 #include "l1_rf12.h"
77 #elif (RF_FAM == 61)
78 #include "l1_rf61.h"
79 #endif
80 #include "l1_time.h"
81 #include "l1_signa.h"
82
83 #if TESTMODE
84 #include "l1tm_defty.h"
85 #endif
86 #if (AUDIO_TASK == 1)
87 #include "l1audio_const.h"
88 #include "l1audio_cust.h"
89 #include "l1audio_defty.h"
90 #endif
91 #if (L1_GTT == 1)
92 #include "l1gtt_const.h"
93 #include "l1gtt_defty.h"
94 #endif
95 #if (L1_MP3 == 1)
96 #include "l1mp3_defty.h"
97 #endif
98 #if (L1_MIDI == 1)
99 #include "l1midi_defty.h"
100 #endif
101 //ADDED FOR AAC
102 #if (L1_AAC == 1)
103 #include "l1aac_defty.h"
104 #endif
105 #include "l1_defty.h"
106 #include "cust_os.h"
107 #include "l1_msgty.h"
108 #include "l1_varex.h"
109 #include "l1_proto.h"
110 #include "l1_mftab.h"
111 #include "l1_tabs.h"
112 #include "l1_ver.h"
113 #include "tpudrv.h"
114
115 #include "mem.h"
116 #include "inth.h"
117 #include "clkm.h"
118 #include "rhea_arm.h"
119 #include "dma.h"
120 #include "ulpd.h"
121 #include "leadapi.h"
122
123 #if (OP_L1_STANDALONE)
124 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \
125 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
126 #include "dynamic_clock.h"
127 #endif
128 #endif
129
130
131 #if L1_GPRS
132 #include "l1p_cons.h"
133 #include "l1p_msgt.h"
134 #include "l1p_deft.h"
135 #include "l1p_vare.h"
136 #include "l1p_tabs.h"
137 #include "l1p_macr.h"
138 #endif
139
140 #endif
141 #include "l1_trace.h"
142
143 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
144 extern void L1_trace_string(char *s);
145 #endif
146
147
148 #if (CODE_VERSION != SIMULATION)
149
150 /* DSP patch */
151 #if (DWNLD == NO_DWNLD)
152 const UWORD8 patch_array[1];
153 const UWORD8 DspCode_array[1] ;
154 const UWORD8 DspData_array[1];
155 #elif (DWNLD == PATCH_DWNLD)
156 extern const UWORD8 patch_array[] ;
157 const UWORD8 DspCode_array[1] ;
158 const UWORD8 DspData_array[1];
159 #elif (DWNLD == DSP_DWNLD)
160 const UWORD8 patch_array[1] ;
161 extern const UWORD8 DspCode_array[] ;
162 extern const UWORD8 DspData_array[];
163 #else
164 extern const UWORD8 patch_array[] ;
165 extern const UWORD8 DspCode_array[] ;
166 extern const UWORD8 DspData_array[];
167 #endif
168
169 extern const UWORD8 bootCode[] ;
170 /* DSP patch */
171
172 #if ( FF_REPEATED_DL_FACCH == 1 )
173 UWORD32 fn_prev; // Added as a debug stage..
174 #endif
175
176 /*-------------------------------------------------------*/
177 /* Prototypes of internal functions used in this file. */
178 /*-------------------------------------------------------*/
179 void l1s_init_voice_blocks (void);
180
181 /*-------------------------------------------------------*/
182 /* Prototypes of external functions used in this file. */
183 /*-------------------------------------------------------*/
184 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
185 void LA_ReleaseLead(void);
186 #if (CODE_VERSION != SIMULATION)
187 void l1s_audio_path_control (UWORD16 FIR_selection, UWORD16 audio_loop);
188 #endif
189
190 #if (L1_GPRS)
191 // external functions from GPRS implementation
192 void initialize_l1pvar(void);
193 void l1pa_reset_cr_freq_list(void);
194 #endif
195 /*-------------------------------------------------------*/
196 /* dsp_power_on() */
197 /*-------------------------------------------------------*/
198 /* Parameters : */
199 /* Return : */
200 /* Functionality : */
201 /* Remarq : USART Buffer is 256 characters. While USART*/
202 /* is not run during Application_Initialize */
203 /* (hisrs not served because Nucleus scheduler*/
204 /* is not running yet) : */
205 /* ==> check string size < 256 !!!!!! */
206 /*-------------------------------------------------------*/
207 void dsp_power_on(void)
208 {
209 UWORD16 dsp_start_address;
210 UWORD16 param_size;
211 #if IDS
212 UWORD16 param_size2;
213 #endif
214
215 API i;
216 API *pt;
217 volatile WORD16 j;
218
219 T_NDB_MCU_DSP * dsp_ndb_ptr;
220
221 #if (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
222 static API_SIGNED param_tab[] = {
223
224 D_TRANSFER_RATE,
225
226 // ..................Latencies
227 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM,
228
229 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM,
230
231 //...................p_gprs_install_adress
232 D_HOLE,
233
234 //...................d_misc_config
235 D_MISC_CONFIG,
236
237
238 //...................d_cn_sw_workaround
239 C_DSP_SW_WORK_AROUND,
240
241 //...................Reserved
242 D_HOLE, D_HOLE,
243 D_HOLE, D_HOLE,
244
245 //...................Frequency burst
246 D_FB_MARGIN_BEG, D_FB_MARGIN_END,
247 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
248 D_FB_THR_DET_TRACK,
249 //...................Demodulation
250 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
251 D_DEM_POND_RED,
252 //...................TCH Full Speech
253 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
254 D_GU, D_GO, D_ATTMAX,
255 D_SM, D_B,
256
257 //...................V42 bis
258 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX,
259 D_V42B_RESET_DELAY,
260
261 //...................TCH Half Speech
262 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR,
263 D_GU_HR, D_GO_HR, D_B_HR,
264 D_SM_HR, D_ATTMAX_HR,
265
266 //...................Added variables for EFR
267 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR,
268 C_GU_EFR, C_GO_EFR, C_B_EFR,
269 C_SM_EFR, C_ATTMAX_EFR,
270
271 //...................Full rate variables
272 D_SD_MIN_THR_TCHFS,
273 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
274
275 //...................TCH Half Speech
276 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS,
277 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS,
278
279 //...................TCH Enhanced Full Rate Speech
280 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS,
281 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI,
282
283 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
284 D_SLOPE, D_Y_MIN, D_Y_MAX,
285 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
286
287 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES,
288 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT
289 };
290 param_size = 79;
291
292 #if (OP_L1_STANDALONE)
293 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \
294 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
295 /* Dynamic clock configuration */
296 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate;
297 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge;
298 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam;
299 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access;
300 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam;
301 #endif
302 #endif
303
304 #elif (DSP == 33)
305 static API_SIGNED param_tab[] = {
306
307 D_TRANSFER_RATE,
308
309 // ..................Latencies
310 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM,
311
312 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM,
313
314 //...................p_gprs_install_adress
315 D_HOLE,
316
317 //...................d_misc_config
318 D_MISC_CONFIG,
319
320 //...................d_cn_sw_workaround
321 C_DSP_SW_WORK_AROUND,
322
323 #if DCO_ALGO
324 //...................d_cn_dco_param
325 C_CN_DCO_PARAM,
326 #else
327 //.................. Reserved
328 D_HOLE,
329 #endif
330
331 //...................Reserved
332 D_HOLE, D_HOLE,
333 D_HOLE,
334
335 //...................Frequency burst
336 D_FB_MARGIN_BEG, D_FB_MARGIN_END,
337 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
338 D_FB_THR_DET_TRACK,
339 //...................Demodulation
340 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
341 D_DEM_POND_RED,
342 //...................TCH Full Speech
343 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
344 D_GU, D_GO, D_ATTMAX,
345 D_SM, D_B,
346
347 //...................V42 bis
348 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX,
349 D_V42B_RESET_DELAY,
350
351 //...................TCH Half Speech
352 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR,
353 D_GU_HR, D_GO_HR, D_B_HR,
354 D_SM_HR, D_ATTMAX_HR,
355
356 //...................Added variables for EFR
357 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR,
358 C_GU_EFR, C_GO_EFR, C_B_EFR,
359 C_SM_EFR, C_ATTMAX_EFR,
360
361 //...................Full rate variables
362 D_SD_MIN_THR_TCHFS,
363 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
364
365 //...................TCH Half Speech
366 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS,
367 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS,
368
369 //...................TCH Enhanced Full Rate Speech
370 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS,
371 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI,
372
373 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
374 D_SLOPE, D_Y_MIN, D_Y_MAX,
375 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
376
377 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES,
378 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT
379 };
380 param_size = 79;
381
382 #if (OP_L1_STANDALONE)
383 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \
384 (CHIPSET == 11) || (CHIPSET == 12)
385 /* Dynamic clock configuration */
386 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate;
387 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge;
388 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam;
389 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access;
390 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam;
391 #endif
392 #endif
393
394 #else
395
396 #if (VOC == FR)
397 static API_SIGNED param_tab[] = {
398 //...................Frequency burst
399 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
400 D_FB_THR_DET_TRACK,
401 //...................Demodulation
402 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
403 D_DEM_POND_RED, D_HOLE, D_HOLE,
404 //...................TCH Full Speech
405 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
406 D_GU, D_GO, D_ATTMAX,
407 D_SM, D_B, D_SD_MIN_THR_TCHFS,
408 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
409 //...................TCH Half Speech
410 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS,
411 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, D_WED_FIL_INI,
412 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
413 D_SLOPE, D_Y_MIN, D_Y_MAX,
414 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
415 D_DSP_TEST
416 };
417 param_size = 38;
418 #endif
419
420 #if (VOC == FR_HR)
421 static API_SIGNED param_tab[] = {
422 //...................Frequency burst
423 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
424 D_FB_THR_DET_TRACK,
425 //...................Demodulation
426 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
427 D_DEM_POND_RED, D_HOLE, D_HOLE,
428 //...................TCH Full Speech
429 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
430 D_GU, D_GO, D_ATTMAX,
431 D_SM, D_B,
432 //...................TCH Half Speech
433 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR,
434 D_GU_HR, D_GO_HR, D_B_HR,
435 D_SM_HR, D_ATTMAX_HR,
436 //...................TCH Full Speech
437 D_SD_MIN_THR_TCHFS,
438 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
439 //...................TCH Half Speech
440 D_SD_MIN_THR_TCHHS,
441 D_MA_MIN_THR_TCHHS,
442 D_SD_AV_THR_TCHHS,
443 D_MD_MAX_THR_TCHHS,
444 D_MD1_MAX_THR_TCHHS,
445 D_WED_FIL_INI,
446 D_WED_FIL_TC,
447 D_X_MIN,
448 D_X_MAX,
449 D_SLOPE,
450 D_Y_MIN,
451 D_Y_MAX,
452 D_WED_DIFF_THRESHOLD,
453 D_MABFI_MIN_THR_TCHHS,
454 D_FACCH_THR,
455 D_DSP_TEST
456 };
457 param_size = 46;
458 #endif
459
460 #if (VOC == FR_EFR)
461 static API_SIGNED param_tab[] = {
462 //...................Frequency burst
463 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
464 D_FB_THR_DET_TRACK,
465 //...................Demodulation
466 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
467 D_DEM_POND_RED, D_HOLE, D_HOLE,
468
469 //...................TCH Full Speech
470 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
471 D_GU, D_GO, D_ATTMAX,
472 D_SM, D_B,
473
474 //...................Added variables for EFR
475 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR,
476 C_GU_EFR, C_GO_EFR, C_B_EFR,
477 C_SM_EFR, C_ATTMAX_EFR,
478
479 //...................Full rate variables
480 D_SD_MIN_THR_TCHFS,
481 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
482
483 //...................TCH Enhanced Full Rate Speech
484 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS,
485 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI,
486
487 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
488 D_SLOPE, D_Y_MIN, D_Y_MAX,
489 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
490 D_DSP_TEST
491 };
492 param_size = 46;
493 #endif
494
495 #if (VOC == FR_HR_EFR)
496 static API_SIGNED param_tab[] = {
497 //...................Frequency burst
498 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ,
499 D_FB_THR_DET_TRACK,
500 //...................Demodulation
501 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL,
502 D_DEM_POND_RED, D_HOLE, D_TRANSFER_RATE,
503 //...................TCH Full Speech
504 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH,
505 D_GU, D_GO, D_ATTMAX,
506 D_SM, D_B,
507
508 //...................TCH Half Speech
509 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR,
510 D_GU_HR, D_GO_HR, D_B_HR,
511 D_SM_HR, D_ATTMAX_HR,
512
513 //...................Added variables for EFR
514 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR,
515 C_GU_EFR, C_GO_EFR, C_B_EFR,
516 C_SM_EFR, C_ATTMAX_EFR,
517
518 //...................Full rate variables
519 D_SD_MIN_THR_TCHFS,
520 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS,
521
522 //...................TCH Half Speech
523 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS,
524 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS,
525
526 //...................TCH Enhanced Full Rate Speech
527 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS,
528 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI,
529
530 D_WED_FIL_TC, D_X_MIN, D_X_MAX,
531 D_SLOPE, D_Y_MIN, D_Y_MAX,
532 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR,
533 D_HOLE,
534
535 //...................Data patch provisions
536 D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE,
537
538 //...................Version Number, TI Number
539 D_HOLE, D_HOLE,
540
541 // ..................DSP page
542 D_DSP_TEST
543
544 #if IDS
545 ,D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES,
546 D_M1_THRES, D_MAX_OVSP_DL
547 #endif
548
549 };
550 param_size = 67;
551 #if IDS
552 // Take care to not erased "d_version_number, d_ti_version and d_dsp_page" wrote by DSP before ARM
553 // set PARAM memory
554 param_size2 = 5;
555 #endif
556 #endif
557 #endif // (end of DSP != 33 || DSP != 34 || DSP != 35 || DSP != 36) || (DSP != 37) || (DSP != 38) || (DSP != 39)
558
559 // NDB pointer.
560 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
561
562
563 //-------------
564 // DSP STARTUP
565 //-------------
566 {
567 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7)
568 #if (CHIPSET == 1)
569 L1_trace_string ("\n\r\n\rGEMINI/POLESTAR test code\n\r-------------------------");
570 #elif (CHIPSET == 2)
571 L1_trace_string ("\n\r\n\rHERCULES test code\n\r------------------");
572 #elif (CHIPSET == 3)
573 L1_trace_string ("\n\r\n\rULYSSE/ULYSSE G0 test code\n\r--------------------------");
574 #elif (CHIPSET == 4)
575 L1_trace_string ("\n\r\n\rSAMSON test code\n\r----------------");
576 #elif (CHIPSET == 5)
577 L1_trace_string ("\n\r\n\rULYSSE G1 test code 13 MHz\n\r-------------------");
578 #elif (CHIPSET == 6)
579 L1_trace_string ("\n\r\n\rULYSSE G1 test code 26 MHz\n\r-------------------");
580 #elif (CHIPSET == 7)
581 L1_trace_string ("\n\r\n\rCALYPSO Rev A test code\n\r-------------------");
582 #elif (CHIPSET == 8)
583 L1_trace_string ("\n\r\n\rCALYPSO Rev B test code\n\r-------------------");
584 #elif (CHIPSET == 9)
585 L1_trace_string ("\n\r\n\rULYSSE C035 test code\n\r-------------------");
586 #elif (CHIPSET == 10) || (CHIPSET == 11)
587 L1_trace_string ("\n\r\n\rCALYPSO C035 test code\n\r-------------------");
588 #elif (CHIPSET == 12)
589 L1_trace_string ("\n\r\n\rCALYPSO PLUS test code\n\r-------------------");
590 #elif (CHIPSET == 15)
591 L1_trace_string ("\n\r\n\rLOCOSTO test code\n\r-------------------");
592 #endif
593 #endif
594
595 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7)
596 /* Display Audio Configuration */
597 L1_trace_string ("\n\rAUDIO: ");
598 #if (KEYBEEP)
599 L1_trace_string ("KB ");
600 #endif
601 #if (TONE)
602 L1_trace_string ("TN ");
603 #endif
604 #if (MELODY_E1)
605 L1_trace_string ("E1 ");
606 #endif
607 #if (MELODY_E2)
608 L1_trace_string ("E2 ");
609 #endif
610 #if (VOICE_MEMO)
611 L1_trace_string ("VM ");
612 #endif
613 #if (L1_VOICE_MEMO_AMR)
614 L1_trace_string ("VMA ");
615 #endif
616 #if (SPEECH_RECO)
617 L1_trace_string ("SR ");
618 #endif
619 #if (L1_NEW_AEC)
620 L1_trace_string ("NEWAEC ");
621 #elif (AEC)
622 L1_trace_string ("AEC ");
623 #endif
624 #if (L1_GTT)
625 L1_trace_string ("GTT ");
626 #endif
627 #if (FIR)
628 L1_trace_string ("FIR ");
629 #endif
630 #if (AUDIO_MODE)
631 L1_trace_string ("AUM ");
632 #endif
633 #if (L1_CPORT == 1)
634 L1_trace_string ("CPO ");
635 #endif
636 #if (L1_STEREOPATH == 1)
637 L1_trace_string ("STP ");
638 #endif
639 #if (L1_EXT_AUDIO_MGT == 1)
640 L1_trace_string ("EAM ");
641 #endif
642 L1_trace_string ("\n\r");
643 #endif
644 // Release Lead reset before DSP code/patch download to insure proper reset of DSP
645 LA_ReleaseLead();
646
647 // Init PLL : PLONOFF =1, PLMU = 0010 (k=3), PLLNDIV=1, PLLDIV=0
648 LA_InitialLeadBoot(bootCode); // Load the bootCode in API
649 LA_StartLead(CLKSTART); // LEAD_PLL_CNTL register (on MCU side)
650 // On SAMSON, only the LEAD reset is released
651
652 // GSM 1.5
653 //-----------------------------------------------------------------
654 // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900)
655 // register is in reset state: HOM mode, PLL off, Bridge off. No ws
656 // are applied for MCU<-->API access !!!!! So, MCU must wait for
657 // end of Leadboot execution before accessing API.
658 wait_ARM_cycles(convert_nanosec_to_cycles(10000)); // wait 10us
659
660
661 if(l1_config.dwnld == NO_DWNLD)
662 // NO DOWNLOAD...
663 {
664 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7)
665 L1_trace_string ("\n\r-> No download !!");
666 #endif
667
668 // Wait for READY status from DSP.
669 while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY);
670
671 // Set DSP start address.
672 dsp_start_address = DSP_START;
673 }
674 else
675 if(l1_config.dwnld == DSP_DWNLD)
676 // DSP CODE DOWNLOAD...
677 {
678 WORD32 load_result;
679
680 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
681 #if (VOC == FR)
682 L1_trace_string ("\n\r-> Downloading FR DSP code...");
683 #endif
684
685 #if (VOC == FR_HR)
686 L1_trace_string ("\n\r-> Downloading FR&HR DSP code...");
687 #endif
688
689 #if (VOC == FR_EFR)
690 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code...");
691 #endif
692
693 #if (VOC == FR_HR_EFR)
694 #if IDS
695 L1_trace_string ("\n\r-> Download FR&IDS DSP code...");
696 #else
697 L1_trace_string ("\n\r-> Downloading 3VOC DSP code...");
698 #endif
699 #endif
700 #endif
701
702 // Download DSP code into DSP via API / bootcode.
703 load_result = LA_LoadPage(DspCode_array,0,0);
704
705 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
706 if(load_result)
707 L1_trace_string ("\n\r-> Download FAILED !!");
708 else
709 L1_trace_string ("\n\r-> ... finished !!");
710 #endif
711
712 #if (VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR)
713 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
714 #if (VOC == FR_HR)
715 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM...");
716 #endif
717
718 #if (VOC == FR_EFR)
719 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM...");
720 #endif
721
722 #if (VOC == FR_HR_EFR)
723 #if IDS
724 L1_trace_string ("\n\r-> Download FR&IDS DSP Data ROM...");
725 #else
726 L1_trace_string ("\n\r-> Downloading 3VOC DSP DATA ROM...");
727 #endif
728 #endif
729 #endif
730
731 load_result = LA_LoadPage(DspData_array,1,0);
732
733 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
734 if(load_result)
735 L1_trace_string ("\n\r-> Download FAILED !!");
736 else
737 L1_trace_string ("\n\r-> ... finished !!");
738 #endif
739 #endif
740
741 // Set DSP start address;
742 dsp_start_address = DSP_START;
743 }
744 else
745 if(l1_config.dwnld == PATCH_DWNLD)
746 // DSP PATCH DOWNLOAD...
747 {
748 WORD32 load_result;
749
750 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
751 L1_trace_string ("\n\r-> Downloading patch...");
752 #endif
753
754 // Download DSP patch into DSP via API / bootcode.
755 load_result = LA_LoadPage(patch_array,0,0);
756
757 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
758 if(load_result)
759 L1_trace_string ("\n\r-> Download FAILED !!");
760 else
761 L1_trace_string ("\n\r-> ... finished !!");
762 #endif
763
764 // Catch start address always from patch_file#.c.
765 dsp_start_address = (WORD16)patch_array[3];
766 dsp_start_address <<= 8;
767 dsp_start_address += (WORD16)patch_array[2];
768
769 // if COFF2CP output, the file begins by a null tag
770 if(dsp_start_address == 0)
771 {
772 dsp_start_address = (WORD16)patch_array[13];
773 dsp_start_address <<= 8;
774 dsp_start_address += (WORD16)patch_array[12];
775 }
776 }
777 else
778 if(l1_config.dwnld == PATCH_DSP_DWNLD)
779 // DSP CODE DOWNLOAD + PATCH DOWNLOAD...
780 {
781 WORD32 load_result;
782
783 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
784 #if (VOC == FR)
785 L1_trace_string ("\n\r-> Downloading FR DSP code...");
786 #endif
787
788 #if (VOC == FR_HR)
789 L1_trace_string ("\n\r-> Downloading FR&HR DSP code...");
790 #endif
791
792 #if (VOC == FR_EFR)
793 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code...");
794 #endif
795
796 #if (VOC == FR_HR_EFR)
797 #if IDS
798 L1_trace_string ("\n\r-> Download FR&IDS DSP code...");
799 #else
800 L1_trace_string ("\n\r-> Downloading 3VOC DSP code...");
801 #endif
802 #endif
803 #endif
804
805 // Download DSP code into DSP via API / bootcode.
806 load_result = LA_LoadPage(DspCode_array,0,0);
807
808 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
809 if(load_result)
810 L1_trace_string ("\n\r-> Download FAILED !!");
811 else
812 L1_trace_string ("\n\r-> ... finished !!");
813 #endif
814
815 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
816 L1_trace_string ("\n\r-> Downloading patch...");
817 #endif
818
819 // Download DSP patch into DSP via API / bootcode.
820 load_result = LA_LoadPage(patch_array,0,0);
821
822 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
823 if(load_result)
824 L1_trace_string ("\n\r-> Download FAILED !!");
825 else
826 L1_trace_string ("\n\r-> ... finished !!");
827 #endif
828
829 #if ((VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR))
830 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
831 #if (VOC == FR_HR)
832 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM...");
833 #endif
834
835 #if (VOC == FR_EFR)
836 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM...");
837 #endif
838
839 #if (VOC == FR_HR_EFR)
840 #if IDS
841 L1_trace_string ("\n\r-> Download FR&IDS DSP data ROM...");
842 #else
843 L1_trace_string ("\n\r-> Downloading 3VOC DSP data ROM...");
844 #endif
845 #endif
846 #endif
847
848 load_result = LA_LoadPage(DspData_array,1,0);
849
850 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7)
851 if(load_result)
852 L1_trace_string ("\n\r-> Download FAILED !!");
853 else
854 L1_trace_string ("\n\r-> ... finished !!");
855 #endif
856 #endif
857
858
859 // Catch start address always from patch_file#.c.
860 dsp_start_address = (WORD16)patch_array[3];
861 dsp_start_address <<= 8;
862 dsp_start_address += (WORD16)patch_array[2];
863
864 // if COFF2CP output, the file begins by a null tag
865 if(dsp_start_address == 0)
866 {
867 dsp_start_address = (WORD16)patch_array[13];
868 dsp_start_address <<= 8;
869 dsp_start_address += (WORD16)patch_array[12];
870 }
871 }
872
873 #if (DSP == 16 || DSP == 17 || DSP == 30 || DSP == 31 || DSP == 32)
874 dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1; // PLL variable (multiply by 3 factor)+ Power consumpt.
875 dsp_ndb_ptr->d_pll_clkmod2 = CLKMOD2; // PLL variable (40 us lock time)
876 #endif
877 }
878
879 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7)
880 L1_trace_string ("\n\r\n\r");
881 #endif
882
883 //--------------------------------------------------------------
884 // Loading of NDB parameters.......
885 //--------------------------------------------------------------
886
887 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
888 // Initialize background control variable to No background. Background tasks can be launch in GPRS
889 // as in GSM.
890 dsp_ndb_ptr->d_background_enable = 0;
891 dsp_ndb_ptr->d_background_abort = 0;
892 dsp_ndb_ptr->d_background_state = 0;
893 dsp_ndb_ptr->d_debug_ptr = 0x0074;
894 dsp_ndb_ptr->d_debug_bk = 0x0001;
895 dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG;
896 dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD;
897 dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE;
898 dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE;
899
900
901 #if (CHIPSET == 12) || (CHIPSET == 15)
902 dsp_ndb_ptr->d_swh_flag_ndb = 0; /* interpolation off for non SAIC build*/
903 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x0000;
904 #if (DSP == 36) || (DSP == 37) || (DSP == 39)
905 #if (L1_SAIC != 0)
906 dsp_ndb_ptr->d_swh_flag_ndb = SAIC_INITIAL_VALUE;
907 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x4000;
908 #endif
909 #endif
910 #endif
911
912 #if (W_A_DSP_IDLE3 == 1)
913 // Deep Sleep work around used on Calypso
914 // This init is used to backward compatibility with old patch.
915 dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3;
916 #endif
917
918 dsp_ndb_ptr->d_audio_gain_ul = 0;
919 dsp_ndb_ptr->d_audio_gain_dl = 0;
920
921 // for patch >= 2100, use new AEC
922 #if (!L1_NEW_AEC)
923 dsp_ndb_ptr->d_es_level_api = 0x5213;
924 #endif
925 dsp_ndb_ptr->d_mu_api = 0x5000;
926 #else
927 #if L1_GPRS
928 {
929 T_NDB_MCU_DSP_GPRS *p_ndb_gprs = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
930
931 // Initialize background control variable to No background.
932 p_ndb_gprs->d_background_enable = 0;
933 p_ndb_gprs->d_background_abort = 0;
934 p_ndb_gprs->d_background_state = 0;
935 }
936 #endif
937
938 #if (AMR == 1)
939 // Reset NDB pointer for AMR trace
940 dsp_ndb_ptr->p_debug_amr = 0;
941 #endif
942
943 #endif
944
945 //--------------------------------------------------------------
946 // Loading of PARAM area.......
947 //--------------------------------------------------------------
948 // Load PARAM memory...
949 pt = (API *) PARAM_ADR;
950
951 for (i=0; i<param_size; i++) *pt++ = param_tab[i];
952 #if (DSP < 33) && (IDS)
953 pt += 3;
954 for (i= param_size + 3; i<param_size + 3 + param_size2; i++) *pt++ = param_tab[i];
955 #endif
956
957 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
958 {
959 T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR;
960
961 // "d_gprs_install_address" has to be set only if no PATCH is download, i.e.
962 // "d_gprs_install_address" is automatically set by DSP if a PATCH is download
963 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD))
964 pt_param->d_gprs_install_address = INSTALL_ADD;
965 }
966 #endif
967
968 #if L1_GPRS
969 //--------------------------------------------------------------
970 // Loading of GPRS PARAM area.......
971 //--------------------------------------------------------------
972 // Load GPRS PARAM memory...
973 {
974 T_PARAM_MCU_DSP_GPRS *pt_gprs = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
975
976 // WARNING: must be configured according to the ARM & DSP clock speed.
977 // The following values are required with a 13MHz ARM clock and with a 65 MIPS DSP.
978 pt_gprs->d_overlay_rlcmac_cfg_gprs = 0;
979 pt_gprs->d_mac_threshold = 0x4e20;
980 pt_gprs->d_sd_threshold = 0x0016;
981 pt_gprs->d_nb_max_iteration = 0x0004;
982
983 #if (DSP != 33) && (DSP != 34) && (DSP != 35) && (DSP != 36) && (DSP != 37) && (DSP != 38) && (DSP != 39)
984
985 #if (OP_L1_STANDALONE)
986 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \
987 (CHIPSET == 11) || (CHIPSET == 12)
988 pt_gprs->d_lat_mcu_bridge = p_dynamic_clock_cfg->d_lat_mcu_bridge;
989 pt_gprs->d_lat_mcu_hom2sam = p_dynamic_clock_cfg->d_lat_mcu_hom2sam;
990 #endif
991 #endif
992
993 #if (CHIPSET == 4)
994 #if (!OP_L1_STANDALONE)
995 // Latency for DSP at 78 MIPS
996 pt_gprs->d_lat_mcu_bridge = 0x0009;
997 #endif
998 pt_gprs->d_lat_pll2div = 0x000C;
999 #if (!OP_L1_STANDALONE)
1000 pt_gprs->d_lat_mcu_hom2sam = 0x000C;
1001 #endif
1002 #else
1003 #if (!OP_L1_STANDALONE)
1004 pt_gprs->d_lat_mcu_bridge = 0x0008;
1005 #endif
1006 pt_gprs->d_lat_pll2div = 0x000A;
1007 #if (!OP_L1_STANDALONE)
1008 pt_gprs->d_lat_mcu_hom2sam = 0x000A;
1009 #endif
1010 #endif
1011
1012 // To be removed once G0 patch process will be aligned with G1 & G2
1013 // i.e. "d_gprs_install_address" automatically set by DSP if a Patch is present.
1014 #if (DSP == 31)
1015 if ((l1_config.dwnld == PATCH_DSP_DWNLD) ||
1016 (l1_config.dwnld == PATCH_DWNLD))
1017 pt_gprs->d_gprs_install_address = INSTALL_ADD_WITH_PATCH;
1018 else
1019 pt_gprs->d_gprs_install_address = INSTALL_ADD;
1020 #else
1021 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD))
1022 pt_gprs->d_gprs_install_address = INSTALL_ADD;
1023 #endif
1024 #endif // DSP != 33 && DSP != 34 && (DSP != 35) && DSP != 36 && DSP != 37 && DSP != 38
1025 }
1026 #endif // L1_GPRS
1027
1028 *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address...
1029 *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address.
1030 *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP...
1031
1032 }
1033 #endif //#if CODE_VERSION!=SIMULATION
1034
1035 /*-------------------------------------------------------*/
1036 /* l1s_reset_db_mcu_to_dsp() */
1037 /*-------------------------------------------------------*/
1038 /* Parameters : */
1039 /* Return : */
1040 /* Functionality : */
1041 /*-------------------------------------------------------*/
1042 void l1s_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP *page_ptr)
1043 {
1044 API i;
1045 API size = sizeof(T_DB_MCU_TO_DSP) / sizeof(API);
1046 API *ptr = (API *)page_ptr;
1047
1048 // Clear all locations.
1049 for(i=0; i<size; i++) *ptr++ = 0;
1050 }
1051
1052 #if (DSP == 38) || (DSP == 39)
1053 /*-------------------------------------------------------*/
1054 /* l1s_reset_db_common_mcu_to_dsp() */
1055 /*-------------------------------------------------------*/
1056 /* Parameters : */
1057 /* Return : */
1058 /* Functionality : */
1059 /*-------------------------------------------------------*/
1060 void l1s_reset_db_common_mcu_to_dsp(T_DB_COMMON_MCU_TO_DSP *page_ptr)
1061 {
1062 API i;
1063 API size = sizeof(T_DB_COMMON_MCU_TO_DSP) / sizeof(API);
1064 API *ptr = (API *)page_ptr;
1065
1066 // Clear all locations.
1067 for(i=0; i<size; i++) *ptr++ = 0;
1068 }
1069 #endif
1070 /*-------------------------------------------------------*/
1071 /* l1s_reset_db_dsp_to_mcu() */
1072 /*-------------------------------------------------------*/
1073 /* Parameters : */
1074 /* Return : */
1075 /* Functionality : */
1076 /*-------------------------------------------------------*/
1077 void l1s_reset_db_dsp_to_mcu(T_DB_DSP_TO_MCU *page_ptr)
1078 {
1079 API i;
1080 API size = sizeof(T_DB_DSP_TO_MCU) / sizeof(API);
1081 API *ptr = (API *)page_ptr;
1082
1083 // Clear all locations.
1084 for(i=0; i<size; i++) *ptr++ = 0;
1085
1086 // Set crc result as "SB not found".
1087 page_ptr->a_sch[0] = (1<<B_SCH_CRC); // B_SCH_CRC =1, BLUD =0
1088 }
1089
1090 /*-------------------------------------------------------*/
1091 /* l1s_increment_time() */
1092 /*-------------------------------------------------------*/
1093 /* Parameters : */
1094 /* Return : */
1095 /* Functionality : */
1096 /*-------------------------------------------------------*/
1097 void l1s_increment_time(T_TIME_INFO *time, UWORD32 fn_offset)
1098 {
1099 // Increment FN % MAX_FN.
1100 //------------------------
1101 IncMod(time->fn, fn_offset, MAX_FN);
1102
1103 if(fn_offset == 1)
1104 // Frame by frame increment...
1105 //----------------------------
1106 {
1107 IncMod(time->t2, 1, 26); // increment T2 % 26.
1108 IncMod(time->t3, 1, 51); // increment T3 % 51.
1109 IncMod(time->fn_mod42432, 1, 42432); // increment FN % 42432.
1110 IncMod(time->fn_mod13, 1, 13); // increment FN % 13.
1111
1112 if(time->t3 == 0)
1113 // new FN is a multiple of 51.
1114 {
1115 // Increment TC ((FN/51) % 8).
1116 IncMod(time->tc, 1, 8);
1117
1118 // New FN is a multiple of 26 and 51 -> increment T1 % 2048 (T1=FN div (26*51)).
1119 if(time->t2 == 0) IncMod(time->t1, 1, 2048);
1120 }
1121
1122 #if (L1_GPRS)
1123 IncMod(time->fn_mod52, 1, 52); // increment FN % 52.
1124 IncMod(time->fn_mod104, 1, 104); // increment FN % 104.
1125
1126 IncMod(time->fn_mod13_mod4, 1, 4); // increment (FN % 13) % 4.
1127 if(time->fn_mod13 == 0)
1128 time->fn_mod13_mod4 = 0;
1129
1130 if((time->fn_mod13 == 0) || (time->fn_mod13 == 4) || (time->fn_mod13 == 8))
1131 IncMod(time->block_id, 1, MAX_BLOCK_ID);
1132 #endif
1133
1134 }
1135
1136 else
1137 // Jumping on a new serving cell.
1138 //-------------------------------
1139 {
1140 time->t2 = time->fn % 26; // T2 = FN % 26.
1141 time->t3 = time->fn % 51; // T3 = FN % 51.
1142 time->t1 = time->fn / (26L*51L); // T1 = FN div 26*51
1143 time->tc = (time->fn / 51) % 8; // TC = (FN div 51) % 8
1144 time->fn_mod42432 = time->fn % 42432; // FN%42432.
1145 time->fn_mod13 = time->fn % 13; // FN % 13.
1146
1147 #if (L1_GPRS)
1148 time->fn_mod104 = time->fn % 104; // FN % 104.
1149
1150 if(time->fn_mod104 >= 52) // FN % 52.
1151 time->fn_mod52 = time->fn_mod104 - 52;
1152 else
1153 time->fn_mod52 = time->fn_mod104;
1154
1155 time->fn_mod13_mod4 = time->fn_mod13 % 4; // FN % 13 % 4.
1156
1157 time->block_id = ((3 * (time->fn / 13)) + (time->fn_mod13 / 4));
1158 #endif
1159
1160 }
1161
1162 // Computes reporting period frame number according to the current FN
1163 if(l1a_l1s_com.l1s_en_task[DEDIC] == TASK_ENABLED)
1164 {
1165 T_CHANNEL_DESCRIPTION *desc_ptr;
1166 UWORD8 timeslot_no;
1167 UWORD8 subchannel;
1168
1169 // Get a meaningfull channel description.
1170 //---------------------------------------
1171 // Rem1: this is to avoid a bad setting of "fn_in_report" when synchro is performed
1172 // whereas L1 is waiting for starting time and no channel discribed BEFORE STI.
1173 // Rem2: "fn_in_report" is computed with "CHAN1" parameters since it is the channel
1174 // which carries the SACCH.
1175 if(l1a_l1s_com.dedic_set.aset->chan1.desc_ptr->channel_type == INVALID_CHANNEL)
1176 desc_ptr = &l1a_l1s_com.dedic_set.aset->chan1.desc;
1177 else
1178 desc_ptr = l1a_l1s_com.dedic_set.aset->chan1.desc_ptr;
1179
1180 timeslot_no = desc_ptr->timeslot_no;
1181 subchannel = desc_ptr->subchannel;
1182 if(desc_ptr->channel_type == TCH_H) timeslot_no = (2*(timeslot_no/2) + subchannel);
1183
1184
1185 // Compute "fn_in_report" according to the channel_type.
1186 //------------------------------------------------------
1187 if(desc_ptr->channel_type == SDCCH_4)
1188 // FN_REPORT for SDCCH/4 is: fn%102 in [37..36].
1189 {
1190 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 37 + 102) % 102);
1191 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 37 + 102) % 102);
1192 }
1193 else
1194 if(desc_ptr->channel_type == SDCCH_8)
1195 // FN_REPORT for SDCCH/4 is: fn%102 in [12..11].
1196 {
1197 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 12 + 102) % 102);
1198 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 12 + 102) % 102);
1199 }
1200 else
1201 // TCH_F or TCH_H...
1202 {
1203 // 1) (timeslot_no * 13) is computed in order to substract the considered beginning for this
1204 // timeslot and then always be in the range 0..103
1205 // 2) 104 is added in order to cope with negative numbers.
1206 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - (timeslot_no * 13) + 104) % 104);
1207 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - (timeslot_no * 13) + 104) % 104);
1208 }
1209 }
1210 }
1211
1212 /*-------------------------------------------------------*/
1213 /* l1s_encode_rxlev() */
1214 /*-------------------------------------------------------*/
1215 /* Parameters : */
1216 /* Return : */
1217 /* Functionality : */
1218 /*-------------------------------------------------------*/
1219 WORD16 l1s_encode_rxlev(UWORD8 inlevel)
1220 {
1221 WORD16 rxlev;
1222
1223 rxlev = (221 - inlevel) / 2; // the result is divided by 2 due to
1224 // the IL format is 7.1 and rxlev format is 8.0
1225
1226 return(rxlev);
1227 }
1228
1229 /*-------------------------------------------------------*/
1230 /* l1s_send_ho_finished() */
1231 /*-------------------------------------------------------*/
1232 /* Parameters : */
1233 /* Return : */
1234 /* Functionality : */
1235 /*-------------------------------------------------------*/
1236 void l1s_send_ho_finished(UWORD8 cause)
1237 {
1238 xSignalHeaderRec *msg;
1239
1240 msg = os_alloc_sig(sizeof(T_MPHC_HANDOVER_FINISHED));
1241 DEBUGMSG(status,NU_ALLOC_ERR)
1242 msg->SignalCode = L1C_HANDOVER_FINISHED;
1243 ((T_MPHC_HANDOVER_FINISHED *)(msg->SigP))->cause = cause;
1244
1245 os_send_sig(msg, L1C1_QUEUE);
1246 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
1247 }
1248
1249
1250 /*-------------------------------------------------------*/
1251 /* l1s_get_versions() */
1252 /*-------------------------------------------------------*/
1253 /* Parameters : */
1254 /* Return : */
1255 /* Functionality : return address of version structur */
1256 /*-------------------------------------------------------*/
1257 T_VERSION *l1s_get_version (void)
1258 {
1259 //update the fields not initialized by the sw init.
1260
1261 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1262 l1s.version.dsp_code_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number1;
1263 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number2;
1264 // Note: if l1s.version.dsp_checksum is not initialized (field set to 0)
1265 // use TST_TEST_HW_REQ message to initialize the whole structur.
1266 #else
1267 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_param_ptr->d_version_number;
1268 // Note: if l1s.version.dsp_code_version and l1s.version.dsp_checksum
1269 // are not initialized (fields set to 0)
1270 // use TST_TEST_HW_REQ message to initialize the whole structur.
1271 #endif
1272
1273 return (&l1s.version);
1274 }
1275
1276 /*-------------------------------------------------------*/
1277 /* l1s_reset_dedic_meas() */
1278 /*-------------------------------------------------------*/
1279 /* Parameters : */
1280 /* Return : */
1281 /* Functionality : */
1282 /*-------------------------------------------------------*/
1283 void l1s_reset_dedic_serving_meas(void)
1284 {
1285 // Reset rxlev related fields
1286 l1a_l1s_com.Scell_info.meas.acc = 0;
1287 l1a_l1s_com.Scell_info.meas.nbr_meas = 0;
1288 l1a_l1s_com.Smeas_dedic.acc_sub = 0;
1289 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0;
1290
1291 // Reset rxqual related fields
1292 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0;
1293 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0;
1294 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0;
1295 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0;
1296
1297
1298 #if REL99
1299 #if FF_EMR
1300 // Reset EMR variables
1301 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0;
1302 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0;
1303 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0;
1304 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0;
1305 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0;
1306 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0;
1307 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0;
1308 #endif
1309 #endif
1310
1311
1312 // Reset dtx frame counter
1313 l1a_l1s_com.Smeas_dedic.dtx_used = 0;
1314 }
1315
1316 /*-------------------------------------------------------*/
1317 /* SwapIQ_dl() */
1318 /*-------------------------------------------------------*/
1319 /* Parameters : */
1320 /* Return : */
1321 /* Functionality : */
1322 /*-------------------------------------------------------*/
1323 UWORD32 l1s_swap_iq_dl(UWORD16 radio_freq, UWORD8 task)
1324 {
1325 UWORD8 swap_iq;
1326 UWORD32 task_tab;
1327
1328 #if (L1_FF_MULTIBAND == 0)
1329 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) &&
1330 (radio_freq >= l1_config.std.first_radio_freq_band2))
1331 {
1332 swap_iq = l1_config.std.swap_iq_band2;
1333 }
1334 else
1335 {
1336 swap_iq = l1_config.std.swap_iq_band1;
1337 }
1338 #else // L1_FF_MULTIBAND = 1 below
1339
1340 UWORD16 physical_band_id;
1341 physical_band_id =
1342 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq);
1343 swap_iq = rf_band[physical_band_id].swap_iq;
1344
1345 #endif // #if (L1_FF_MULTIBAND == 0) else
1346
1347 switch(swap_iq)
1348 {
1349 case 0: /* No swap at all. */
1350 case 2: /* DL, no swap. */
1351 task_tab = (UWORD32)DSP_TASK_CODE[task];
1352 break;
1353 case 1: /* DL I/Q swap. */
1354 case 3: /* DL I/Q swap. */
1355 task_tab = (UWORD32)DSP_TASK_CODE[task];
1356 task_tab |= 0x8000L;
1357 break;
1358 }
1359 return(task_tab);
1360 }
1361
1362 /*-------------------------------------------------------*/
1363 /* l1s_swap_iq_ul() */
1364 /*-------------------------------------------------------*/
1365 /* Parameters : */
1366 /* Return : */
1367 /* Functionality : */
1368 /*-------------------------------------------------------*/
1369 UWORD32 l1s_swap_iq_ul(UWORD16 radio_freq, UWORD8 task)
1370 {
1371 UWORD8 swap_iq;
1372 UWORD32 task_tab;
1373
1374 #if (L1_FF_MULTIBAND == 0)
1375
1376 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) &&
1377 (radio_freq >= l1_config.std.first_radio_freq_band2))
1378 {
1379 swap_iq = l1_config.std.swap_iq_band2;
1380 }
1381 else
1382 {
1383 swap_iq = l1_config.std.swap_iq_band1;
1384 }
1385 #else // L1_FF_MULTIBAND = 1 below
1386
1387 UWORD16 physical_band_id = 0;
1388 physical_band_id =
1389 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq);
1390 swap_iq = rf_band[physical_band_id].swap_iq;
1391
1392 #endif // #if (L1_FF_MULTIBAND == 0) else
1393
1394 switch(swap_iq)
1395 {
1396 case 0: /* No swap at all. */
1397 case 1: /* UL, no swap. */
1398 task_tab = (UWORD32)DSP_TASK_CODE[task];
1399 break;
1400 case 2: /* UL I/Q swap. */
1401 case 3: /* UL I/Q swap. */
1402 task_tab = (UWORD32)DSP_TASK_CODE[task];
1403 task_tab |= 0x8000L;
1404 break;
1405 }
1406 return(task_tab);
1407 }
1408
1409
1410 /*-------------------------------------------------------*/
1411 /* l1s_ADC_decision_on_NP() */
1412 /*-------------------------------------------------------*/
1413 /* Parameters : */
1414 /* Return : */
1415 /* Functionality : */
1416 /*-------------------------------------------------------*/
1417 UWORD8 l1s_ADC_decision_on_NP(void)
1418 {
1419 UWORD8 adc_active = INACTIVE;
1420
1421 if (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED) // no reorg mode
1422 {
1423 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING) // perform ADC only one time
1424 {
1425 adc_active = ACTIVE;
1426 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle
1427 }
1428 else
1429 {
1430 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING) // perform ADC on each "period" x bloc
1431 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period
1432 {
1433 adc_active = ACTIVE;
1434 l1a_l1s_com.adc_cpt = 0;
1435 }
1436 }
1437 }
1438 else // ADC measurement in reorg mode
1439 {
1440 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING_REORG) // perform ADC only one time
1441 {
1442 adc_active = ACTIVE;
1443 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle
1444 }
1445 else
1446 {
1447 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING_REORG) // perform ADC on each "period" x bloc
1448 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period
1449 {
1450 adc_active = ACTIVE;
1451 l1a_l1s_com.adc_cpt = 0;
1452 }
1453 }
1454 }
1455 return(adc_active);
1456 }
1457
1458
1459 #if (AMR == 1)
1460 /*-------------------------------------------------------*/
1461 /* l1s_amr_get_ratscch_type() */
1462 /*-------------------------------------------------------*/
1463 /* */
1464 /* Description: */
1465 /* ------------ */
1466 /* This function returns the type of a RATSCCH block */
1467 /* Decoding is done according to ETSI spec 05.09 */
1468 /* */
1469 /* Input parameter: */
1470 /* --------------- */
1471 /* "a_ratscch" */
1472 /* pointer to the RATSCCH block */
1473 /* */
1474 /* Output parameter: */
1475 /* ---------------- */
1476 /* Type of RATSCCH block. */
1477 /* Can be: C_RATSCCH_UNKNOWN */
1478 /* C_RATSCCH_CMI_PHASE_REQ */
1479 /* C_RATSCCH_AMR_CONFIG_REQ_MAIN */
1480 /* C_RATSCCH_AMR_CONFIG_REQ_ALT */
1481 /* C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE */
1482 /* C_RATSCCH_THRES_REQ */
1483 /* */
1484 /*-------------------------------------------------------*/
1485 UWORD8 l1s_amr_get_ratscch_type(API *a_ratscch)
1486 {
1487 // Check if the RATSCCH block is a CMI_PHASE_REQ block
1488 // -> if and only if bits 1, 3 through 34 are cleared and bit 2 is set
1489 if(((UWORD16)(a_ratscch[3] & 0xFFFE) == 0x0004) && // bits 1, 3-15 are cleared, bit 2 is set
1490 ((UWORD16)(a_ratscch[4]) == 0x0000) && // bits 16-31 are cleared
1491 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared
1492 {
1493 return C_RATSCCH_CMI_PHASE_REQ;
1494 }
1495
1496 // Check if the RATSCCH block is a THRES_REQ block
1497 // -> if and only if bits 31 through 34 are cleared and bit 30 is set
1498 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0x4000) && // bit 30 is set, bit 31 is cleared
1499 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared
1500 {
1501 return C_RATSCCH_THRES_REQ;
1502 }
1503
1504 // Check if the RATSCCH block is a AMR_CONFIG_REQ block
1505 // -> if and only if bits 33-34 are cleared and bits 30-32 are set
1506 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0xC000) && // bits 30-31 are set
1507 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0001)) // bit 32 is set, bits 33-34 are cleared
1508 {
1509 // Check if it's a main AMR_CONFIG_REQ block or an alternative AMR_CONFIG_REQ block
1510 UWORD16 ratscch_acs = (a_ratscch[4] & 0x0FF0) >> 4; // get bits 20-27
1511 UWORD8 nb_coders,i;
1512
1513 // Count number of active coders
1514 for(i=0, nb_coders=0; i<8; i++)
1515 {
1516 if((ratscch_acs & 1)==1) nb_coders++;
1517 ratscch_acs >>= 1;
1518 }
1519
1520 // If the number of coders is 1, 2 or 3, it is a main AMR_CONFIG_REQ block
1521 if(nb_coders<=3)
1522 return C_RATSCCH_AMR_CONFIG_REQ_MAIN;
1523
1524 // If the number of coders is more than 4, it is an alternate AMR_CONFIG_REQ block
1525 // Check if it must be ignored (block THRES_REQ pending) or not
1526 // -> if and only if bits 0 through 19 are set
1527 if(((UWORD16)(a_ratscch[3]) == 0xFFFF) && // bits 0-15 are set
1528 ((UWORD16)(a_ratscch[4] & 0x000F) == 0x000F)) // bits 16-19 are set
1529 return C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE;
1530 else
1531 return C_RATSCCH_AMR_CONFIG_REQ_ALT;
1532 }
1533
1534 // Block is not recognized
1535 return C_RATSCCH_UNKNOWN;
1536 }
1537
1538
1539 /*--------------------------------------------------------*/
1540 /* l1s_amr_update_from_ratscch() */
1541 /*--------------------------------------------------------*/
1542 /* */
1543 /* Description: */
1544 /* ------------ */
1545 /* This function updates the AMR parameters modified by */
1546 /* the RATSCCH block received. This updates is done both */
1547 /* in the NDB and in the L1A/L1S communication structure */
1548 /* (aset pointer). */
1549 /* Data manipulation is done according to ETSI spec 05.08 */
1550 /* */
1551 /* Input parameter: */
1552 /* --------------- */
1553 /* "a_ratscch_dl" */
1554 /* pointer to the RATSCCH block */
1555 /* */
1556 /* Output parameter: */
1557 /* ---------------- */
1558 /* n/a */
1559 /* */
1560 /*--------------------------------------------------------*/
1561 void l1s_amr_update_from_ratscch(API *a_ratscch_dl)
1562 {
1563 UWORD16 acs,hysteresis1,hysteresis2,hysteresis3,threshold1,threshold2,threshold3,icm,cmip;
1564 UWORD16 amr_change_bitmap=0;
1565 UWORD8 ratscch_type;
1566 BOOL ratscch_unknown=TRUE; // No AMR parameters update
1567
1568 // Get the RATSCCH block's type
1569 ratscch_type = l1s_amr_get_ratscch_type(a_ratscch_dl);
1570
1571 // Check the RATSCCH block's type
1572 switch(ratscch_type)
1573 {
1574 case C_RATSCCH_CMI_PHASE_REQ:
1575 {
1576 // Copy CMIP to L1 structure
1577 cmip = a_ratscch_dl[3] & 0x0001; // bit 0
1578 l1a_l1s_com.dedic_set.aset->cmip=(UWORD8)cmip;
1579 amr_change_bitmap |= 1 << C_AMR_CHANGE_CMIP;
1580 // AMR parameters update flag
1581 ratscch_unknown=FALSE;
1582 }
1583 break;
1584 case C_RATSCCH_AMR_CONFIG_REQ_MAIN:
1585 {
1586 // Copy ACS to L1 structure
1587 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27
1588 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs;
1589 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS;
1590
1591 // Copy ICM to L1 structure
1592 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29
1593 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm;
1594 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM;
1595
1596 // Copy hysteresis 1 to L1 structure
1597 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9
1598 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1;
1599 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1;
1600
1601 // Copy threshold 1 to L1 structure
1602 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5
1603 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1;
1604 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1;
1605
1606 // Copy hysteresis 2 to L1 structure
1607 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19
1608 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2;
1609 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2;
1610
1611 // Copy threshold 2 to L1 structure
1612 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15
1613 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2;
1614 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2;
1615 // AMR parameters update flag
1616 ratscch_unknown=FALSE;
1617 }
1618 break;
1619 case C_RATSCCH_AMR_CONFIG_REQ_ALT:
1620 {
1621 // Copy ACS to L1 structure
1622 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27
1623 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs;
1624 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS;
1625
1626 // Copy ICM to L1 structure
1627 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29
1628 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm;
1629 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM;
1630
1631 // Copy threshold 1 to L1 structure
1632 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5
1633 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1;
1634 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1;
1635
1636 // Copy threshold 2 to L1 structure
1637 threshold2 = (a_ratscch_dl[3] & 0x0FC0) >> 6; // bits 6-11
1638 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2;
1639 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2;
1640
1641 // Copy threshold 3 to L1 structure
1642 threshold3 = ((a_ratscch_dl[3] & 0xF000) >> 12) | // bits 12-15
1643 ((a_ratscch_dl[4] & 0x0003) << 4); // bits 16-17
1644 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3;
1645 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3;
1646
1647 // Copy hysteresis 1, 2 and 3 (common hysteresis) to L1 structure
1648 hysteresis1 = (a_ratscch_dl[4] & 0x000C) >> 2; // bits 18-19
1649 hysteresis2 = hysteresis3 = hysteresis1;
1650 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=
1651 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=
1652 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis1;
1653 amr_change_bitmap |= (1 << C_AMR_CHANGE_HYST1) | (1 << C_AMR_CHANGE_HYST2) | (1 << C_AMR_CHANGE_HYST3);
1654 // AMR parameters update flag
1655 ratscch_unknown=FALSE;
1656 }
1657 break;
1658 case C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE:
1659 {
1660 // Copy ACS to L1 structure
1661 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27
1662 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs;
1663 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS;
1664
1665 // Copy ICM to L1 structure
1666 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29
1667 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm;
1668 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM;
1669 // AMR parameters update flag
1670 ratscch_unknown=FALSE;
1671 }
1672 break;
1673 case C_RATSCCH_THRES_REQ:
1674 {
1675 // Copy hysteresis 1 to L1 structure
1676 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9
1677 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1;
1678 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1;
1679
1680 // Copy threshold 1 to L1 structure
1681 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5
1682 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1;
1683 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1;
1684
1685 // Copy hysteresis 2 to L1 structure
1686 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19
1687 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2;
1688 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2;
1689
1690 // Copy threshold 2 to L1 structure
1691 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15
1692 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2;
1693 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2;
1694
1695 // Copy hysteresis 3 to L1 structure
1696 hysteresis3 = (a_ratscch_dl[4] & 0x3C00) >> 10; // bits 26-29
1697 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis3;
1698 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST3;
1699
1700 // Copy threshold 3 to L1 structure
1701 threshold3 = (a_ratscch_dl[4] & 0x03F0) >> 4; // bits 20-25
1702 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3;
1703 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3;
1704 // AMR parameters update flag
1705 ratscch_unknown=FALSE;
1706 }
1707 break;
1708 case C_RATSCCH_UNKNOWN:
1709 {
1710 // No AMR parameters update
1711 ratscch_unknown=TRUE;
1712 }
1713 break;
1714 }
1715 // AMR parameters update only if valid RATSCCH
1716 if(ratscch_unknown==FALSE)
1717 {
1718 // Update NDB with new AMR parameters
1719 l1ddsp_load_amr_param(l1a_l1s_com.dedic_set.aset->amr_configuration,l1a_l1s_com.dedic_set.aset->cmip);
1720
1721 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1722 l1_trace_ratscch(l1s.actual_time.fn_mod42432,amr_change_bitmap);
1723 #endif
1724 }
1725 }
1726
1727 #endif // AMR
1728
1729
1730 /*
1731 * FreeCalypso TCS211 reconstruction: the following l1_memcpy_16bit()
1732 * function has been moved to l1_dyn_dwl_func.c.
1733 */
1734
1735 #if 0
1736 /*--------------------------------------------------------*/
1737 /* l1_memcpy_16bit() */
1738 /*--------------------------------------------------------*/
1739 /* */
1740 /* Description: */
1741 /* ------------ */
1742 /* This function is equivalemt of memcopy. Thid function */
1743 /* does only 8/16 bit accessed to both source and */
1744 /* destination */
1745 /* */
1746 /* Input parameter: */
1747 /* --------------- */
1748 /* "src" - input pointer */
1749 /* "len" - number of bytes to copy */
1750 /* */
1751 /* Output parameter: */
1752 /* ---------------- */
1753 /* "dst" - output pointer */
1754 /* */
1755 /*--------------------------------------------------------*/
1756 void l1_memcpy_16bit(void *dst,void* src,unsigned int len)
1757 {
1758 unsigned int i;
1759 unsigned int tempLen;
1760 unsigned char *cdst,*csrc;
1761 unsigned short *ssrc,*sdst;
1762
1763 cdst=dst;
1764 csrc=src;
1765 sdst=dst;
1766 ssrc=src;
1767
1768 if(((unsigned int)src&0x01) || ((unsigned int)dst&0x01)){
1769 // if either source or destination is not 16-bit aligned do the entire memcopy
1770 // in 8-bit
1771 for(i=0;i<len;i++){
1772 *cdst++=*csrc++;
1773 }
1774 }
1775 else{
1776 // if both the source and destination are 16-bit aligned do the memcopy
1777 // in 16-bits
1778 tempLen = len>>1;
1779 for(i=0;i<tempLen;i++){
1780 *sdst++ = *ssrc++;
1781 }
1782 if(len & 0x1){
1783 // if the caller wanted to copy odd number of bytes do a last 8-bit copy
1784 cdst=(unsigned char*)sdst;
1785 csrc=(unsigned char*)ssrc;
1786 *cdst++ = *csrc++;
1787 }
1788 }
1789 return;
1790 }
1791 #endif
1792
1793 #if (FF_L1_FAST_DECODING == 1)
1794 /*-----------------------------------------------------------------*/
1795 /* l1s_restore_synchro */
1796 /*-----------------------------------------------------------------*/
1797 /* Description: */
1798 /* ------------ */
1799 /* This function restores TPU synchro after an actiity */
1800 /* using synchro/synchro back scheme. */
1801 /* */
1802 /* Input parameters: */
1803 /* ----------------- */
1804 /* None */
1805 /* */
1806 /* Input parameters from globals: */
1807 /* ------------------------------ */
1808 /* l1s.tpu_offset */
1809 /* l1s.next_time */
1810 /* l1s.next_plus_time */
1811 /* */
1812 /* Output parameters: */
1813 /* ------------------ */
1814 /* None */
1815 /* */
1816 /* Modified parameters from globals: */
1817 /* --------------------------------- */
1818 /* l1s.actual_time */
1819 /* l1s.next_time */
1820 /* l1s.next_plus_time */
1821 /* l1s.tpu_ctrl_reg */
1822 /* l1s.dsp_ctrl_reg */
1823 /*-----------------------------------------------------------------*/
1824 void l1s_restore_synchro(void)
1825 {
1826 // Slide synchro back to mach current serving timeslot.
1827 l1dmacro_synchro(SWITCH_TIME, l1s.tpu_offset);
1828
1829 // Increment frame number.
1830 #if L1_GPRS
1831 l1s.actual_time = l1s.next_time;
1832 l1s.next_time = l1s.next_plus_time;
1833 l1s_increment_time(&(l1s.next_plus_time), 1); // Increment "next_plus time".
1834 #else
1835 l1s.actual_time = l1s.next_time;
1836 l1s_increment_time(&(l1s.next_time), 1); // Increment "next time".
1837 #endif
1838
1839 l1s.tpu_ctrl_reg |= CTRL_SYCB;
1840 l1s.dsp_ctrl_reg |= CTRL_SYNC;
1841
1842 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1843 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1));
1844 #endif
1845 }
1846
1847 BOOL l1s_check_deferred_control(UWORD8 task, UWORD8 burst_id)
1848 {
1849 /* Control activities are performed only if:
1850 - Fast decoding is not authorized
1851 - Fast decoding authorized, control running inside the fast HISR context and not first burst
1852 - Fast decoding authorized, control running inside L1S context and first burst */
1853
1854 /* Running from fast API HISR? */
1855 BOOL fast_decoding_hisr = (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING);
1856
1857 if (fast_decoding_hisr && (burst_id == BURST_1))
1858 {
1859 /* Error this case shouldn't happen */
1860 return TRUE;
1861 }
1862 else if (!fast_decoding_hisr && (burst_id != BURST_1))
1863 {
1864 /* Currently running from L1S, control must be performed on the upcoming fast HISR */
1865 l1a_apihisr_com.fast_decoding.task = task;
1866 l1a_apihisr_com.fast_decoding.burst_id = burst_id;
1867 /* If a tasks semaphore get SET do not do deferred control */
1868 if(!(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
1869 {
1870 l1a_apihisr_com.fast_decoding.deferred_control_req = TRUE;
1871 return TRUE;
1872 }
1873 }
1874 else if (!fast_decoding_hisr && (burst_id == BURST_1))
1875 {
1876 /* Control running from L1S for the first burst => Control must be performed now. */
1877 /* As a result, a fast API IT will be triggered on the next frame */
1878
1879 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED)
1880 {
1881 /* A fast API IT was already awaited. It means that we are starting the fast decoding */
1882 /* of a new block before the previous one is finished. */
1883 /* This case is signaled through the variable below so the status can stay as awaited */
1884 /* for the first fast API IT of the new block. */
1885 l1a_apihisr_com.fast_decoding.contiguous_decoding = TRUE;
1886 }
1887 else
1888 {
1889 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_AWAITED;
1890 }
1891 l1a_apihisr_com.fast_decoding.task = task;
1892 return FALSE;
1893 }
1894 /* In other cases do control now. */
1895 return FALSE;
1896 } /* end function l1s_check_deferred_control */
1897
1898 BOOL l1s_check_fast_decoding_authorized(UWORD8 task)
1899 {
1900 BOOL result = FALSE;
1901
1902 /* Is a fast decoding already in progress (AWAITED or PROCESSING states)? */
1903 /* Is a fast decoding complete but waiting for the read activity (COMPLETE state)? */
1904 /* In that case, it will continue, even if a mode change has occured. */
1905 BOOL already_in_progress = ( (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED)
1906 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING)
1907 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_COMPLETE) );
1908
1909 /* One variable used later that contains the status of several tasks */
1910 BOOL no_serving_audio_and_neighbour_tasks = (
1911 (l1a_l1s_com.l1s_en_task[EP] == TASK_DISABLED)
1912 && (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED)
1913 && (l1a_l1s_com.l1s_en_task[NSYNC] == TASK_DISABLED)
1914 && (l1a_l1s_com.l1s_en_task[FBNEW] == TASK_DISABLED)
1915 && (l1a_l1s_com.l1s_en_task[SBCONF] == TASK_DISABLED)
1916 && (l1a_l1s_com.l1s_en_task[BCCHN] == TASK_DISABLED)
1917 && (l1a_l1s_com.l1s_en_task[EBCCHS] == TASK_DISABLED)
1918 //&& (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_DISABLED)
1919 && (l1a_l1s_com.l1s_en_task[BCCHN_TOP] == TASK_DISABLED)
1920 #if (L1_GPRS)
1921 && (l1a_l1s_com.l1s_en_task[PBCCHS] == TASK_DISABLED)
1922 && (l1a_l1s_com.l1s_en_task[PEP] == TASK_DISABLED)
1923 && (l1a_l1s_com.l1s_en_task[PALLC] == TASK_DISABLED)
1924 && (l1a_l1s_com.l1s_en_task[PBCCHN_IDLE] == TASK_DISABLED)
1925 #endif /* L1_GPRS */
1926 //&& (l1a_l1s_com.l1s_en_task[SMSCB] == TASK_DISABLED)
1927 #if (L1_MP3 == 1)
1928 && (l1a_apihisr_com.mp3.running == FALSE)
1929 #endif
1930 #if (L1_AAC == 1)
1931 && (l1a_apihisr_com.aac.running == FALSE)
1932 #endif
1933 );
1934
1935 /* If fast decoding is already forbidden, do not enable it until the end of the block. */
1936 /* The forbidden status is reset at the first control of the block */
1937 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_FORBIDDEN)
1938 {
1939 return FALSE;
1940 }
1941
1942 switch(task)
1943 {
1944 case NP:
1945 {
1946 /* Enable Fast Paging (NP) except if CCCH reorg*/
1947 if ( ( already_in_progress == TRUE )
1948 ||
1949 ( (l1a_l1s_com.mode == I_MODE)
1950 && (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1951 && (no_serving_audio_and_neighbour_tasks == TRUE) )
1952 )
1953 {
1954 result = TRUE;
1955 }
1956 break;
1957 } /* case NP */
1958
1959 case NBCCHS:
1960 {
1961 /* Enable Fast Paging (NP) except if CCCH reorg*/
1962 if ( ( already_in_progress == TRUE )
1963 ||
1964 ( (l1a_l1s_com.mode == I_MODE)
1965 && (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_ENABLED)
1966 && (no_serving_audio_and_neighbour_tasks == TRUE) )
1967 )
1968 {
1969 result = TRUE;
1970 }
1971 break;
1972 } /* case NBCCHS */
1973
1974 #if (L1_GPRS)
1975 case PNP:
1976 {
1977 /* Enable Fast Paging (PNP) except if PCCCH reorg*/
1978 if ( ( already_in_progress == TRUE )
1979 ||
1980 ( (l1a_l1s_com.mode == I_MODE)
1981 && (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED)
1982 && (no_serving_audio_and_neighbour_tasks == TRUE)
1983 )
1984 )
1985 {
1986 result = TRUE;
1987 }
1988 break;
1989 } /* case PNP */
1990 #endif /* L1_GPRS*/
1991
1992 } /* switch(task) */
1993
1994 #if (L1_GPRS)
1995 if ((result == FALSE) && ((task == NP) || (task == PNP) || (task == NBCCHS)))
1996 #else /* NO_GPRS*/
1997 if ((result == FALSE) && ((task == NP) || (task == NBCCHS)))
1998 #endif /* L1_GPRS */
1999 {
2000 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_FORBIDDEN;
2001 }
2002
2003 return result;
2004 } /* end function l1s_check_fast_decoding_authorized */
2005
2006 #endif /* FF_L1_FAST_DECODING */
2007 /*-----------------------------------------------------------------*/
2008 /* l1s_check_sacch_dl_block */
2009 /*-----------------------------------------------------------------*/
2010 /* Description: */
2011 /* ------------ */
2012 /* Downlink SACCH buffer comparison function for FER Traces */
2013 /* This is called only when there is a successfully decoded */
2014 /* block. The count of no of successfully decoded SACCH blocks */
2015 /* is updated. */
2016 /* */
2017 /* Input parameters: */
2018 /* ----------------- */
2019 /* sacch_dl_block "Downlink SACCH BLOCK" */
2020 /* */
2021 /* Output parameters: */
2022 /* ------------------ */
2023 /* None */
2024 /* */
2025 /*-----------------------------------------------------------------*/
2026 #if ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4))
2027
2028 void l1s_check_sacch_dl_block(API *sacch_dl_block)
2029 {
2030 int i,j,repeat=1;
2031 if( trace_info.repeat_sacch.dl_buffer_empty == FALSE )
2032 {
2033 for(i=3,j=0;i<15;i++,j++)
2034 {
2035 if(trace_info.repeat_sacch.dl_buffer[j] != sacch_dl_block[i])
2036 {
2037 break;
2038 }
2039 }
2040 if( i != 15 )
2041 {
2042 repeat=0;
2043 }
2044 }
2045 else /* if( trace_info.repeat_sacch.dl_buffer_empty == FALSE ) */
2046 {
2047 repeat=0;
2048 } /* end else empty DL SACCH buffer*/
2049 if(repeat == 0)
2050 {
2051 trace_info.repeat_sacch.dl_good_norep++;
2052 for ( i=3 ; i<15 ; i++ )
2053 {
2054 trace_info.repeat_sacch.dl_buffer[i] = sacch_dl_block[i];// info_address[i];
2055 }
2056 trace_info.repeat_sacch.dl_buffer_empty = FALSE;
2057 } /* end if repeat = 0*/
2058 else
2059 {
2060 trace_info.repeat_sacch.dl_buffer_empty = TRUE;
2061 } /* end else repeat = 1*/
2062 } /* end function void l1s_check_sacch_dl_block */
2063 #endif /* ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4)) */
2064
2065
2066 /*-----------------------------------------------------------------*/
2067 /* l1s_store_sacch_buffer */
2068 /*-----------------------------------------------------------------*/
2069 /* Description: */
2070 /* ------------ */
2071 /* Function to store data in case of a retransmission. */
2072 /* */
2073 /* */
2074 /* Input parameters: */
2075 /* ----------------- */
2076 /* sacch_ul_block "SACCH Uplink block to be stored" */
2077 /* repeat_sacch "The buffer tocontain the stored block" */
2078 /* */
2079 /* Output parameters: */
2080 /* ------------------ */
2081 /* None */
2082 /* */
2083 /*-----------------------------------------------------------------*/
2084
2085 #if (FF_REPEATED_SACCH == 1 )
2086 void l1s_store_sacch_buffer(T_REPEAT_SACCH *repeat_sacch, UWORD8 *sacch_ul_block)
2087 {
2088 int i=0;
2089 /* Store the first 11 words after header in the first 22 bytes. */
2090 for(i=0;i<23;i++)
2091 {
2092 repeat_sacch->buffer[i] = sacch_ul_block[i] ;
2093 }
2094 repeat_sacch->buffer_empty = FALSE;
2095 }
2096 #endif /* (FF_REPEATED_SACCH == 1 ) */
2097
2098
2099 /*-----------------------------------------------------------------*/
2100 /* l1s_repeated_facch_check */
2101 /*-----------------------------------------------------------------*/
2102 /* Description: */
2103 /* ------------ */
2104 /* If two successfully decoded blocks (separated by 8 or 9 frames) are */
2105 /* identical then it returns a NULL buffer otherwise a pointer to the last block */
2106 /* data. */
2107 /* */
2108 /* */
2109 /* Input parameters: */
2110 /* ----------------- */
2111 /* "FACCH block to be stored" */
2112 /* */
2113 /* Output parameters: */
2114 /* ------------------ */
2115 /* None */
2116 /* */
2117 /*-----------------------------------------------------------------*/
2118
2119
2120 #if ( FF_REPEATED_DL_FACCH == 1 )
2121 API * l1s_repeated_facch_check(API *info_address)
2122 {
2123 unsigned int repeat=1;
2124 unsigned int i,j;
2125 UWORD8 counter_candidate;
2126
2127 counter_candidate=l1s.repeated_facch.counter_candidate;
2128 if( l1s.repeated_facch.pipeline[counter_candidate].buffer_empty == FALSE )
2129 {
2130 for(i=3,j=0;i<15;j++,i++)
2131 {
2132 if(l1s.repeated_facch.pipeline[counter_candidate].buffer[j] != info_address[i])
2133 {
2134 break;
2135 }
2136 }
2137 if( i != 15 )
2138 {
2139 repeat=0;
2140 }
2141 }
2142 else
2143 {
2144 repeat=0;
2145 } /* end else buffer empty*/
2146 #if TESTMODE
2147 if(l1_config.repeat_facch_dl_enable != REPEATED_FACCHDL_ENABLE) // repeated FACCH mode is disabled
2148 {
2149 repeat = 0;
2150 }
2151 #endif
2152 if(repeat == 0)
2153 {
2154 return &info_address[0];
2155 }
2156 else
2157 {
2158 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
2159 trace_info.facch_dl_repetition_block_count++;
2160 #endif
2161 if (((l1s.actual_time.fn - fn_prev ) == 8) || ((l1s.actual_time.fn - fn_prev ) == 9 )) // added debug
2162 return (API)NULL;
2163 else
2164 return &info_address[0];
2165 }
2166 }
2167 #endif /* FF_REPEATED_DL_FACCH == 1 */
2168
2169
2170
2171 #if ( FF_REPEATED_DL_FACCH == 1 )
2172 void l1s_store_facch_buffer(T_REPEAT_FACCH *repeated_facch, API *facch_block)
2173 {
2174 int i;
2175 UWORD8 counter_candidate;
2176 fn_prev = l1s.actual_time.fn ;// added
2177 counter_candidate=repeated_facch->counter_candidate;
2178 /* Store the first 12 words after header in the first 23 bytes. */
2179 for(i=0;i<13;i++)
2180 {
2181 repeated_facch->pipeline[counter_candidate].buffer[i] = facch_block[i] ;
2182 }
2183 repeated_facch->pipeline[counter_candidate].buffer_empty = FALSE;
2184 }
2185 #endif /* ( FF_REPEATED_DL_FACCH == 1 ) */
2186
2187 #if(L1_FF_MULTIBAND == 1)
2188
2189 #if 0
2190
2191 /*-------------------------------------------------------*/
2192 /* l1_multiband_radio_freq_convert_into_effective_band_id*/
2193 /*-------------------------------------------------------*/
2194 /* Parameters : radio_freq the frequency to convert */
2195 /* */
2196 /* */
2197 /* */
2198 /* Return : the ID of the effectiev band in which */
2199 /* is located radio_freq */
2200 /* Functionality : compare radio_freq with the effective */
2201 /* bands ranges, return efective_band_id */
2202 /* */
2203 /* */
2204 /*-------------------------------------------------------*/
2205 UWORD8 l1_multiband_radio_freq_convert_into_effective_band_id(UWORD16 radio_freq)
2206 {
2207 UWORD8 effective_band_id = 0;
2208 while( effective_band_id < NB_MAX_EFFECTIVE_SUPPORTED_BANDS)
2209 {
2210 if ((radio_freq >= multiband_conversion_data[effective_band_id].first_radio_freq)
2211 && (radio_freq < (multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].nbmax_carrier)) )
2212
2213 {
2214 return(effective_band_id);
2215 }
2216 else
2217 {
2218 effective_band_id ++;
2219 }
2220 }
2221 if(effective_band_id == NB_MAX_EFFECTIVE_SUPPORTED_BANDS)
2222 {
2223 l1_multiband_error_handler(radio_freq);
2224 }
2225 return(effective_band_id);
2226
2227 }
2228 /*-------------------------------------------------------*/
2229 /* l1_multiband_radio_freq_convert_into_physical_band_id */
2230 /*-------------------------------------------------------*/
2231 /* Parameters : radio_freq the frequency to convert */
2232 /* */
2233 /* */
2234 /* */
2235 /* Return : the ID of the physical_band band in which*/
2236 /* radio_freq is located */
2237 /* Functionality : Identify effective_band_id, the ID of */
2238 /* the effective band in whicb radio_freq is located */
2239 /* then derive physical_band_id from effective_band_id */
2240 /*-------------------------------------------------------*/
2241
2242 UWORD8 l1_multiband_radio_freq_convert_into_physical_band_id(UWORD16 radio_freq)
2243 {
2244 UWORD8 effective_band_id, physical_band_id;
2245 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq);
2246 physical_band_id = multiband_conversion_data[effective_band_id].physical_band_id;
2247 return(physical_band_id);
2248 }
2249
2250 /*-------------------------------------------------------*/
2251 /* l1_multiband_radio_freq_convert_into_operative_radio_freq*/
2252 /*-------------------------------------------------------*/
2253 /* Parameters : radio_freq the frequency to convert */
2254 /* */
2255 /* */
2256 /* */
2257 /* Return : the operative_radio_freq corresponding to radio_freq */
2258 /* Functionality : identify effective_band_id, then */
2259 /* based on the relationships linking the ranges of operative_radio_freq*/
2260 /* and radio_freq , derive operative_radio_freq */
2261 /*-------------------------------------------------------*/
2262 UWORD16 l1_multiband_radio_freq_convert_into_operative_radio_freq(UWORD16 radio_freq)
2263 {
2264 UWORD8 effective_band_id;
2265 UWORD16 operative_radio_freq;
2266 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq);
2267 operative_radio_freq = radio_freq - multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].first_operative_radio_freq;
2268 return(operative_radio_freq);
2269 }
2270 /*--------------------------------------------------------*/
2271 /* l1_multiband_map_radio_freq_into_tpu_table */
2272 /*--------------------------------------------------------*/
2273 /* Parameters : */
2274 /* radio_freq the parameter to be converted */
2275 /* */
2276 /* Return : the index in table rf_band or rf_tpu_band */
2277 /* corresponding to radio_freq */
2278 /* Functionality :identify physical_band_id */
2279 /* then derive from physical_band_id, tpu_band_index to be*/
2280 /* returned a physical band having the ID physical_band_id*/
2281 /* is mapped to the table rf_band[physical_band_id ] */
2282 /*--------------------------------------------------------*/
2283 UWORD8 l1_multiband_map_radio_freq_into_tpu_table(UWORD16 radio_freq)
2284 {
2285 UWORD8 tpu_table_index = 0;
2286 UWORD8 physical_band_id = 0;
2287 physical_band_id = l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq);
2288 /*For Neptune a band having the ID physical_band_id is mapped to multiband_rf_data[physical_band_id], rf_band[physical_band_id]*/
2289 /*Consequently the existence of this API for API is not necessary since it is redundant with l1_multiband_radio_freq_convert_into_physical_band_id*/
2290 tpu_table_index = physical_band_id;
2291 return(tpu_table_index);
2292 }
2293 /*--------------------------------------------------------*/
2294 /* l1_multiband_error_handler */
2295 /*--------------------------------------------------------*/
2296 /* Parameters : */
2297 /* radio_freq the channel number received from the L3 */
2298 /* */
2299 /* Return : */
2300 /* corresponding to radio_freq */
2301 /* Functionality :handling error code of MULTIBAND */
2302 /*--------------------------------------------------------*/
2303 void l1_multiband_error_handler(UWORD16 radio_freq)
2304 {
2305 L1_MULTIBAND_TRACE_PARAMS(MULTIBAND_ERROR_TRACE_ID, 1);
2306 #if (OP_L1_STANDALONE == 1)
2307 #if(CODE_VERSION == NOT_SIMULATION)
2308 L1BSP_error_handler();
2309 #endif /*if(CODE_VERSION == NOT_SIMULATION)*/
2310 #endif
2311 }
2312 #endif // if 0
2313 #endif /*if (L1_FF_MULTIBAND == 1)*/
2314
2315 #if (OP_L1_STANDALONE == 1)
2316
2317 UWORD8 l1_get_pwr_mngt()
2318 {
2319 return(l1_config.pwr_mngt);
2320 }
2321
2322 #endif
2323
2324 #if (L1_FF_MULTIBAND == 1)
2325 void l1_multiband_error_handler(UWORD16 radio_freq)
2326 {
2327 while(1);
2328 }
2329 #endif