FreeCalypso > hg > fc-magnetite

comparison src/cs/layer1/cfile/l1_init.c @ 69:50a15a54801e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
src/cs/layer1: import from tcs211-l1-reconst project
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 01 Oct 2016 23:45:38 +0000
parents
children 11e279107681
comparison
equal deleted inserted replaced
68:838717193e09 69:50a15a54801e
1 /************ Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_INIT.C
4 *
5 * Filename l1_init.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_INIT_C
11
12 #include "l1_confg.h"
13
14 #define W_A_DSP_PR20037 1 /* FreeCalypso */
15
16 #if (CODE_VERSION == SIMULATION)
17 #include <string.h>
18 #include "l1_types.h"
19 #include "sys_types.h"
20 #include "l1_const.h"
21 #include "l1_time.h"
22 #include "l1_signa.h"
23
24 #if TESTMODE
25 #include "l1tm_defty.h"
26 #endif
27 #if (AUDIO_TASK == 1)
28 #include "l1audio_const.h"
29 #include "l1audio_cust.h"
30 #include "l1audio_defty.h"
31 #endif
32 #if (L1_GTT == 1)
33 #include "l1gtt_const.h"
34 #include "l1gtt_defty.h"
35 #endif
36
37 #if (L1_MP3 == 1)
38 #include "l1mp3_defty.h"
39 #endif
40
41 #if (L1_MIDI == 1)
42 #include "l1midi_defty.h"
43 #endif
44 //ADDED FOR AAC
45 #if (L1_AAC == 1)
46 #include "l1aac_defty.h"
47 #endif
48 #if (L1_DYN_DSP_DWNLD == 1)
49 #include "l1_dyn_dwl_proto.h"
50 #endif
51
52 #include "l1_defty.h"
53 #include "cust_os.h"
54 #include "l1_msgty.h"
55 #include "l1_varex.h"
56 #include "l1_proto.h"
57 #include "l1_mftab.h"
58 #include "l1_tabs.h"
59 #include "l1_ver.h"
60 #include "ulpd.h"
61
62 #include "l1_proto.h"
63
64 #if L1_GPRS
65 #include "l1p_cons.h"
66 #include "l1p_msgt.h"
67 #include "l1p_deft.h"
68 #include "l1p_vare.h"
69 #include "l1p_tabs.h"
70 #include "l1p_macr.h"
71 #include "l1p_ver.h"
72 #endif
73
74 #if TESTMODE
75 #include "l1tm_ver.h"
76 #endif
77
78 #include <stdio.h>
79 #include "sim_cfg.h"
80 #include "sim_cons.h"
81 #include "sim_def.h"
82 #include "sim_var.h"
83
84 #else // NO SIMULATION
85
86 #include <string.h>
87 #include "tm_defs.h"
88 #include "l1_types.h"
89 #include "sys_types.h"
90 #include "leadapi.h"
91 #include "l1_const.h"
92 #include "l1_macro.h"
93 #include "l1_time.h"
94 #include "l1_signa.h"
95 #if (AUDIO_TASK == 1)
96 #include "l1audio_const.h"
97 #include "l1audio_cust.h"
98 #include "l1audio_defty.h"
99 #endif
100
101
102 #include "spi_drv.h"
103 #include "abb.h"
104 #if (ANLG_FAM != 11)
105 #include "abb_core_inth.h"
106 #endif
107
108 #if TESTMODE
109 #include "l1tm_defty.h"
110 #endif
111
112 #if (L1_GTT == 1)
113 #include "l1gtt_const.h"
114 #include "l1gtt_defty.h"
115 #endif
116
117 #if (L1_MP3 == 1)
118 #include "l1mp3_defty.h"
119 #endif
120
121 #if (L1_MIDI == 1)
122 #include "l1midi_defty.h"
123 #endif
124 //ADDED FOR AAC
125 #if (L1_AAC == 1)
126 #include "l1aac_defty.h"
127 #endif
128 #if (L1_DYN_DSP_DWNLD == 1)
129 #include "l1_dyn_dwl_proto.h"
130 #endif
131
132 #include "l1_defty.h"
133 #include "cust_os.h"
134 #include "l1_msgty.h"
135 #include "l1_varex.h"
136 #include "l1_proto.h"
137 #include "l1_mftab.h"
138 #include "l1_tabs.h"
139 #include "l1_ver.h"
140 #include "tpudrv.h"
141
142 #if (CHIPSET == 12) || (CHIPSET == 15)
143 #include "sys_inth.h"
144 #else
145 #include "mem.h"
146 #include "inth.h"
147 #include "dma.h"
148 #include "iq.h"
149 #endif
150
151 #include "clkm.h"
152 #include "rhea_arm.h"
153 #include "ulpd.h"
154
155 #include "l1_proto.h"
156
157 #if L1_GPRS
158 #include "l1p_cons.h"
159 #include "l1p_msgt.h"
160 #include "l1p_deft.h"
161 #include "l1p_vare.h"
162 #include "l1p_tabs.h"
163 #include "l1p_macr.h"
164 #include "l1p_ver.h"
165 #endif
166
167 #if TESTMODE
168 #include "l1tm_ver.h"
169 #endif
170
171 #endif // NOT SIMULATION
172
173
174
175 #if (RF_FAM == 61)
176 #if (DRP_FW_EXT==0)
177 #include "drp_drive.h"
178 #include "drp_api.h"
179 #include "l1_rf61.h"
180 #include "apc.h"
181 #else
182 #include "l1_rf61.h"
183 #include "l1_drp_inc.h"
184 #endif
185 #endif
186
187
188 #if (RF_FAM == 60)
189 #include "drp_drive.h"
190 #include "drp_api.h"
191 #include "l1_rf60.h"
192 #endif
193
194 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4)
195 #include "l1_trace.h"
196 #endif
197
198 #include <string.h>
199 #include <stdio.h>
200
201 #if (ANLG_FAM == 11)
202 #include "bspTwl3029_I2c.h"
203 #include "bspTwl3029_Aud_Map.h"
204 #include "bspTwl3029_Madc.h"
205 #endif
206
207 #if (RF_FAM == 61)
208 //OMAPS148175
209 #include "l1_drp_if.h"
210 #include "drp_main.h"
211 #endif
212
213 #if (ANLG_FAM == 11)
214 #if (L1_MADC_ON == 1)
215 extern BspTwl3029_MadcResults l1_madc_results;
216 extern void l1a_madc_callback(void);
217 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
218 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC
219 #endif
220 #endif
221
222 #if (AUDIO_DEBUG == 1)
223 extern UWORD8 audio_reg_read_status;
224 #endif
225
226 #endif
227
228 #if (AUDIO_TASK == 1)
229 /**************************************/
230 /* External audio prototypes */
231 /**************************************/
232 extern void l1audio_initialize_var (void);
233 #endif
234
235 extern void l1audio_dsp_init (void);
236 extern void initialize_wait_loop(void);
237
238 #if (L1_GPRS)
239 // external functions from GPRS implementation
240 void initialize_l1pvar(void);
241 void l1pa_reset_cr_freq_list(void);
242 #endif // L1_GPRS
243 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION))
244 extern void l1_api_dump(void);
245 #endif
246
247 #if (TRACE_TYPE==3)
248 void reset_stats();
249 #endif // TRACE_TYPE
250
251 #if (L1_GTT == 1)
252 extern void l1gtt_initialize_var(void);
253 #endif
254
255 #if (L1_MP3 == 1)
256 extern void l1mp3_initialize_var(void);
257 #endif
258
259 #if (L1_MIDI == 1)
260 extern void l1midi_initialize_var(void);
261 #endif
262 //ADDED FOR AAC
263 #if (L1_AAC == 1)
264 extern void l1aac_initialize_var(void);
265 #endif
266
267 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
268 extern void L1_trace_string(char *s);
269 #endif
270
271 #if (RF_FAM == 60 || RF_FAM == 61)
272 extern const UWORD8 drp_ref_sw[] ;
273 extern T_DRP_REGS_STR *drp_regs;
274 extern T_DRP_SRM_API* drp_srm_api;
275
276 extern T_DRP_SW_DATA drp_sw_data_calib;
277 extern T_DRP_SW_DATA drp_sw_data_init;
278
279 #endif
280
281 /*-------------------------------------------------------*/
282 /* l1_dsp_init() */
283 /*-------------------------------------------------------*/
284 /* Parameters : */
285 /* Return : */
286 /* Functionality : */
287 /*-------------------------------------------------------*/
288 void l1_dsp_init(void)
289 {
290 //int i;-OMAPS90550- new
291 #if (CODE_VERSION == SIMULATION)
292 // L1S <-> DSP communication...
293 //====================================================
294 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb);
295 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[0]);
296 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[0]);
297 l1s_dsp_com.dsp_param_ptr = &(buf.param);
298 l1s_dsp_com.dsp_w_page = 0;
299 l1s_dsp_com.dsp_r_page = 0;
300 l1s_dsp_com.dsp_r_page_used = 0;
301
302 #if (L1_GPRS)
303 l1ps_dsp_com.pdsp_ndb_ptr = &(buf.ndb_gprs);
304 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[0]);
305 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[0]);
306 l1ps_dsp_com.pdsp_param_ptr = &(buf.param_gprs);
307 #endif
308
309 // Reset DSP page bit and DSP enable bit...
310 //====================================================
311 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
312 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
313
314 // Set EOTD bit if required
315 //====================================================
316 #if (L1_EOTD ==1)
317 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
318 #endif
319
320
321 #else // NO SIMULATION
322
323 // L1S <-> DSP communication...
324 //====================================================
325 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
326 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0;
327 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0;
328 l1s_dsp_com.dsp_param_ptr = (T_PARAM_MCU_DSP *) PARAM_ADR;
329 l1s_dsp_com.dsp_w_page = 0;
330 l1s_dsp_com.dsp_r_page = 0;
331 l1s_dsp_com.dsp_r_page_used = 0;
332
333 #if (DSP == 38) || (DSP == 39)
334 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *)DB_COMMON_W_PAGE_0;
335 #endif
336
337 /* DSP CPU load measurement */
338 #if (DSP == 38) || (DSP == 39)
339 l1s_dsp_com.dsp_cpu_load_db_w_ptr = (T_DB_MCU_TO_DSP_CPU_LOAD *)DSP_CPU_LOAD_DB_W_PAGE_0;
340 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_CTRL))) = (API)0x0001; // enable DSP CPU load measurement
341 #endif
342
343 #if (L1_GPRS)
344 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
345 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
346 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
347 l1ps_dsp_com.pdsp_param_ptr = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
348 #endif
349
350 #if (DSP_DEBUG_TRACE_ENABLE == 1)
351 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
352 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
353 #endif
354
355 // Reset DSP page bit and DSP enable bit...
356 //====================================================
357
358 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
359
360 #if (DSP >= 33)
361 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
362 #else
363 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
364 #endif
365
366 // NDB init : Reset buffers and set flags...
367 //====================================================
368 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = FB_MODE_1;
369 l1s_dsp_com.dsp_ndb_ptr->d_fb_det = FALSE; // D_FB_DET =0
370 l1s_dsp_com.dsp_ndb_ptr->a_cd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
371 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[0] = 0; // BLUD = 0
372 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[2] = 0xffff; // NERR = 0xffff
373 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[0] = 0; // BLUD = 0
374 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[2] = 0xffff; // NERR = 0xffff
375 l1s_dsp_com.dsp_ndb_ptr->a_du_0[0] = 0; // BLUD = 0
376 l1s_dsp_com.dsp_ndb_ptr->a_du_0[2] = 0xffff; // NERR = 0xffff
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[0] = 0; // BLUD = 0
378 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
380 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff
381 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0;
382
383 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
384 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11)
385 #endif
386
387 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
388 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits
389 #endif
390 #if (ANLG_FAM == 11)
391 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits
392 #endif
393
394 #if (DSP == 32)
395 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2;
396 #endif // OP_WCP
397
398 l1s_dsp_com.dsp_ndb_ptr->a_sch26[0] = (1<<B_SCH_CRC);// B_SCH_CRC =1, BLUD =0
399 l1audio_dsp_init();
400
401 #if IDS
402 l1s_dsp_com.dsp_ndb_ptr->d_ra_conf = 0; // IDS
403 l1s_dsp_com.dsp_ndb_ptr->d_ra_act = 0; // IDS
404 l1s_dsp_com.dsp_ndb_ptr->d_ra_test = 0; // IDS
405 l1s_dsp_com.dsp_ndb_ptr->d_ra_statu = 0; // IDS
406 l1s_dsp_com.dsp_ndb_ptr->d_ra_statd = 0; // IDS
407 l1s_dsp_com.dsp_ndb_ptr->d_fax = 0; // IDS
408 #endif
409
410 #if(RF_FAM != 61)
411 // interrupt rif TX on FIFO <= threshold with threshold = 0
412 l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179;
413 #else
414 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny
415
416 #endif
417
418 #if (DSP >= 33)
419 // Initialize V42b variables
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0;
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0;
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0;
423 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0;
424 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control = 0;
425 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control_sema = 0;
426
427 #if !(W_A_DSP_SR_BGD)
428 // Initialize background control variable to No background. Background tasks can be launch in GPRS
429 // as in GSM.
430 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 0;
431 #endif
432
433 #if (L1_GPRS)
434 #if (DSP == 36) || (DSP == 37)
435 // Initialize GEA module
436 l1ps_dsp_com.pdsp_ndb_ptr->d_gea_mode = 0;
437 #endif
438 #endif
439
440 #else
441 #if (L1_GPRS)
442 // Initialize background control variable to No background
443 l1ps_dsp_com.pdsp_ndb_ptr->d_max_background = 0;
444 #endif
445 #endif
446
447 #if (L1_GPRS)
448 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER;
449
450 // Initialize the poll response buffer to "no poll request"
451 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE;
452 #else // L1_GPRS
453 #if (DSP >= 31)
454 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
455 #endif
456 #endif // L1_GPRS
457
458 // Set EOTD bit if required
459 //=============================================
460 #if (L1_EOTD ==1)
461 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
462 #endif // L1_EOTD
463
464 #if (DSP == 33)
465 #if DCO_ALGO
466 // Set DCO bit
467 if (l1_config.params.dco_enabled == TRUE)
468 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
469 #endif
470 #endif
471
472 // DCO algo in case of DSP 17/32
473 #if (DCO_ALGO == 1)
474 #if ((DSP == 17)||(DSP == 32))
475 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
476 #endif // DSP
477 #endif // DCO_ALGO
478
479 #if (DSP >= 34)
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
483 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
484 #endif
485
486 #if (DSP >= 35)
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS
491 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS
492 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_ahs = 150; // thresh detection SID frames AHS
493 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER
494 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA
495 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA
496 #endif
497
498 #if ((DSP >= 36) && (AMR_THRESHOLDS_WORKAROUND == 1))
499 // init of the afs thresholds parameters
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0;
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0;
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0;
503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0;
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0;
505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0;
506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0;
507 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1500;
508
509 // init of the ahs thresholds parameters
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500;
511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500;
512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500;
513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[3]=1500;
514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500;
515 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500;
516 #endif
517
518 // init of of the threshold for USF detection
519 #if 1 /* match TCS211 object */
520 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2140;
521 #elif (L1_FALSE_USF_DETECTION == 1)
522 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300;
523 #else
524 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0;
525 #endif
526
527 #if (CHIPSET == 12) || (CHIPSET == 15)
528 #if (DSP >= 35)
529 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
530 #endif
531 #endif
532
533 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto
534 #if (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
535 // Note: for locosto there is only one MCSI port
536 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = MCSI_PORT1;
537 #endif
538
539 #if(DSP == 36) || (DSP == 37)
540 l1s_dsp_com.dsp_ndb_ptr->d_vol_ul_level = 0x1000;
541 l1s_dsp_com.dsp_ndb_ptr->d_vol_dl_level = 0x1000;
542 l1s_dsp_com.dsp_ndb_ptr->d_vol_speed = 0x68;
543 l1s_dsp_com.dsp_ndb_ptr->d_sidetone_level = 0;
544 #endif
545 #endif // ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)))
546
547 // DB Init DB : Reset all pages, set TX power and reset SCH buffer...
548 //====================================================
549 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_0);
550 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_1);
551 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_0);
552 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_1);
553 #if (DSP == 38) || (DSP == 39)
554 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0);
555 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_1);
556 #endif
557
558 #endif // NO_SIMULATION
559
560 #if ((DSP==17)||(DSP == 32))
561 // init the DC offset values
562 l1s_dsp_com.dsp_ndb_ptr->d_dco_type = 0x0000; // Tide off
563 l1s_dsp_com.dsp_ndb_ptr->p_start_IQ = 0x0000;
564 l1s_dsp_com.dsp_ndb_ptr->d_level_off = 0x0000;
565 l1s_dsp_com.dsp_ndb_ptr->d_dco_dbg = 0x0000;
566 l1s_dsp_com.dsp_ndb_ptr->d_tide_resa = 0x0000;
567 #endif
568
569 //Initialize DSP DCO
570 #if (((DSP == 38) || (DSP == 39)) && (RF_FAM == 61))
571 l1s_dsp_com.dsp_ndb_ptr->d_dco_samples_per_symbol = C_DCO_SAMPLES_PER_SYMBOL;
572 l1s_dsp_com.dsp_ndb_ptr->d_dco_fcw = C_DCO_FCW;
573
574 // APCDEL1 will be initialized on rach only ....
575 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
576 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
577 // APCCTRL2 alone initialize on the next TDMA frame possible
578 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
579
580 l1dapc_init_ramp_tables();
581
582 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
583
584 /* Chase combining feature flag Initialise */
585 l1s_dsp_com.dsp_ndb_ptr->d_chase_comb_ctrl |= 0x0001;
586 #endif /* FF_REPEATED_SACCH or FF_REPEATED_DL_FACCH */
587
588 #endif // DSP == 38
589
590 // Intialize the AFC
591 #if (DSP == 38) || (DSP == 39)
592 #if (CODE_VERSION != SIMULATION)
593 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
594 #endif
595
596 #if (L1_DRP_IQ_SCALING == 1)
597 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
598 #else
599 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
600 #endif
601 #endif
602
603 }
604
605 /*-------------------------------------------------------*/
606 /* l1_tpu_init() */
607 /*-------------------------------------------------------*/
608 /* Parameters : */
609 /* Return : */
610 /* Functionality : */
611 /*-------------------------------------------------------*/
612 void l1_tpu_init(void)
613 {
614 #if (CODE_VERSION == SIMULATION)
615 // L1S -> TPU communication...
616 //=============================
617 l1s_tpu_com.tpu_w_page = 0;
618 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
619 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
620 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
621 l1s_tpu_com.offset = &(hw.offset);
622
623 // Reset TPU.
624 //=============================
625 *(l1s_tpu_com.offset) = 0;
626 *(l1s_tpu_com.reg_com_int) = 0;
627 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
628 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
629 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
630 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
631 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
632
633 // Init. OFFSET and SYNC registers
634 //================================
635 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
636 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
637 l1dtpu_end_scenario(); // Close TPU scenario
638
639 #else
640 // bit TPU_RESET set
641 // OFFSET and SYNCHRO initialized at 0
642 // TSP_ACT bits reset
643 // Sleep added and TPU_ENABLE set...
644 l1dmacro_init_hw();
645
646 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
647 #endif
648 }
649
650 void l1_tpu_init_light(void)
651 {
652 #if (CODE_VERSION == SIMULATION)
653 // L1S -> TPU communication...
654 //=============================
655 l1s_tpu_com.tpu_w_page = 0;
656 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
657 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
658 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
659 l1s_tpu_com.offset = &(hw.offset);
660
661 // Reset TPU.
662 //=============================
663 *(l1s_tpu_com.offset) = 0;
664 *(l1s_tpu_com.reg_com_int) = 0;
665 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
666 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
667 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
668 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
669 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
670
671 // Init. OFFSET and SYNC registers
672 //================================
673 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
674 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
675 l1dtpu_end_scenario(); // Close TPU scenario
676
677 #else
678 // bit TPU_RESET set
679 // OFFSET and SYNCHRO initialized at 0
680 // TSP_ACT bits reset
681 // Sleep added and TPU_ENABLE set...
682 l1dmacro_init_hw_light();
683
684 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
685 #endif
686 }
687
688 /*-------------------------------------------------------*/
689 /* l1_abb_power_on() */
690 /*-------------------------------------------------------*/
691 /* Parameters : */
692 /* Return : */
693 /* Functionality : */
694 /* Initialize the global structure for spi communication */
695 /* with ABB. */
696 /* Set up ABB connection (CLK 13M free) */
697 /* Aknowledge the ABB status register */
698 /* Configure ABB modules */
699 /* Program the ramp parameters into the NDB */
700 /* Load in the NDB registers' value to be programmed in */
701 /* ABB at first communication it */
702 /*-------------------------------------------------------*/
703
704 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c
705 void l1_abb_power_on(void)
706 {
707 #if (CODE_VERSION != SIMULATION)
708 #if (CHIPSET != 15)
709 T_SPI_DEV *Abb;
710 T_SPI_DEV init_spi_device;
711 UWORD16 Abb_Status;
712 T_NDB_MCU_DSP * dsp_ndb_ptr;
713
714 Abb = &init_spi_device; /* Pointer initialization to device communication structure */
715 Abb->PrescVal = SPI_CLOCK_DIV_1; /* ABB transmission parameters initialization */
716 Abb->DataTrLength = SPI_WNB_15;
717 Abb->DevAddLength = 5;
718 Abb->DevId = ABB;
719 Abb->ClkEdge = SPI_CLK_EDG_RISE;
720 Abb->TspEnLevel = SPI_NTSPEN_NEG_LEV;
721 Abb->TspEnForm = SPI_NTSPEN_LEV_TRIG;
722
723 SPI_InitDev(Abb); /* Initialize the spi to work with ABB */
724
725 ABB_free_13M(); /* Set up Abb connection (CLK 13M free).*/
726 Abb_Status = ABB_Read_Status(); /* Aknowledge the Abb status register. */
727
728 /*------------------------------------------------------------------*/
729 /* Add here SW to manage Abb VRPCSTS status register informations */
730 /*------------------------------------------------------------------*/
731
732 ABB_Read_Register_on_page(PAGE0,ITSTATREG); /* Aknowledge the interrupt status register */
733 /* to clear any pending interrupt */
734
735 ABB_on(AFC | MADC, l1a_l1s_com.recovery_flag);
736
737 // ADC init: Configuration of the channels to be converted and enable the ADC Interrupt
738 ABB_Conf_ADC(ALL,EOC_INTENA);
739
740 //in case of reset due to a recovery process do not create the HISR
741 if (l1a_l1s_com.recovery_flag == FALSE)
742 {
743 Create_ABB_HISR();
744 }
745
746 // Load RAMP up/down in NDB memory...
747 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
748
749 if (l1_config.tx_pwr_code == 0)
750 {
751 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
752 0 /* not used */,
753 0 /* not used */,
754 1 /* arbitrary value for arfcn*/);
755 }
756 else
757 {
758 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
759 5 /* arbitrary value working in any case */,
760 5 /* arbitrary value working in any case */,
761 1 /* arbitrary value for arfcn*/);
762 }
763 #endif
764
765
766 #if (ANLG_FAM == 1)
767 // Omega registers values will be programmed at 1st DSP communication interrupt
768
769 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
770 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
771 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
772 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
773 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
774 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
775 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
776 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
777 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
778 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
779 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
780
781 // APCDEL1 will be initialized on rach only ....
782 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
783
784 #if (DSP >= 33)
785 // To increase the robustness the IOTA register are reseted to 0
786 // if OMEGA, NAUSICA is used
787 dsp_ndb_ptr->d_bulgcal = 0x0000;
788 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
789 dsp_ndb_ptr->d_apcdel2 = 0x0000;
790 #endif
791 #endif
792 #if (ANLG_FAM == 2)
793 // Iota registers values will be programmed at 1st DSP communication interrupt
794
795 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
796 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
797 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
798 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
799 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
800 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
801 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
802 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
803 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
804 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
805 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
806 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
807 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
808
809 // APCDEL1 will be initialized on rach only ....
810 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
811 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
812 #endif
813 #if (ANLG_FAM == 3)
814 // Syren registers values will be programmed at 1st DSP communication interrupt
815
816 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
817 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
818 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
819 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
820 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
821 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
822 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
823 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
824 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
825 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
826 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
827 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0
828 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
829
830 // APCDEL1 will be initialized on rach only ....
831 dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
832 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
833
834 // Additional registers management brought by SYREN
835 dsp_ndb_ptr->d_vbpop = l1_config.params.vbpop; // HSOAUTO enabled only
836 dsp_ndb_ptr->d_vau_delay_init = l1_config.params.vau_delay_init; // vaud_init_delay init 2 frames
837 dsp_ndb_ptr->d_vaud_cfg = l1_config.params.vaud_cfg; // Init to zero
838 dsp_ndb_ptr->d_vauo_onoff = l1_config.params.vauo_onoff; // Init to zero
839 #if ((L1_AUDIO_MCU_ONOFF == 1)&&(OP_L1_STANDALONE == 1)&&(CHIPSET == 12))
840 ABB_Write_Register_on_page(PAGE1, VAUOCTRL, 0x0015A);
841 #endif // E Sample testing of audio on off
842 dsp_ndb_ptr->d_vaus_vol = l1_config.params.vaus_vol; // Init to zero
843 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero
844 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense)
845
846 #endif
847
848 #if (ANLG_FAM == 11)
849 // The following settings need to be done only in L1 StandALoen as PSP would
850 // do in the case of full PS Build...
851
852 //Set the CTRL3 register
853 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
854 l1_config.params.ctrl3,NULL);
855
856 #if (OP_L1_STANDALONE == 1)
857 // THESE REGISTERS ARE INITIALIZED IN STANDALONE AND PS BUILDS FOR AUDIO PATH
858
859 // ************ START REG INIT FOR PS build/STANDALONE *************
860 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_TOGB_OFFSET,
861 0x15,NULL);
862 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VULGAIN_OFFSET,
863 l1_config.params.vulgain,NULL);
864 //Set the VDLGAIN register
865 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VDLGAIN_OFFSET,
866 l1_config.params.vdlgain,NULL);
867 //Set the SIDETONE register
868 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_SIDETONE_OFFSET,
869 l1_config.params.sidetone,NULL);
870 //Set the CTRL1 register
871 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL1_OFFSET,
872 l1_config.params.ctrl1,NULL);
873 //Set the CTRL2 register
874 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL2_OFFSET,
875 l1_config.params.ctrl2,NULL);
876
877 //Set the CTRL4 register
878 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL4_OFFSET,
879 l1_config.params.ctrl4,NULL);
880 //Set the CTRL5 register
881 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL5_OFFSET,
882 l1_config.params.ctrl5,NULL);
883 //Set the CTRL6 register
884 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL6_OFFSET,
885 l1_config.params.ctrl6,NULL);
886 //Set the POPAUTO register
887 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_POPAUTO_OFFSET,
888 l1_config.params.popauto,NULL);
889
890 // ************ END REG INIT FOR PS build/STANDALONE ****************
891
892
893
894 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
895 l1_config.params.outen1,NULL);
896 //Set the OUTEN2 register
897 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
898 l1_config.params.outen2,NULL);
899 //Set the OUTEN3 register
900 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
901 l1_config.params.outen3,NULL);
902
903
904
905 //Set the AUDLGAIN register
906 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDLGAIN_OFFSET,
907 l1_config.params.aulga,NULL);
908 //Set the AUDRGAIN register
909 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDRGAIN_OFFSET,
910 l1_config.params.aurga,NULL);
911 #endif
912
913
914 #if (OP_L1_STANDALONE == 1)
915 #if (L1_MADC_ON == 1)
916 //MADC Real time initialization for all the 11 ADCs
917 bspTwl3029_Madc_enableRt( NULL, 0x7ff, l1a_madc_callback, &l1_madc_results);
918 #endif
919 #endif
920
921 #endif
922 #endif //CODE_VERSION != SIMULATION
923 }
924
925 /*-------------------------------------------------------*/
926 /* l1_pwr_mgt_init() */
927 /*-------------------------------------------------------*/
928 /* Parameters : */
929 /* ------------- */
930 /* Return : */
931 /* ------------- */
932 /* Description : */
933 /* ------------- */
934 /* This routine is used to initialize the gauging */
935 /* related variables. */
936 /*-------------------------------------------------------*/
937 void l1_pwr_mgt_init(void)
938 {
939
940 //++++++++++++++++++++++++++++++++++++++++++
941 // Power management variables
942 //++++++++++++++++++++++++++++++++++++++++++
943
944 // flags for wake-up ....
945 l1s.pw_mgr.Os_ticks_required = FALSE;
946 l1s.pw_mgr.frame_adjust = FALSE;
947 #if 0 /* not present in TCS211 */
948 l1s.pw_mgr.wakeup_time = 0;
949 #endif
950
951 // variables for sleep ....
952 l1s.pw_mgr.sleep_duration = 0;
953 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP;
954 l1s.pw_mgr.modules_status = 0; // all clocks ON
955 l1s.pw_mgr.paging_scheduled = FALSE;
956
957 #if 0 /* not present in TCS211 */
958 // variable for afc bypass mode
959 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE;
960 #endif
961
962 // 32 Khz gauging ....
963 l1s.pw_mgr.gaug_count = 0;
964 l1s.pw_mgr.enough_gaug = FALSE;
965 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
966 #if 0 /* not present in TCS211 */
967 l1s.force_gauging_next_paging_due_to_CCHR = 0;
968 #endif
969 l1s.pw_mgr.gauging_task = INACTIVE;
970
971 // GAUGING duration
972 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
973 if (l1_config.dpll <8 )
974 l1s.pw_mgr.gaug_duration = 9; // 9 frames (no more CTRL with DSP)
975 else // with a dpll >= 104Mhz the HF counter is too small: gauging limitation to 6 frames.
976 #if(CHIPSET == 15)
977 // Gauging duration could be reduced to 4 frames (from 5 frames) as fast paging (FF_L1_FAST_DECODING) is available
978 l1s.pw_mgr.gaug_duration = 4; // 4 frames
979 #else
980 l1s.pw_mgr.gaug_duration = 6; // 6 frames
981 #endif
982 #else
983 l1s.pw_mgr.gaug_duration = 11; // 1CTRL + 9 frames +1CTRL
984 #endif
985
986
987 //-------------------------------------------------
988 // INIT state:
989 // 32.768Khz is in the range [-500 ppm,+100 ppm]
990 // due to temperature variation.
991 // LF_100PPM = 32.7712768 Khz
992 // LF_500PPM = 32.751616 Khz
993 //
994 // ACQUIS STATE :
995 // 32.768Khz variations allowed from INIT value
996 // are [-50 ppm,+50ppm]. Same delta on ideal 32khz
997 // during 9 frames (gauging duration) represents 1348*T32.
998 // LF_50PPM = 32.7696384 Khz
999 // 1348/32.768 - 1348/32.7696384 = 0.002056632 ms
1000 // At 78 Mhz it means : 0.002056632ms/0.000012820513ms= 160 T
1001 //
1002 // UPDATE state :
1003 // allowed variations are [-6 ppm,+6ppm] jitter
1004 // LF_6PPM = 32.76819661 Khz
1005 // 1348/32.768 - 1348/32.76819661 = 0.00024691 ms
1006 // At 78 Mhz it means : 0.00024691 / 0.000012820513ms= 19 T
1007 //
1008 // 78 Mhz 65 Mhz 84.5 Mhz
1009 // ===========================
1010 // C_CLK_MIN 2380 1983 2578
1011 // C_CLK_INIT_MIN 8721 29113 31293
1012 // C_CLK_MAX 2381 1984 2580
1013 // C_CLK_INIT_MAX 36823 41608 1662
1014 // C_DELTA_HF_ACQUIS 160 130 173
1015 // C_DELTA_HF_UPDATE 19 15 20
1016 //-------------------------------------------------
1017 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
1018 l1s.pw_mgr.c_clk_min = C_CLK_MIN;
1019 l1s.pw_mgr.c_clk_init_min = C_CLK_INIT_MIN;
1020 l1s.pw_mgr.c_clk_max = C_CLK_MAX;
1021 l1s.pw_mgr.c_clk_init_max = C_CLK_INIT_MAX;
1022 l1s.pw_mgr.c_delta_hf_acquis = C_DELTA_HF_ACQUIS;
1023 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE;
1024 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1025 // 78000/32.7712768 = 2380.13308
1026 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM);
1027 // 0.13308*2^16
1028 #if 0 /* LoCosto version */
1029 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))-
1030 (l1s.pw_mgr.c_clk_min*LF_100PPM))*
1031 65536)/LF_100PPM); //omaps00090550
1032 #else /* TSM30 version */
1033 l1s.pw_mgr.c_clk_init_min = (UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1034 (double)(l1s.pw_mgr.c_clk_min*LF_100PPM))*
1035 65536)/LF_100PPM;
1036 #endif
1037 // 78000/32.751616 = 2381.561875
1038 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550
1039 // 0.561875*2^16
1040 #if 0 /* LoCosto version */
1041 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1042 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1043 65536)/LF_500PPM);//omaps00090550
1044 #else /* TSM30 version */
1045 l1s.pw_mgr.c_clk_init_max =(UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1046 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1047 65536)/LF_500PPM;
1048 #endif
1049 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz)
1050 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550
1051 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550
1052 #endif
1053
1054 } /* l1_pwr_mgt_init() */
1055
1056 /*-------------------------------------------------------*/
1057 /* l1_initialize_var() */
1058 /*-------------------------------------------------------*/
1059 /* Parameters : */
1060 /* ------------- */
1061 /* Return : */
1062 /* ------------- */
1063 /* Description : */
1064 /* ------------- */
1065 /* This routine is used to initialize the l1a, l1s and */
1066 /* l1a_l1s_com global structures. */
1067 /*-------------------------------------------------------*/
1068 void l1_initialize_var(void)
1069 {
1070 UWORD32 i;
1071 UWORD8 task_id;
1072
1073 //++++++++++++++++++++++++++++++++++++++++++
1074 // Power management variables
1075 //++++++++++++++++++++++++++++++++++++++++++
1076 l1_pwr_mgt_init();
1077
1078 //++++++++++++++++++++++++++++++++++++++++++
1079 // Reset "l1s" structure.
1080 //++++++++++++++++++++++++++++++++++++++++++
1081
1082 // time counter used for debug and by L3 scenario...
1083 l1s.debug_time = 0;
1084
1085 // L1S tasks management...
1086 //-----------------------------------------
1087 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++)
1088 {
1089 if (!((task_id == ADC_CSMODE0) && (l1a_l1s_com.recovery_flag != FALSE)))
1090 {
1091 l1s.task_status[task_id].new_status = NOT_PENDING;
1092 l1s.task_status[task_id].current_status = INACTIVE;
1093 }
1094 }
1095 l1s.frame_count = 0;
1096 l1s.forbid_meas = 0;
1097 #if L1_GPRS
1098 #if 0 /* not present in TCS211 */
1099 l1s.tcr_prog_done=0;
1100 #endif
1101 #endif
1102 #if (AUDIO_DEBUG == 1)
1103 audio_reg_read_status=0;
1104 #endif
1105 // MFTAB management variables...
1106 //-----------------------------------------
1107 l1s.afrm = 0;
1108 l1s_clear_mftab(l1s.mftab.frmlst);
1109
1110 // Controle parameters... (miscellaneous)
1111 //-----------------------------------------
1112 #if (RF_FAM != 61)
1113 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>3); //F13.3 -> F16.0
1114 #endif
1115 #if (RF_FAM == 61)
1116 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>2); //F13.3 -> F14.0
1117 #endif
1118
1119
1120 l1s.afc_frame_count = 0;
1121
1122 #if (TOA_ALGO == 2)
1123 l1s.toa_var.toa_shift = ISH_INVALID;
1124 l1s.toa_var.toa_snr_mask = 0;
1125 l1s.toa_var.toa_frames_counter = 0;
1126 l1s.toa_var.toa_accumul_counter = 0;
1127 l1s.toa_var.toa_accumul_value = 0;
1128 l1s.toa_var.toa_update_fn = 0;
1129 l1s.toa_var.toa_update_flag = FALSE;
1130 #else
1131 l1s.toa_shift = ISH_INVALID;
1132 l1s.toa_snr_mask = 0;
1133 #if L1_GPRS
1134 l1s.toa_period_count = 0;
1135 l1s.toa_update = FALSE;
1136 #endif
1137 #endif
1138
1139 #if (L1_GPRS == 1)
1140 #if 0 /* not present in TCS211 */
1141 l1s.algo_change_synchro_active = FALSE;
1142 #endif
1143 #endif
1144
1145 #if (L1_RF_KBD_FIX == 1)
1146 l1s.total_kbd_on_time = 5000;
1147 l1s.correction_ratio = 1;
1148 #endif
1149 /* Initialising the repeated SACCH variables */
1150 #if (FF_REPEATED_SACCH == 1 )
1151 l1s.repeated_sacch.srr = 0;/* SACCH Repetiton Request */
1152 l1s.repeated_sacch.sro = 0;/* SACCH Repetiton Order */
1153 l1s.repeated_sacch.buffer_empty = TRUE;
1154 #endif /* FF_REPEATED_SACCH ==1*/
1155
1156 #if (FF_REPEATED_DL_FACCH == 1)
1157 l1s.repeated_facch.pipeline[0].buffer_empty=l1s.repeated_facch.pipeline[1].buffer_empty=TRUE;
1158 l1s.repeated_facch.counter_candidate=0;
1159 l1s.repeated_facch.counter=1;
1160 #endif/* (FF_REPEATED_DL_FACCH == 1) */
1161
1162 // Init the spurious_fb_detected flag
1163 l1s.spurious_fb_detected = FALSE;
1164
1165 // Flag registers for RF task controle...
1166 //-----------------------------------------
1167 l1s.tpu_ctrl_reg = 0;
1168 l1s.dsp_ctrl_reg = 0;
1169
1170 // Serving...
1171 //============
1172
1173 // Serving frame number management.
1174 //---------------------------------
1175 if (l1a_l1s_com.recovery_flag == FALSE)
1176 {
1177 l1s.actual_time.tc = 0;
1178 l1s.actual_time.fn = 0;
1179 l1s.actual_time.t1 = 0;
1180 l1s.actual_time.t2 = 0;
1181 l1s.actual_time.t3 = 0;
1182 l1s.actual_time.fn_in_report = 0;
1183 l1s.actual_time.fn_mod42432 = 0;
1184
1185 l1s.next_time.tc = 0;
1186 l1s.next_time.fn = 0;
1187 l1s.next_time.t1 = 0;
1188 l1s.next_time.t2 = 0;
1189 l1s.next_time.t3 = 0;
1190 l1s.next_time.fn_in_report = 0;
1191 l1s.next_time.fn_mod42432 = 0;
1192
1193 #if L1_GPRS
1194 l1s.actual_time.block_id = 0;
1195 l1s.next_time.block_id = 0;
1196 l1s.next_plus_time = l1s.next_time;
1197 l1s_increment_time(&(l1s.next_plus_time),1);
1198 l1s.ctrl_synch_before = FALSE;
1199 #if 0 /* not present in TCS211 */
1200 l1s.next_gauging_scheduled_for_PNP= 0;
1201 #endif
1202 #endif
1203 }
1204
1205 // TXPWR management.
1206 //-------------------
1207 l1s.reported_txpwr = 0;
1208 l1s.applied_txpwr = 0;
1209
1210 // Last RXQUAL value.
1211 //-------------------
1212 l1s.rxqual = 0;
1213
1214 // Hardware info.
1215 //---------------
1216 l1s.tpu_offset = 0;
1217 l1s.tpu_offset_hw = 0;
1218
1219 l1s.tpu_win = 0;
1220
1221 // Initialize TXPWR info.
1222 l1s.last_used_txpwr = NO_TXPWR;
1223
1224 #if (AMR == 1)
1225 // Reset DTX AMR status
1226 //---------------------
1227 l1s.dtx_amr_dl_on=FALSE;
1228 #endif
1229
1230 // Code version structure
1231 //-------------------------
1232
1233 // DSP versions & checksum
1234 l1s.version.dsp_code_version = 0;
1235 l1s.version.dsp_patch_version = 0;
1236 l1s.version.dsp_checksum = 0; // checksum patch+code DSP
1237
1238 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION;
1239 l1s.version.mcu_tcs_internal = INTERNAL_VERSION;
1240 l1s.version.mcu_tcs_official = OFFICIAL_VERSION;
1241
1242 #if TESTMODE
1243 l1s.version.mcu_tm_version = TESTMODEVERSION;
1244 #else
1245 l1s.version.mcu_tm_version = 0;
1246 #endif
1247
1248 //++++++++++++++++++++++++++++++++++++++++++
1249 // Reset "l1a" structure.
1250 //++++++++++++++++++++++++++++++++++++++++++
1251
1252 // Downlink tasks management...
1253 // Uplink tasks management...
1254 // Measurement tasks management...
1255 //-----------------------------------------
1256
1257 if (l1a_l1s_com.recovery_flag == FALSE)
1258 {
1259 for(i=0; i<NBR_L1A_PROCESSES; i++)
1260 {
1261 l1a.l1a_en_meas[i] = 0;
1262 l1a.state[i] = 0; // RESET state.
1263 }
1264 }
1265 else
1266 {
1267 // L1A state for full list meas has to be maintained in case of recovery
1268 for(i=0; i<NBR_L1A_PROCESSES; i++)
1269 {
1270 if ((i != FULL_MEAS) && (i!= I_ADC))
1271 {
1272 l1a.l1a_en_meas[i] = 0;
1273 l1a.state[i] = 0; // RESET state.
1274 }
1275 }
1276 }
1277
1278 l1a.confirm_SignalCode = 0;
1279
1280 // Flag for forward/delete message management.
1281 //---------------------------------------------
1282 if (l1a_l1s_com.recovery_flag == FALSE)
1283 {
1284 l1a.l1_msg_forwarded = 0;
1285 }
1286
1287 #if (L1_VOCODER_IF_CHANGE == 1)
1288 // Reset new vocoder interface L1A global variables: automatic disabling and vocoder enabling flag.
1289 l1a.vocoder_state.automatic_disable = FALSE;
1290 l1a.vocoder_state.enabled = FALSE;
1291 #endif // if L1_VOCODER_IF_CHANGE == 1
1292 //++++++++++++++++++++++++++++++++++++++++++
1293 // Reset "l1a_l1s_com" structure.
1294 //++++++++++++++++++++++++++++++++++++++++++
1295
1296 l1a_l1s_com.l1a_activity_flag = TRUE;
1297 l1a_l1s_com.time_to_next_l1s_task = 0;
1298
1299 // Serving Cell...
1300 //=================
1301
1302 // Serving Cell identity and information.
1303 //---------------------------------------
1304 l1a_reset_cell_info(&(l1a_l1s_com.Scell_info));
1305
1306 l1a_l1s_com.Smeas_dedic.acc_sub = 0;
1307 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0;
1308 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0;
1309 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0;
1310 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0;
1311 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0;
1312 l1a_l1s_com.Smeas_dedic.dtx_used = 0;
1313
1314 #if REL99
1315 #if FF_EMR
1316 // Serving Cell identity EMR information.
1317 //---------------------------------------
1318 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0;
1319 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0;
1320 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0;
1321 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0;
1322 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0;
1323 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0;
1324 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0;
1325
1326 #endif
1327 #endif
1328
1329
1330 l1a_l1s_com.Scell_used_IL.input_level = l1_config.params.il_min;
1331 l1a_l1s_com.Scell_used_IL_d.input_level = l1_config.params.il_min;
1332 l1a_l1s_com.Scell_used_IL_dd.input_level = l1_config.params.il_min;
1333
1334 l1a_l1s_com.Scell_used_IL.lna_off = FALSE;
1335 l1a_l1s_com.Scell_used_IL_d.lna_off = FALSE;
1336 l1a_l1s_com.Scell_used_IL_dd.lna_off = FALSE;
1337
1338 // Synchro information.
1339 //---------------------------------------
1340 l1a_l1s_com.tn_difference = 0;
1341 l1a_l1s_com.dl_tn = 0;
1342 #if L1_FF_WA_OMAPS00099442
1343 l1a_l1s_com.change_tpu_offset_flag = FALSE;
1344 #endif
1345
1346 #if L1_GPRS
1347 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1348 #endif
1349
1350 // Idle parameters.
1351 //-----------------
1352 l1a_l1s_com.nbcchs.schedule_array_size=0;
1353 l1a_l1s_com.ebcchs.schedule_array_size=0;
1354 l1a_l1s_com.bcchn.current_list_size=0;
1355 l1a_l1s_com.nsync.current_list_size=0;
1356
1357 #if (GSM_IDLE_RAM != 0)
1358 l1s.gsm_idle_ram_ctl.l1s_full_exec = TRUE;
1359
1360 #if GSM_IDLE_RAM_DEBUG
1361 #if (CHIPSET == 10) && (OP_WCP == 1)
1362 l1s.gsm_idle_ram_ctl.TC_true_control=0;
1363 #endif // CHIPSET && OP_WCP
1364 #endif // GSM_IDLE_RAM_DEBUG
1365 #endif // GSM_IDLE_RAM
1366
1367 #if (L1_12NEIGH ==1)
1368 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1369 #else
1370 for (i=0;i<6;i++)
1371 #endif
1372 {
1373 l1a_l1s_com.nsync.list[i].status=NSYNC_FREE;
1374 }
1375 for (i=0;i<6;i++)
1376 {
1377 l1a_l1s_com.bcchn.list[i].status=NSYNC_FREE;
1378 }
1379
1380 // EOTD variables
1381 #if (L1_EOTD==1)
1382 l1a_l1s_com.nsync.eotd_meas_session=FALSE;
1383 l1a_l1s_com.nsync.fn_sb_serv;
1384 l1a_l1s_com.nsync.ta_sb_serv;
1385 #endif
1386
1387 // CBCH parameters.
1388 // ----------------
1389 // nothing to reset.
1390
1391 // Random Access information.
1392 // ----------------------------
1393 // nothing to reset.
1394
1395 // ADC management
1396 //---------------
1397 if (l1a_l1s_com.recovery_flag == FALSE)
1398 l1a_l1s_com.adc_mode = ADC_DISABLED;
1399
1400 // TXPWR management.
1401 //-------------------
1402 #if(L1_FF_MULTIBAND == 0)
1403 l1a_l1s_com.powerclass_band1 = 0;
1404 l1a_l1s_com.powerclass_band2 = 0;
1405 #else
1406 for( i = 0; i< (NB_MAX_SUPPORTED_BANDS); i++)
1407 {
1408 l1a_l1s_com.powerclass[i] = 0;
1409 }
1410 #endif
1411
1412 // Dedicated parameters.
1413 //----------------------
1414 l1a_l1s_com.dedic_set.aset = NULL;
1415 l1a_l1s_com.dedic_set.fset = NULL;
1416 l1a_l1s_com.dedic_set.SignalCode = 0;
1417 l1a_l1s_com.dedic_set.sync_tch = 0;
1418 l1a_l1s_com.dedic_set.reset_facch = FALSE;
1419 l1a_l1s_com.dedic_set.stop_tch = 0;
1420 #if (FF_L1_TCH_VOCODER_CONTROL)
1421 l1a_l1s_com.dedic_set.reset_sacch = FALSE;
1422 #if (L1_VOCODER_IF_CHANGE == 0)
1423 l1a_l1s_com.dedic_set.vocoder_on = TRUE;
1424 #if (W_A_DSP_PR20037 == 1)
1425 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
1426 #else // W_A_DSP_PR20037 == 0
1427 l1a_l1s_com.dedic_set.start_vocoder = FALSE;
1428 #endif // W_A_DSP_PR20037
1429 #else // L1_VOCODER_IF_CHANGE
1430 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
1431 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND;
1432 #endif // L1_VOCODER_IF_CHANGE
1433 #endif // FF_L1_TCH_VOCODER_CONTROL
1434
1435 l1a_l1s_com.dedic_set.radio_freq = 0;
1436 l1a_l1s_com.dedic_set.radio_freq_d = 0;
1437 l1a_l1s_com.dedic_set.radio_freq_dd = 0;
1438 #if ((REL99 == 1) && (FF_BHO == 1))
1439 // blind handover params in dedic set
1440 // Initialize the handover type to default value that is Normal Handover.
1441 l1a_l1s_com.dedic_set.handover_type = 0;
1442 l1a_l1s_com.dedic_set.long_rem_handover_type = 0;
1443 l1a_l1s_com.dedic_set.bcch_carrier_of_nbr_cell = 0;
1444 l1a_l1s_com.dedic_set.fn_offset = 0;
1445 l1a_l1s_com.dedic_set.time_alignment = 0;
1446 #endif
1447
1448 #if (L1_12NEIGH ==1)
1449 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1450 #else
1451 for (i=0;i<6;i++)
1452 #endif
1453 {
1454 l1a_l1s_com.nsync.list[i].sb26_offset = 0;
1455 }
1456
1457 l1a_l1s_com.dedic_set.pwrc = 0;
1458 l1a_l1s_com.dedic_set.handover_fail_mode = FALSE;
1459 #if (AMR == 1)
1460 l1a_l1s_com.dedic_set.sync_amr = FALSE;
1461 #endif
1462
1463 // Handover parameters.
1464 //---------------------
1465 // nothing to reset.
1466
1467 // Neighbour Cells...
1468 //====================
1469
1470 // FULL list.
1471 //-----------
1472 l1a_reset_full_list();
1473
1474 // BA list.
1475 //---------
1476 l1a_reset_ba_list();
1477 l1a_l1s_com.ba_list.new_list_present = FALSE;
1478
1479 #if L1_GPRS
1480 // Packet measurement: Reset of the frequency list.
1481 //-------------------------------------------------
1482 l1pa_reset_cr_freq_list();
1483 #endif
1484
1485 // L1S scheduler...
1486 //====================
1487
1488 // L1S tasks management...
1489 //-----------------------------------------
1490 {
1491 UWORD8 mem;
1492 mem = l1a_l1s_com.l1s_en_task[ADC_CSMODE0];
1493
1494 for(i=0; i<NBR_DL_L1S_TASKS; i++)
1495 {
1496 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET;
1497 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED;
1498 }
1499
1500 // in case of recovery do not change the ADC initialization
1501 if (l1a_l1s_com.recovery_flag != FALSE)
1502 l1a_l1s_com.l1s_en_task[ADC_CSMODE0] = mem;
1503 }
1504
1505 // Measurement tasks management...
1506 //-----------------------------------------
1507 l1a_l1s_com.meas_param = 0;
1508 l1a_l1s_com.l1s_en_meas = 0;
1509
1510 // L1 mode...
1511 //-----------------------------------------
1512 if (l1a_l1s_com.recovery_flag == FALSE) // do not restart from CS_MODE0 after a recovery
1513 l1a_l1s_com.mode = CS_MODE0;
1514
1515 // Control algo variables.
1516 //-----------------------------------------
1517 l1a_l1s_com.fb_mode = 0;
1518 l1a_l1s_com.toa_reset = FALSE;
1519
1520 #if(L1_FF_MULTIBAND == 0)
1521 for(i=0; i<=l1_config.std.nbmax_carrier; i++)
1522 #else
1523 for(i=0; i<= NBMAX_CARRIER; i++)
1524 #endif
1525 {
1526 l1a_l1s_com.last_input_level[i].input_level = l1_config.params.il_min;
1527 l1a_l1s_com.last_input_level[i].lna_off = FALSE;
1528 }
1529
1530 #if FF_L1_IT_DSP_DTX
1531 // Fast DTX variables.
1532 //-----------------------------------------
1533 // Clear DTX interrupt condition
1534 l1a_apihisr_com.dtx.pending = FALSE;
1535 // Enable TX activity
1536 l1a_apihisr_com.dtx.tx_active = TRUE;
1537 // No DTX status awaited
1538 l1a_apihisr_com.dtx.dtx_status = DTX_AVAILABLE;
1539 // Fast DTX service latency timer
1540 l1a_apihisr_com.dtx.fast_dtx_ready_timer = 0;
1541 // Fast DTX service available
1542 l1a_apihisr_com.dtx.fast_dtx_ready = FALSE;
1543 #endif
1544 #if L1_RECOVERY
1545 l1s.recovery.frame_count = 0;
1546 #endif
1547
1548 #if (AUDIO_TASK == 1)
1549 l1audio_initialize_var();
1550 #endif
1551
1552 #if (L1_GTT == 1)
1553 l1gtt_initialize_var();
1554 #endif
1555
1556 #if (L1_MP3 == 1)
1557 l1mp3_initialize_var();
1558 #endif
1559
1560 #if (L1_MIDI == 1)
1561 l1midi_initialize_var();
1562 #endif
1563 //ADDED FOR AAC
1564 #if (L1_AAC == 1)
1565 l1aac_initialize_var();
1566 #endif
1567 #if (L1_DYN_DSP_DWNLD == 1)
1568 l1_dyn_dwnld_initialize_var();
1569 #endif
1570 #if (FF_L1_FAST_DECODING == 1)
1571 l1a_apihisr_com.fast_decoding.pending = FALSE;
1572 l1a_apihisr_com.fast_decoding.crc_error = FALSE;
1573 l1a_apihisr_com.fast_decoding.status = 0;
1574 l1a_apihisr_com.fast_decoding.deferred_control_req = FALSE;
1575 l1a_apihisr_com.fast_decoding.task = 0;
1576 l1a_apihisr_com.fast_decoding.burst_id = 0;
1577 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE;
1578 #endif /* FF_L1_FAST_DECODING */
1579
1580
1581 #if(L1_CHECK_COMPATIBLE == 1)
1582 l1a.vcr_wait = FALSE;
1583 l1a.stop_req = FALSE;
1584 l1a.vcr_msg_param = TRUE;
1585 l1a.vch_auto_disable = FALSE;
1586
1587 #endif
1588
1589
1590 }
1591
1592
1593 /*---------------------------------------------------------*/
1594 /* l1_dpll_init_var() */
1595 /*---------------------------------------------------------*/
1596 /* Parameters : None */
1597 /* Return : None */
1598 /* Functionality : Initialize L1 DPLL variable for gauging */
1599 /* processing */
1600 /*---------------------------------------------------------*/
1601 void l1_dpll_init_var(void) {
1602
1603 #if (CODE_VERSION != SIMULATION)
1604 // Init DPLL variable
1605 //===================
1606 #if (CHIPSET == 2 || CHIPSET == 3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9)
1607 l1_config.dpll=PLL;
1608 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1609 {
1610 UWORD16 dpll_div;
1611 UWORD16 dpll_mul;
1612 #if (CHIPSET == 12)
1613 // not required for Locosto: There is NO CNTL_CLK_DSP in Locosto
1614 double dsp_div = CLKM_GET_DSP_DIV_VALUE;
1615 #endif
1616
1617 dpll_div=DPLL_READ_DPLL_DIV;
1618 dpll_mul=DPLL_READ_DPLL_MUL;
1619
1620 #if (CHIPSET == 12)
1621 // Not required for locsto due to the reason mentioned above.
1622 l1_config.dpll= ((double)(dpll_mul)/(double)(dpll_div+1))/(double)(dsp_div);
1623 #else
1624 l1_config.dpll= (double)(dpll_mul)/(double)(dpll_div+1);
1625 #endif
1626 }
1627 #endif
1628 #endif
1629
1630 } /* l1_dpll_init_var() */
1631
1632 /*-------------------------------------------------------------*/
1633 /* FUNCTION: l1_drp_wrapper_init */
1634
1635 /*-------------------------------------------------------------*/
1636
1637 #if(RF_FAM == 61)
1638 void l1_drp_wrapper_init (void)
1639 {
1640 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
1641 }
1642 #endif
1643
1644 /*-------------------------------------------------------------*/
1645 /* FUNCTION: l1_drp_init */
1646 /* Params: Void */
1647 /*
1648 Functionality: This function does the following
1649 1. Initialize Misc variables wrt DRP
1650 2a Copy the RAMP Tables into the DSP MCU API
1651 2b. Initialize other APIs wrt DCO
1652 3. Download Reference Software
1653 4. Call the function to : Start the REG_ON Script in the DRP
1654 */
1655 /*-------------------------------------------------------------*/
1656
1657 #if (L1_DRP == 1)
1658 #if (DRP_FW_EXT==1)
1659 #pragma DATA_SECTION(l1_drp_int_mem, ".drp_ptr")
1660 void * l1_drp_int_mem;
1661 #pragma DATA_SECTION(l1_drp_ext_mem, ".drp_ptr")
1662 void *l1_drp_ext_mem;
1663 #endif
1664 void l1_drp_init()
1665 {
1666 //int i;- OMAPS90550-new
1667 #if (DRP_FW_EXT==1)
1668 uint32 size_int=0;
1669 uint32 size_ext=0;
1670 #endif
1671 #if (RF_FAM == 61)
1672 volatile UWORD16 *ptr_drp_init16;
1673 UWORD16 drp_maj_version;
1674 UWORD16 drp_min_version;
1675
1676 //Initialize the following SRM_API, REG related address drp_srm_data = DRP_SRM_DATA_ADD,
1677 //drp_regs = DRP_REGS_BASE_ADD;, drp_srm_api = DRP_SRM_API_ADD
1678
1679 drp_api_addr_init();
1680
1681 #if (DRP_FW_EXT==1)
1682 drp_maj_version = (drp_ref_sw_ver >> 8) & 0xFF;
1683 drp_min_version = (drp_ref_sw_ver & 0xFF);
1684 #endif
1685
1686 //Initialize the following variables... TBD Danny
1687 //SRM_CW = 0x00000040, IRQ_CNT= 0x00000040 , TX_PTR_START_END_ADDR = 0X00200025,
1688 //RX_PTR_START_END_ADDR = 0X0000001F , 0XFFFE0806= 16
1689 //The registers are 32 bit since its a RHEA peripheral has to be writtin in 16 bit writes
1690 // This is done by the DRP script download
1691
1692 // The counter for # of DRP_DBB_RX_IRQs (in the wrapper) to be masked
1693 ptr_drp_init16 = (UWORD16 *) (DRP_DBB_RX_IRQ_MASK);
1694 (*ptr_drp_init16) = DRP_DBB_RX_IRQ_COUNT;
1695
1696 #endif //RF_FAM == 61
1697 l1s.boot_result=0;
1698 #if (DRP_FW_EXT==1)
1699 if(!((drp_min_version >= L1_DRP_COMPAT_MINOR_VER) && (drp_maj_version == L1_DRP_COMPAT_MAJOR_VER))) {
1700 l1s.boot_result = 1;
1701 return;
1702 }
1703 drp_get_memory_size(&size_int,&size_ext);
1704 /* FIXME FIXME ERROR handling for memory allocation failure */
1705 if(size_int)
1706 {
1707 l1_drp_int_mem=os_alloc_sig(size_int);
1708 if(l1_drp_int_mem==NULL)
1709 {
1710 /*FIXME Error Handling Here */
1711 l1s.boot_result = 1;
1712 return;
1713 }
1714 }
1715 if(size_ext)
1716 {
1717 l1_drp_ext_mem=os_alloc_sig(size_ext);
1718
1719 if(l1_drp_ext_mem==NULL)
1720 {
1721 /*FIXME Error Handling Here */
1722 l1s.boot_result = 1;
1723 return;
1724 }
1725 }
1726
1727 // Populate pointers
1728 if(drpfw_init(&modem_func_jump_table,&modem_var_jump_table))
1729 {
1730 // This condition should not be reached in phase 1 of DRP FW
1731 // Extraction. DRP and L1 software should always be compatible
1732 l1s.boot_result = 1;
1733 return;
1734 }
1735
1736 ((T_DRP_ENV_INT_BLK *)l1_drp_int_mem)->g_pcb_config = RF_BAND_SYSTEM_INDEX; //OMAPS148175
1737
1738 #endif // DRP_FW_EXT==1
1739 // This function would takes care of drp_ref_sw download till that is in place this would be a dummy function
1740 // Testing PLD_WriteRegister(0x0440, 0x165c);
1741 #if (RF_FAM == 60) // PLD board
1742 // for PLD board script downloading will happen through USP driver
1743 // load ref_sw_main
1744 // drp_ref_sw_upload(drp_ref_sw);
1745 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1746 #elif (RF_FAM == 61) // Locosto based board
1747 // load ref_sw_main
1748 // drp_ref_sw_upload(drp_ref_sw); // TBD replace with DRP Copy function...
1749 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1750 #endif
1751
1752 #if (L1_DRP_DITHERING == 1)
1753 (*(volatile UINT8 *)CONF_MUX_VIEW8) = 0x01;
1754 (*(volatile UINT8 *)CONF_DEBUG_SEL_TST_8) = 0x07;
1755 (*(volatile UINT8 *)CONF_GPIO_17) = 0x02;
1756 (*(volatile UINT8 *)CONF_LOCOSTO_DEBUG) = 0x00;
1757 #endif
1758
1759 }
1760 #endif // L1_DRP
1761
1762 /*-------------------------------------------------------*/
1763 /* l1_initialize() */
1764 /*-------------------------------------------------------*/
1765 /* Parameters : */
1766 /* Return : */
1767 /* Functionality : */
1768 /*-------------------------------------------------------*/
1769 void l1_initialize(T_MMI_L1_CONFIG *mmi_l1_config)
1770 {
1771 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 5)
1772 l1_trace_init();
1773 #endif
1774
1775 // this is not a recovery initialization .
1776 l1a_l1s_com.recovery_flag = FALSE;
1777
1778 // initialize the ratio of the wait loop
1779 // must be initialized before using the wait_ARM_cycles() function !!!
1780 #if (CODE_VERSION != SIMULATION)
1781 initialize_wait_loop();
1782 #endif
1783
1784 // Init Layer 1 configuration
1785 //===========================
1786 #if(L1_FF_MULTIBAND == 0)
1787 l1_config.std.id = mmi_l1_config->std;
1788 #endif
1789
1790 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code;
1791 #if 0 /* not present in TCS211 */
1792 #if IDS
1793 l1_config.ids_enable = mmi_l1_config->ids_enable;
1794 #endif
1795 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable;
1796 l1_config.facch_test.period = mmi_l1_config->facch_test.period;
1797 #endif
1798 l1_config.dwnld = mmi_l1_config->dwnld;
1799
1800 #if TESTMODE
1801 // Initialize TestMode params: must be done after Omega power-on
1802 l1_config.TestMode = FALSE;
1803 // Enable control algos and ADC
1804 l1_config.agc_enable = 1;
1805 l1_config.afc_enable = 1;
1806 l1_config.adc_enable = 1;
1807 #if (FF_REPEATED_SACCH == 1)
1808 l1_config.repeat_sacch_enable = 1; /* Repeated SACCH mode enabled */
1809 #endif /* (FF_REPEATED_SACCH == 1) */
1810 #if (FF_REPEATED_DL_FACCH == 1)
1811 l1_config.repeat_facch_dl_enable = 1; /* Repeated SACCH mode enabled */
1812 #endif /* ( FF_REPEATED_DL_FACCH == 1) */
1813 #endif
1814
1815 // sleep management configuration
1816 //===============================
1817 l1s.pw_mgr.mode_authorized = mmi_l1_config->pwr_mngt_mode_authorized;
1818 l1s.pw_mgr.clocks = mmi_l1_config->pwr_mngt_clocks;
1819 l1_config.pwr_mngt = mmi_l1_config->pwr_mngt;
1820
1821 Cust_init_std();
1822 Cust_init_params();
1823
1824
1825
1826 // Init DPLL variable
1827 //===================
1828 l1_dpll_init_var();
1829
1830 // Reset hardware (DSP,Analog Baseband device , TPU) ....
1831 //========================================================
1832 #if (CODE_VERSION != SIMULATION)
1833 dsp_power_on();
1834 l1_abb_power_on();
1835 #if (L1_DRP == 1)
1836 l1_drp_init();
1837 //required for interworking with Isample 2.1 and Isample 2.5
1838 #if (DRP_FW_EXT == 1)
1839 if (!l1s.boot_result)
1840 {
1841 #endif
1842 //for DRP Calibration
1843 Cust_init_params_drp();
1844 drp_efuse_init();
1845 #if (DRP_FW_EXT == 1)
1846 } /* end if boot_result != 0 */
1847 #endif
1848
1849 #endif
1850
1851 #endif
1852
1853 // Initialize hardware....(DSP, TPU)....
1854 //=================================================
1855 l1_tpu_init();
1856 l1_dsp_init();
1857
1858 // Initialize L1 variables (l1a, l1s, l1a_l1s_com).
1859 //=================================================
1860 l1_initialize_var();
1861
1862 // API check function
1863 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38) || (DSP == 39)) && (CODE_VERSION != SIMULATION))
1864 l1_api_dump();
1865 #endif
1866
1867 #if (L1_GPRS)
1868 // Initialize L1 variables used in packet mode (l1pa, l1ps, l1pa_l1ps_com).
1869 //========================================================================
1870 initialize_l1pvar();
1871 #endif
1872
1873 // Initialize statistics mode.......
1874 //=================================================
1875 #if TRACE_TYPE==3
1876 reset_stats();
1877 #endif
1878 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
1879 Cust_navc_ctrl_status(1);//start - NAVC
1880 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 )
1881
1882 }
1883
1884 /*-------------------------------------------------------*/
1885 /* l1_initialize_for_recovery */
1886 /*-------------------------------------------------------*/
1887 /* Parameters : */
1888 /* Return : */
1889 /* Functionality : This function is called for L1 */
1890 /* recovery after a Crash. When there are 100 COM error */
1891 /* or if ther are 100 PM =0 from the DSP Successively. */
1892 /* The Layer 1 Crashes. The next time the Protocol stack */
1893 /* requests for Full Rx Measurement (viz Cell selection) */
1894 /* This function gets called and the L1 recovery is */
1895 /* initiated. */
1896 /*-------------------------------------------------------*/
1897 #if L1_RECOVERY
1898 void l1_initialize_for_recovery(void)
1899 {
1900 LA_ResetLead(); // set DSP in reset mode
1901 initialize_wait_loop();
1902
1903 dsp_power_on(); // the reset mode is disabled here
1904 l1_abb_power_on();
1905 #if (L1_DRP == 1)
1906 l1_drp_init();
1907 //Required for interworking with Isample 2.1 and Isample 2.5
1908 Cust_init_params_drp();
1909 drp_efuse_init();
1910 #endif
1911 l1_tpu_init();
1912 #if 0 /* not in TCS211 */
1913 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec
1914 #endif
1915 l1_dsp_init();
1916 l1_initialize_var();
1917
1918 #if L1_GPRS
1919 initialize_l1pvar();
1920 #endif
1921
1922 l1a_l1s_com.recovery_flag = FALSE;
1923
1924 // clear pending IQ_FRAME it and enable it
1925 #if (CHIPSET >= 4 )
1926 #if (CHIPSET == 12) || (CHIPSET == 15)
1927 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1928 #else
1929 * (volatile UWORD16 *) INTH_IT_REG1 &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1930 #endif
1931 #else
1932 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1933 #endif
1934
1935 }
1936 #endif