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comparison cdg211/cdginc/p_cgrlc.h @ 4:56abf6cf8a0b

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cdg211: cdginc/mdf/pdf files from TCS211-20070608
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 26 Sep 2016 01:11:35 +0000
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3:93999a60b835 4:56abf6cf8a0b
1 /*
2 +--------------------------------------------------------------------------+
3 | PROJECT : PROTOCOL STACK |
4 | FILE : p_cgrlc.h |
5 | SOURCE : "__out__\g23m_dfile\prim\cgrlc.pdf" |
6 | LastModified : "2004-05-17" |
7 | IdAndVersion : "8010.119.008.04" |
8 | SrcFileTime : "Mon Apr 24 15:43:20 2006" |
9 | Generated by CCDGEN_2.5.5 on Fri Jun 08 13:59:15 2007 |
10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! |
11 +--------------------------------------------------------------------------+
12 */
13
14 /* PRAGMAS
15 * PREFIX : CGRLC
16 * COMPATIBILITY_DEFINES : NO
17 * ALWAYS_ENUM_IN_VAL_FILE: NO
18 * ENABLE_GROUP: NO
19 * CAPITALIZE_TYPENAME: NO
20 */
21
22
23 #ifndef P_CGRLC_H
24 #define P_CGRLC_H
25
26
27 #define CDG_ENTER__P_CGRLC_H
28
29 #define CDG_ENTER__FILENAME _P_CGRLC_H
30 #define CDG_ENTER__P_CGRLC_H__FILE_TYPE CDGINC
31 #define CDG_ENTER__P_CGRLC_H__LAST_MODIFIED _2004_05_17
32 #define CDG_ENTER__P_CGRLC_H__ID_AND_VERSION _8010_119_008_04
33
34 #define CDG_ENTER__P_CGRLC_H__SRC_FILE_TIME _Mon_Apr_24_15_43_20_2006
35
36 #include "CDG_ENTER.h"
37
38 #undef CDG_ENTER__P_CGRLC_H
39
40 #undef CDG_ENTER__FILENAME
41
42
43 #include "p_cgrlc.val"
44
45 #ifndef __T_CGRLC_fix_alloc_struct__
46 #define __T_CGRLC_fix_alloc_struct__
47 /*
48 * Fixed Allocation structure
49 * CCDGEN:WriteStruct_Count==1211
50 */
51 typedef struct
52 {
53 U8 bitmap_len; /*< 0: 1> Bitmap length */
54 U8 bitmap_array[127]; /*< 1:127> Bitmap array */
55 U32 end_fn; /*<128: 4> End of bitmap framenumber */
56 U8 final_alloc; /*<132: 1> Final allocation */
57 U8 _align0; /*<133: 1> alignment */
58 U8 _align1; /*<134: 1> alignment */
59 U8 _align2; /*<135: 1> alignment */
60 } T_CGRLC_fix_alloc_struct;
61 #endif
62
63 #ifndef __T_CGRLC_freq_param__
64 #define __T_CGRLC_freq_param__
65 /*
66 * Frequency Parameters
67 * CCDGEN:WriteStruct_Count==1212
68 */
69 typedef struct
70 {
71 U16 bcch_arfcn; /*< 0: 2> ARFCN of the BCCH */
72 U8 pdch_hopping; /*< 2: 1> Hopping or no hopping is used on the assigned PDCH */
73 U8 pdch_band; /*< 3: 1> PDCH band */
74 } T_CGRLC_freq_param;
75 #endif
76
77 #ifndef __T_CGRLC_pwr_ctrl_param__
78 #define __T_CGRLC_pwr_ctrl_param__
79 /*
80 * Power Control Parameters
81 * CCDGEN:WriteStruct_Count==1213
82 */
83 typedef struct
84 {
85 U8 alpha; /*< 0: 1> Alpha */
86 U8 gamma_ch[CGRLC_MAX_TIMESLOTS]; /*< 1: 8> Gamma */
87 U8 _align0; /*< 9: 1> alignment */
88 U8 _align1; /*< 10: 1> alignment */
89 U8 _align2; /*< 11: 1> alignment */
90 } T_CGRLC_pwr_ctrl_param;
91 #endif
92
93 #ifndef __T_CGRLC_c_value__
94 #define __T_CGRLC_c_value__
95 /*
96 * C-Value
97 * CCDGEN:WriteStruct_Count==1214
98 */
99 typedef struct
100 {
101 S32 c_lev; /*< 0: 4> C-value raw data level */
102 U16 c_idx; /*< 4: 2> C-value raw data index */
103 U16 c_acrcy; /*< 6: 2> C-value raw data accuracy */
104 } T_CGRLC_c_value;
105 #endif
106
107 #ifndef __T_CGRLC_pan_struct__
108 #define __T_CGRLC_pan_struct__
109 /*
110 * Pan Structure
111 * CCDGEN:WriteStruct_Count==1215
112 */
113 typedef struct
114 {
115 U8 inc; /*< 0: 1> Pan increment */
116 U8 dec; /*< 1: 1> Pan decrement */
117 U8 pmax; /*< 2: 1> Pan maximum */
118 U8 _align0; /*< 3: 1> alignment */
119 } T_CGRLC_pan_struct;
120 #endif
121
122 #ifndef __T_CGRLC_glbl_pwr_ctrl_param__
123 #define __T_CGRLC_glbl_pwr_ctrl_param__
124 /*
125 * Global Power Control Parameters
126 * CCDGEN:WriteStruct_Count==1216
127 */
128 typedef struct
129 {
130 U8 alpha; /*< 0: 1> Alpha */
131 U8 t_avg_t; /*< 1: 1> T_AVG_T */
132 U8 pb; /*< 2: 1> Power reduction value */
133 U8 pc_meas_chan; /*< 3: 1> PC_MEAS_CHAN */
134 U8 pwr_max; /*< 4: 1> Maximum output power of the MS. */
135 U8 _align0; /*< 5: 1> alignment */
136 U8 _align1; /*< 6: 1> alignment */
137 U8 _align2; /*< 7: 1> alignment */
138 } T_CGRLC_glbl_pwr_ctrl_param;
139 #endif
140
141 #ifndef __T_CGRLC_pwr_ctrl__
142 #define __T_CGRLC_pwr_ctrl__
143 /*
144 * Power Control Information
145 * CCDGEN:WriteStruct_Count==1217
146 */
147 typedef struct
148 {
149 U8 _align0; /*< 0: 1> alignment */
150 U8 _align1; /*< 1: 1> alignment */
151 U8 _align2; /*< 2: 1> alignment */
152 U8 v_pwr_ctrl_param; /*< 3: 1> valid-flag */
153 T_CGRLC_pwr_ctrl_param pwr_ctrl_param; /*< 4: 12> Power Control Parameters */
154 U8 _align3; /*< 16: 1> alignment */
155 U8 _align4; /*< 17: 1> alignment */
156 U8 _align5; /*< 18: 1> alignment */
157 U8 v_glbl_pwr_ctrl_param; /*< 19: 1> valid-flag */
158 T_CGRLC_glbl_pwr_ctrl_param glbl_pwr_ctrl_param; /*< 20: 8> Global Power Control Parameters */
159 U8 _align6; /*< 28: 1> alignment */
160 U8 _align7; /*< 29: 1> alignment */
161 U8 _align8; /*< 30: 1> alignment */
162 U8 v_freq_param; /*< 31: 1> valid-flag */
163 T_CGRLC_freq_param freq_param; /*< 32: 4> Frequency Parameters */
164 U8 _align9; /*< 36: 1> alignment */
165 U8 _align10; /*< 37: 1> alignment */
166 U8 _align11; /*< 38: 1> alignment */
167 U8 v_c_value; /*< 39: 1> valid-flag */
168 T_CGRLC_c_value c_value; /*< 40: 8> C-Value */
169 } T_CGRLC_pwr_ctrl;
170 #endif
171
172
173 /*
174 * End of substructure section, begin of primitive definition section
175 */
176
177 #ifndef __T_CGRLC_ENABLE_REQ__
178 #define __T_CGRLC_ENABLE_REQ__
179 /*
180 *
181 * CCDGEN:WriteStruct_Count==1218
182 */
183 typedef struct
184 {
185 U8 enable_cause; /*< 0: 1> Enable Cause */
186 U8 _align0; /*< 1: 1> alignment */
187 U8 _align1; /*< 2: 1> alignment */
188 U8 _align2; /*< 3: 1> alignment */
189 U32 ul_tlli; /*< 4: 4> Uplink TLLI value. */
190 U32 dl_tlli; /*< 8: 4> Downlink TLLI value. */
191 U8 _align3; /*< 12: 1> alignment */
192 U8 _align4; /*< 13: 1> alignment */
193 U8 _align5; /*< 14: 1> alignment */
194 U8 v_pan_struct; /*< 15: 1> valid-flag */
195 T_CGRLC_pan_struct pan_struct; /*< 16: 4> Pan Structure */
196 U8 queue_mode; /*< 20: 1> Type of Queue Mode. */
197 U8 burst_type; /*< 21: 1> Default burst type */
198 U8 ab_type; /*< 22: 1> Default access burst type */
199 U8 t3168_val; /*< 23: 1> T3168 Value */
200 U8 cu_cause; /*< 24: 1> Cell update cause */
201 U8 ac_class; /*< 25: 1> Access control class */
202 U8 change_mark; /*< 26: 1> Change mark value */
203 U8 _align6; /*< 27: 1> alignment */
204 } T_CGRLC_ENABLE_REQ;
205 #endif
206
207 #ifndef __T_CGRLC_DISABLE_REQ__
208 #define __T_CGRLC_DISABLE_REQ__
209 /*
210 *
211 * CCDGEN:WriteStruct_Count==1219
212 */
213 typedef struct
214 {
215 U8 disable_class; /*< 0: 1> Disable class. */
216 U8 prim_status; /*< 1: 1> Primitive Queue Handler. */
217 U8 _align0; /*< 2: 1> alignment */
218 U8 _align1; /*< 3: 1> alignment */
219 } T_CGRLC_DISABLE_REQ;
220 #endif
221
222 #ifndef __T_CGRLC_UL_TBF_RES__
223 #define __T_CGRLC_UL_TBF_RES__
224 /*
225 *
226 * CCDGEN:WriteStruct_Count==1220
227 */
228 typedef struct
229 {
230 U32 starting_time; /*< 0: 4> TBF starting time. */
231 U8 tbf_mode; /*< 4: 1> Type of TBF. */
232 U8 prim_status; /*< 5: 1> Primitive Queue Handler. */
233 U8 polling_bit; /*< 6: 1> Polling bit */
234 U8 cs_mode; /*< 7: 1> Type of Coding Scheme. */
235 U8 mac_mode; /*< 8: 1> Type of MAC mode. */
236 U8 nts_max; /*< 9: 1> Number of Timeslots. */
237 U8 tn_mask; /*< 10: 1> timeslot mask */
238 U8 tfi; /*< 11: 1> TFI value. */
239 U8 ti; /*< 12: 1> TLLI indicator. */
240 U8 bs_cv_max; /*< 13: 1> Maximum Countdown value. */
241 U8 tlli_cs_mode; /*< 14: 1> Type of Coding Scheme in Contention Resolution. */
242 U8 r_bit; /*< 15: 1> R bit */
243 T_CGRLC_fix_alloc_struct fix_alloc_struct; /*< 16:136> Fixed Allocation structure */
244 U16 rlc_db_granted; /*<152: 2> RLCdata block granted */
245 U8 _align0; /*<154: 1> alignment */
246 U8 _align1; /*<155: 1> alignment */
247 T_CGRLC_pwr_ctrl pwr_ctrl; /*<156: 48> Power Control Information */
248 } T_CGRLC_UL_TBF_RES;
249 #endif
250
251 #ifndef __T_CGRLC_DL_TBF_REQ__
252 #define __T_CGRLC_DL_TBF_REQ__
253 /*
254 *
255 * CCDGEN:WriteStruct_Count==1221
256 */
257 typedef struct
258 {
259 U32 starting_time; /*< 0: 4> TBF starting time. */
260 U8 rlc_mode; /*< 4: 1> Type of RLC mode. */
261 U8 cs_mode; /*< 5: 1> Type of Coding Scheme. */
262 U8 mac_mode; /*< 6: 1> Type of MAC mode. */
263 U8 nts_max; /*< 7: 1> Number of Timeslots. */
264 U8 tn_mask; /*< 8: 1> timeslot mask */
265 U8 tfi; /*< 9: 1> TFI value. */
266 U8 t3192_val; /*< 10: 1> Value of T3192. */
267 U8 ctrl_ack_bit; /*< 11: 1> Ctrl ack bit */
268 U8 polling_bit; /*< 12: 1> Polling bit */
269 U8 _align0; /*< 13: 1> alignment */
270 U8 _align1; /*< 14: 1> alignment */
271 U8 _align2; /*< 15: 1> alignment */
272 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 16: 48> Power Control Information */
273 } T_CGRLC_DL_TBF_REQ;
274 #endif
275
276 #ifndef __T_CGRLC_TBF_REL_REQ__
277 #define __T_CGRLC_TBF_REL_REQ__
278 /*
279 *
280 * CCDGEN:WriteStruct_Count==1222
281 */
282 typedef struct
283 {
284 U8 tbf_mode; /*< 0: 1> Type of TBF. */
285 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */
286 U8 _align0; /*< 2: 1> alignment */
287 U8 _align1; /*< 3: 1> alignment */
288 U32 rel_fn; /*< 4: 4> Release after Poll with fn. */
289 } T_CGRLC_TBF_REL_REQ;
290 #endif
291
292 #ifndef __T_CGRLC_TBF_REL_IND__
293 #define __T_CGRLC_TBF_REL_IND__
294 /*
295 *
296 * CCDGEN:WriteStruct_Count==1223
297 */
298 typedef struct
299 {
300 U8 tbf_mode; /*< 0: 1> Type of TBF. */
301 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */
302 U8 _align0; /*< 2: 1> alignment */
303 U8 v_c_value; /*< 3: 1> valid-flag */
304 T_CGRLC_c_value c_value; /*< 4: 8> C-Value */
305 U8 dl_trans_id; /*< 12: 1> DL Assignmnet ID */
306 U8 _align1; /*< 13: 1> alignment */
307 U8 _align2; /*< 14: 1> alignment */
308 U8 _align3; /*< 15: 1> alignment */
309 } T_CGRLC_TBF_REL_IND;
310 #endif
311
312 #ifndef __T_CGRLC_TBF_REL_RES__
313 #define __T_CGRLC_TBF_REL_RES__
314 /*
315 *
316 * CCDGEN:WriteStruct_Count==1224
317 */
318 typedef struct
319 {
320 U8 tbf_mode; /*< 0: 1> Type of TBF. */
321 U8 _align0; /*< 1: 1> alignment */
322 U8 _align1; /*< 2: 1> alignment */
323 U8 _align2; /*< 3: 1> alignment */
324 } T_CGRLC_TBF_REL_RES;
325 #endif
326
327 #ifndef __T_CGRLC_UL_TBF_IND__
328 #define __T_CGRLC_UL_TBF_IND__
329 /*
330 *
331 * CCDGEN:WriteStruct_Count==1225
332 */
333 typedef struct
334 {
335 U8 access_type; /*< 0: 1> Access Type. */
336 U8 ra_prio; /*< 1: 1> Radio priority */
337 U8 nr_blocks; /*< 2: 1> Number of blocks */
338 U8 llc_prim_type; /*< 3: 1> LLC Primitive type */
339 U16 peak; /*< 4: 2> Peak value */
340 U16 rlc_oct_cnt; /*< 6: 2> Number of bytes for TBF */
341 } T_CGRLC_UL_TBF_IND;
342 #endif
343
344 #ifndef __T_CGRLC_DATA_REQ__
345 #define __T_CGRLC_DATA_REQ__
346 /*
347 *
348 * CCDGEN:WriteStruct_Count==1226
349 */
350 typedef struct
351 {
352 U8 blk_owner; /*< 0: 1> Block owner. */
353 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 1: 23> Data Array. */
354 } T_CGRLC_DATA_REQ;
355 #endif
356
357 #ifndef __T_CGRLC_DATA_IND__
358 #define __T_CGRLC_DATA_IND__
359 /*
360 *
361 * CCDGEN:WriteStruct_Count==1227
362 */
363 typedef struct
364 {
365 U32 fn; /*< 0: 4> Received frame number. */
366 U8 tn; /*< 4: 1> Timeslot number */
367 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 5: 23> Data Array. */
368 } T_CGRLC_DATA_IND;
369 #endif
370
371 #ifndef __T_CGRLC_POLL_REQ__
372 #define __T_CGRLC_POLL_REQ__
373 /*
374 *
375 * CCDGEN:WriteStruct_Count==1228
376 */
377 typedef struct
378 {
379 U32 poll_fn; /*< 0: 4> Poll frame number. */
380 U8 tn; /*< 4: 1> Timeslot number */
381 U8 poll_b_type; /*< 5: 1> Poll burst type */
382 U8 ctrl_ack; /*< 6: 1> Ctrl_ack */
383 U8 _align0; /*< 7: 1> alignment */
384 } T_CGRLC_POLL_REQ;
385 #endif
386
387 #ifndef __T_CGRLC_ACCESS_STATUS_REQ__
388 #define __T_CGRLC_ACCESS_STATUS_REQ__
389 /*
390 *
391 * CCDGEN:WriteStruct_Count==1229
392 */
393 typedef struct
394 {
395 U8 dummy; /*< 0: 1> no parameters */
396 } T_CGRLC_ACCESS_STATUS_REQ;
397 #endif
398
399 #ifndef __T_CGRLC_CTRL_MSG_SENT_IND__
400 #define __T_CGRLC_CTRL_MSG_SENT_IND__
401 /*
402 *
403 * CCDGEN:WriteStruct_Count==1230
404 */
405 typedef struct
406 {
407 U8 dummy; /*< 0: 1> no parameters */
408 } T_CGRLC_CTRL_MSG_SENT_IND;
409 #endif
410
411 #ifndef __T_CGRLC_STARTING_TIME_IND__
412 #define __T_CGRLC_STARTING_TIME_IND__
413 /*
414 *
415 * CCDGEN:WriteStruct_Count==1231
416 */
417 typedef struct
418 {
419 U8 tbf_mode; /*< 0: 1> Type of TBF. */
420 U8 tfi; /*< 1: 1> TFI value. */
421 U8 _align0; /*< 2: 1> alignment */
422 U8 _align1; /*< 3: 1> alignment */
423 } T_CGRLC_STARTING_TIME_IND;
424 #endif
425
426 #ifndef __T_CGRLC_T3192_STARTED_IND__
427 #define __T_CGRLC_T3192_STARTED_IND__
428 /*
429 *
430 * CCDGEN:WriteStruct_Count==1232
431 */
432 typedef struct
433 {
434 U8 dummy; /*< 0: 1> no parameters */
435 } T_CGRLC_T3192_STARTED_IND;
436 #endif
437
438 #ifndef __T_CGRLC_CONT_RES_DONE_IND__
439 #define __T_CGRLC_CONT_RES_DONE_IND__
440 /*
441 *
442 * CCDGEN:WriteStruct_Count==1233
443 */
444 typedef struct
445 {
446 U8 dummy; /*< 0: 1> no parameters */
447 } T_CGRLC_CONT_RES_DONE_IND;
448 #endif
449
450 #ifndef __T_CGRLC_TA_VALUE_IND__
451 #define __T_CGRLC_TA_VALUE_IND__
452 /*
453 *
454 * CCDGEN:WriteStruct_Count==1234
455 */
456 typedef struct
457 {
458 U8 ta_value; /*< 0: 1> Timing Advance Value. */
459 U8 _align0; /*< 1: 1> alignment */
460 U8 _align1; /*< 2: 1> alignment */
461 U8 _align2; /*< 3: 1> alignment */
462 } T_CGRLC_TA_VALUE_IND;
463 #endif
464
465 #ifndef __T_CGRLC_STATUS_IND__
466 #define __T_CGRLC_STATUS_IND__
467 /*
468 *
469 * CCDGEN:WriteStruct_Count==1235
470 */
471 typedef struct
472 {
473 U8 failure; /*< 0: 1> Lower layer failure. */
474 U8 _align0; /*< 1: 1> alignment */
475 U8 _align1; /*< 2: 1> alignment */
476 U8 _align2; /*< 3: 1> alignment */
477 } T_CGRLC_STATUS_IND;
478 #endif
479
480 #ifndef __T_CGRLC_TEST_MODE_REQ__
481 #define __T_CGRLC_TEST_MODE_REQ__
482 /*
483 *
484 * CCDGEN:WriteStruct_Count==1236
485 */
486 typedef struct
487 {
488 U16 no_of_pdus; /*< 0: 2> Number of PDUs. */
489 U8 dl_timeslot_offset; /*< 2: 1> Downlink Timeslot Offset. */
490 U8 test_mode_flag; /*< 3: 1> Test mode flag. */
491 } T_CGRLC_TEST_MODE_REQ;
492 #endif
493
494 #ifndef __T_CGRLC_TEST_MODE_CNF__
495 #define __T_CGRLC_TEST_MODE_CNF__
496 /*
497 *
498 * CCDGEN:WriteStruct_Count==1237
499 */
500 typedef struct
501 {
502 U8 dummy; /*< 0: 1> no parameters */
503 } T_CGRLC_TEST_MODE_CNF;
504 #endif
505
506 #ifndef __T_CGRLC_TEST_END_REQ__
507 #define __T_CGRLC_TEST_END_REQ__
508 /*
509 *
510 * CCDGEN:WriteStruct_Count==1238
511 */
512 typedef struct
513 {
514 U8 dummy; /*< 0: 1> no parameters */
515 } T_CGRLC_TEST_END_REQ;
516 #endif
517
518 #ifndef __T_CGRLC_TRIGGER_IND__
519 #define __T_CGRLC_TRIGGER_IND__
520 /*
521 *
522 * CCDGEN:WriteStruct_Count==1239
523 */
524 typedef struct
525 {
526 U8 prim_type; /*< 0: 1> Type of primitive. */
527 U8 _align0; /*< 1: 1> alignment */
528 U8 _align1; /*< 2: 1> alignment */
529 U8 _align2; /*< 3: 1> alignment */
530 } T_CGRLC_TRIGGER_IND;
531 #endif
532
533 #ifndef __T_CGRLC_STANDBY_STATE_IND__
534 #define __T_CGRLC_STANDBY_STATE_IND__
535 /*
536 *
537 * CCDGEN:WriteStruct_Count==1240
538 */
539 typedef struct
540 {
541 U8 dummy; /*< 0: 1> no parameters */
542 } T_CGRLC_STANDBY_STATE_IND;
543 #endif
544
545 #ifndef __T_CGRLC_READY_STATE_IND__
546 #define __T_CGRLC_READY_STATE_IND__
547 /*
548 *
549 * CCDGEN:WriteStruct_Count==1241
550 */
551 typedef struct
552 {
553 U8 dummy; /*< 0: 1> no parameters */
554 } T_CGRLC_READY_STATE_IND;
555 #endif
556
557 #ifndef __T_CGRLC_TA_VALUE_REQ__
558 #define __T_CGRLC_TA_VALUE_REQ__
559 /*
560 *
561 * CCDGEN:WriteStruct_Count==1242
562 */
563 typedef struct
564 {
565 U8 ta_value; /*< 0: 1> Timing Advance Value. */
566 U8 _align0; /*< 1: 1> alignment */
567 U8 _align1; /*< 2: 1> alignment */
568 U8 _align2; /*< 3: 1> alignment */
569 } T_CGRLC_TA_VALUE_REQ;
570 #endif
571
572 #ifndef __T_CGRLC_INT_LEVEL_REQ__
573 #define __T_CGRLC_INT_LEVEL_REQ__
574 /*
575 *
576 * CCDGEN:WriteStruct_Count==1243
577 */
578 typedef struct
579 {
580 U8 ilev[CGRLC_MAX_TIMESLOTS]; /*< 0: 8> Interference level */
581 } T_CGRLC_INT_LEVEL_REQ;
582 #endif
583
584 #ifndef __T_CGRLC_TEST_MODE_IND__
585 #define __T_CGRLC_TEST_MODE_IND__
586 /*
587 *
588 * CCDGEN:WriteStruct_Count==1244
589 */
590 typedef struct
591 {
592 U8 test_mode_flag; /*< 0: 1> Test mode flag. */
593 U8 _align0; /*< 1: 1> alignment */
594 U8 _align1; /*< 2: 1> alignment */
595 U8 _align2; /*< 3: 1> alignment */
596 } T_CGRLC_TEST_MODE_IND;
597 #endif
598
599 #ifndef __T_CGRLC_READY_TIMER_CONFIG_REQ__
600 #define __T_CGRLC_READY_TIMER_CONFIG_REQ__
601 /*
602 *
603 * CCDGEN:WriteStruct_Count==1245
604 */
605 typedef struct
606 {
607 U32 t3314_val; /*< 0: 4> Value of T3314. */
608 } T_CGRLC_READY_TIMER_CONFIG_REQ;
609 #endif
610
611 #ifndef __T_CGRLC_FORCE_TO_STANDBY_REQ__
612 #define __T_CGRLC_FORCE_TO_STANDBY_REQ__
613 /*
614 *
615 * CCDGEN:WriteStruct_Count==1246
616 */
617 typedef struct
618 {
619 U8 dummy; /*< 0: 1> no parameters */
620 } T_CGRLC_FORCE_TO_STANDBY_REQ;
621 #endif
622
623 #ifndef __T_CGRLC_PWR_CTRL_REQ__
624 #define __T_CGRLC_PWR_CTRL_REQ__
625 /*
626 *
627 * CCDGEN:WriteStruct_Count==1247
628 */
629 typedef struct
630 {
631 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 0: 48> Power Control Information */
632 } T_CGRLC_PWR_CTRL_REQ;
633 #endif
634
635 #ifndef __T_CGRLC_PWR_CTRL_CNF__
636 #define __T_CGRLC_PWR_CTRL_CNF__
637 /*
638 *
639 * CCDGEN:WriteStruct_Count==1248
640 */
641 typedef struct
642 {
643 U8 dummy; /*< 0: 1> no parameters */
644 } T_CGRLC_PWR_CTRL_CNF;
645 #endif
646
647
648 #include "CDG_LEAVE.h"
649
650
651 #endif