comparison cdg211/prim/cgrlc.pdf @ 4:56abf6cf8a0b

cdg211: cdginc/mdf/pdf files from TCS211-20070608
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 26 Sep 2016 01:11:35 +0000
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1 ;********************************************************************************
2 ;*** File : cgrlc.pdf
3 ;*** Creation : Fri Jun 08 13:57:33 CST 2007
4 ;*** XSLT Processor : Apache Software Foundation / http://xml.apache.org/xalan-j / supports XSLT-Ver: 1
5 ;*** Copyright : (c) Texas Instruments AG, Berlin Germany 2002
6 ;********************************************************************************
7 ;*** Document Type : Service Access Point Specification
8 ;*** Document Name : cgrlc
9 ;*** Document No. : 8010.119.008.04
10 ;*** Document Date : 2004-05-17
11 ;*** Document Status: BEING_PROCESSED
12 ;*** Document Author: SAB
13 ;********************************************************************************
14
15
16
17 PRAGMA SRC_FILE_TIME "Mon Apr 24 15:43:20 2006"
18 PRAGMA LAST_MODIFIED "2004-05-17"
19 PRAGMA ID_AND_VERSION "8010.119.008.04"
20 PRAGMA PREFIX CGRLC ; Prefix for this document
21 PRAGMA ALLWAYS_ENUM_IN_VAL_FILE NO ; Adds enumerations in the .val file.
22 PRAGMA ENABLE_GROUP NO ; Disable h-file grouping
23 PRAGMA COMPATIBILITY_DEFINES NO ; Compatible to the old #defines
24
25
26
27 CONST MAX_CTRL_MSG_SIZE 23 ; Maximum size of a control message in bytes.
28 CONST MAX_TIMESLOTS 8 ; Maximum number of timeslots
29
30
31
32 VALTAB VAL_access_type
33 VAL 0 AT_NULL "No access is required"
34 VAL 1 AT_ONE_PHASE "One phase access requested."
35 VAL 2 AT_TWO_PHASE "Two phase access requested."
36 VAL 3 AT_SHORT_ACCESS "Short access requested."
37 VAL 4 AT_PAGE_RESPONSE "Page response requested."
38 VAL 5 AT_CELL_UPDATE "Access for cell update primitive requested."
39 VAL 6 AT_MM_PROCEDURE "Access for MM/GMM primitive requested."
40 VAL 7 AT_SINGLE_BLOCK "Only used in GRR: access for single block without TBF"
41
42 VALTAB VAL_dl_timeslot_offset
43 VAL 0 TEST_TN0 "Downlink timeslot offset 0."
44 VAL 1 TEST_TN1 "Downlink timeslot offset 1."
45 VAL 2 TEST_TN2 "Downlink timeslot offset 2."
46 VAL 3 TEST_TN3 "Downlink timeslot offset 3."
47 VAL 4 TEST_TN4 "Downlink timeslot offset 4."
48 VAL 5 TEST_TN5 "Downlink timeslot offset 5."
49 VAL 6 TEST_TN6 "Downlink timeslot offset 6."
50 VAL 7 TEST_TN7 "Downlink timeslot offset 7."
51
52 VALTAB VAL_failure
53 VAL 0 ACCESS_2_NETWORK_NOT_ALLOWED "Access to the network is not allowed."
54 VAL 1 PACKET_ACCESS_FAILURE "Failure during packet access procedure, e.g. T3162 expired."
55 VAL 2 RLC_MAC_ERROR "T3168 expires during contention resolution."
56 VAL 3 TLLI_MISMATCH "TLLI mismatch has occurred."
57 VAL 4 TBF_ESTABLISHMENT_FAILURE "T3164 expires or failure occurs due to any other reason."
58 VAL 5 RESUMPTION_FAILURE "Resumption failure after dedicated mode was left."
59 VAL 6 CONTENTION_RESOLUTION_FAILED "Contention Resolution has failed."
60
61 VALTAB VAL_prim_status
62 VAL 0 PRIM_STATUS_NULL "No primitives shall be deleted."
63 VAL 1 PRIM_STATUS_ONE "One primitive shall be deleted."
64 VAL 2 PRIM_STATUS_TBF "All primitives, which belongs to the current TBF, shall be deleted."
65 VAL 0xFF PRIM_STATUS_ALL "All primitives shall be deleted."
66
67 VALTAB VAL_prim_type
68 VAL 0 PRIM_TYPE_GMM "At least one GMM primitive was confirmed."
69 VAL 1 PRIM_TYPE_OTHER "No GMM primitive was confirmed. Other User data was confirmed."
70
71 VALTAB VAL_tbf_rel_cause
72 VAL 0 TBF_REL_NORMAL "Normal TBF release is or shall be performed."
73 VAL 1 TBF_REL_ABNORMAL "Abnormal TBF release is or shall be performed."
74 VAL 2 TBF_REL_CR_FAILED "Contention resolution failed"
75 VAL 3 TBF_REL_WITH_CELL_RESELECT "TBF release with cell reselection"
76
77 VALTAB VAL_starting_time
78 VAL 0xFFFFFFFF STARTING_TIME_NOT_PRESENT "No TBF starting time present."
79
80 VALTAB VAL_test_mode_flag
81 VAL 0 TEST_RANDOM "Pseudo random data."
82 VAL 1 LOOP "Loop back."
83 VAL 0xFE TEST_MODE_RELEASE "used in GRLC, intermediate status during release procedure"
84 VAL 0xFF NO_TEST_MODE "No testmode active"
85
86 VALTAB VAL_ti
87 VAL 0 TLLI_NOT_PRESENT "TLLI shall not be sent in the RLC data block."
88 VAL 1 TLLI_PRESENT "TLLI shall be sent in the RLC data block."
89
90 VALTAB VAL_cs_mode
91 VAL 0 CS_MODE_1 "Coding scheme 1."
92 VAL 1 CS_MODE_2 "Coding scheme 2."
93 VAL 2 CS_MODE_3 "Coding scheme 3."
94 VAL 3 CS_MODE_4 "Coding scheme 4."
95
96 VALTAB VAL_tlli_cs_mode
97 VAL 0 TLLI_CS_MODE_1 "CS 1 shall be used during Contention resolution."
98 VAL 1 TLLI_CS_MODE_DEF "Default coding scheme shall be used during Contention resolution."
99
100 VALTAB VAL_mac_mode
101 VAL 0 MAC_MODE_DA "Dynamic allocation."
102 VAL 1 MAC_MODE_EDA "Extended dynamic allocation."
103 VAL 2 MAC_MODE_FA "Fixed allocation."
104 VAL 3 MAC_MODE_FA_HD "Fixed allocation, half duplex mode."
105
106 VALTAB VAL_queue_mode
107 VAL 0 QUEUE_MODE_DEFAULT "Use current queue."
108 VAL 1 QUEUE_MODE_GMM "Use GMM queue (RAU procedure)."
109 VAL 2 QUEUE_MODE_LLC "Use LLC queue."
110
111 VALTAB VAL_rlc_mode
112 VAL 0 RLC_MODE_ACK "RLC acknowledged mode."
113 VAL 1 RLC_MODE_UACK "RLC unacknowledged mode."
114
115 VALTAB VAL_tbf_mode
116 VAL 0 TBF_MODE_NULL "No tbf active, used in GRR"
117 VAL 1 TBF_MODE_ACCESS_FAILED "Access has failed. GRLC handles prim queue."
118 VAL 2 TBF_MODE_DL "Downlink TBF is assigned/released."
119 VAL 3 TBF_MODE_UL "Uplink TBF is assigned/released."
120 VAL 4 TBF_MODE_TMA "Uplink TBF for Testmode A is assigned."
121 VAL 5 TBF_MODE_TMB "Uplink TBF for Testmode B is assigned."
122 VAL 6 TBF_MODE_DL_UL "Uplink and Downlink TBF assigned/released."
123 VAL 7 TBF_MODE_ESTABLISHMENT_FAILURE "T3164 expires or failure occurs due to any other reason"
124
125 VALTAB VAL_rxlev
126 VAL 0x00 RXLEV_MIN "Minimum receive signal level value."
127 VAL 0x3F RXLEV_MAX "Maximum receive signal level value."
128 VAL 0x80 RXLEV_NONE "Specific value used to indicate that no new RX value is present or RX value is invalid."
129
130 VALTAB VAL_alpha
131 VAL 0xFF ALPHA_INVALID "No alpha value is available."
132
133 VALTAB VAL_pc_meas_chan
134 VAL 0 MEAS_CHAN_BCCH "Downlink measurements for power control shall be made on BCCH."
135 VAL 1 MEAS_CHAN_PDCH "Downlink measurements for power control shall be made on PDCH."
136
137 VALTAB VAL_gamma_ch
138 VAL 0xFF GAMMA_INVALID "No GCH is available."
139
140 VALTAB VAL_disable_class
141 VAL 0 DISABLE_CLASS_NULL "Initial state of the disable class"
142 VAL 1 DISABLE_CLASS_OTHER "Any other cause for disable class"
143 VAL 2 DISABLE_CLASS_CR "Disable cause is cell reselection"
144
145 VALTAB VAL_poll_b_type
146 VAL 0 POLL_NONE "No poll position present,only in grlc"
147 VAL 1 POLL_COLLISION "Collision detected, only in grlc"
148 VAL 2 POLL_DATA "Poll for dl ack/nack, only in grlc"
149 VAL 3 POLL_UACK "Poll for pca uplink tbf relaase"
150 VAL 4 POLL_CTRL "Default poll for control msg."
151 VAL 5 POLL_RES_NB "Poll for normal burst with packet polling req"
152 VAL 6 POLL_RES_AB "Poll for access burst with packet polling req"
153
154 VALTAB VAL_burst_type
155 VAL 0 BURST_TYPE_AB "Access burst"
156 VAL 1 BURST_TYPE_NB "Normal burst"
157
158 VALTAB VAL_ab_type
159 VAL 0 AB_8_BIT "8 bit access burst"
160 VAL 1 AB_11_BIT "11 bit access burst"
161
162 VALTAB VAL_blk_owner
163 VAL 0 BLK_OWNER_CTRL "Owner is service ctrl (GRR)."
164 VAL 1 BLK_OWNER_CS "Owner is service cs (GRR)."
165 VAL 2 BLK_OWNER_TM "Owner is service tm (GRLC)."
166 VAL 3 BLK_OWNER_MEAS "Owner is service meas (GRR)."
167 VAL 4 BLK_OWNER_NONE "Owner is not specified"
168
169 VALTAB VAL_cu_cause
170 VAL 0 RA_DEFAULT "No action required"
171 VAL 1 RA_CU "Next packet access cause will be cell update"
172
173 VALTAB VAL_pmax
174 VAL 0xFF NO_UPDATE_N3102 "N3102 shall not be updated"
175
176 VALTAB VAL_llc_prim_type
177 VAL 0 LLC_PRIM_TYPE_NULL "No primitive available"
178 VAL 1 LLC_PRIM_TYPE_DATA_REQ "GRLC_DATA_REQ"
179 VAL 2 LLC_PRIM_TYPE_UNITDATA_REQ "GRLC_UNITDATA_REQ"
180
181 VALTAB VAL_ac_class
182 VAL 0 - 7 "Allowed Radio priority"
183 VAL 8 CCCH_AC_NOT_ALLOWED "CCCH access control class not allowed"
184 VAL 9 PCCCH_AC_NOT_ALLOWED "PCCCH access control class not allowed"
185 VAL 10 PCCCH_AC_ALLOWED "PCCCH access control class allowed"
186
187 VALTAB VAL_enable_cause
188 VAL 0 ENAC_NORMAL "Normal Operation"
189 VAL 1 ENAC_ABNORM_RELEASE_CRESELECT_FAILED "Abnormal Release with Cell Re-Selection has Failed"
190
191 VALTAB VAL_rlc_db_granted
192 VAL 0 - 255 "Close ended tbf"
193 VAL 0 OPEN_ENDED_TBF "Open ended tbf"
194
195 VALTAB VAL_t3314_val
196 VAL 0x0 - 0xFFFFFFFF "Values Range"
197 VAL 0x00000000 STANDBY "MS always in STANDBY state."
198 VAL 0x0000ABE0 T3314_DEFAULT "Default timeout value for T3314."
199 VAL 0xFFFFFFFF DEACTIVATED "MS always in READY state."
200
201 VALTAB VAL_pdch_band
202 VAL 0 GSM_400 "GSM 400MHz Band."
203 VAL 1 GSM_850 "GSM 850MHz Band."
204 VAL 2 GSM_900 "GSM 900MHz Band."
205 VAL 3 DCS_1800 "DCS 1800MHz Band."
206 VAL 4 PCS_1900 "PCS 1900MHz Band."
207
208 VALTAB VAL_ilev
209 VAL 0x00 ILEV_MIN "Minimum interference level value."
210 VAL 0x3F ILEV_MAX "Maximum interference level value."
211 VAL 0x80 ILEV_NONE "Specific value used to indicate that no new interference level value is present or interference level value is invalid."
212
213
214
215
216 VAR access_type "Access Type." B
217
218 VAL @p_cgrlc - VAL_access_type@
219
220 VAR data_array "Data Array." B
221
222
223 VAR bitmap_array "Bitmap array" B
224
225
226 VAR dl_timeslot_offset "Downlink Timeslot Offset." B
227
228 VAL @p_cgrlc - VAL_dl_timeslot_offset@
229
230 VAR tn_mask "timeslot mask" B
231
232
233 VAR tn "Timeslot number" B
234
235 VAL @p_cgrlc - VAL_dl_timeslot_offset@
236
237 VAR failure "Lower layer failure." B
238
239 VAL @p_cgrlc - VAL_failure@
240
241 VAR bs_cv_max "Maximum Countdown value." B
242
243
244 VAR no_of_pdus "Number of PDUs." S
245
246
247 VAR nts_max "Number of Timeslots." B
248
249
250 VAR prim_status "Primitive Queue Handler." B
251
252 VAL @p_cgrlc - VAL_prim_status@
253
254 VAR prim_type "Type of primitive." B
255
256 VAL @p_cgrlc - VAL_prim_type@
257
258 VAR tbf_rel_cause "TBF Release Cause." B
259
260 VAL @p_cgrlc - VAL_tbf_rel_cause@
261
262 VAR starting_time "TBF starting time." L
263
264 VAL @p_cgrlc - VAL_starting_time@
265
266 VAR rel_fn "Release after Poll with fn." L
267
268 VAL @p_cgrlc - VAL_starting_time@
269
270 VAR fn "Received frame number." L
271
272 VAL @p_cgrlc - VAL_starting_time@
273
274 VAR poll_fn "Poll frame number." L
275
276 VAL @p_cgrlc - VAL_starting_time@
277
278 VAR end_fn "End of bitmap framenumber" L
279
280 VAL @p_cgrlc - VAL_starting_time@
281
282 VAR test_mode_flag "Test mode flag." B
283
284 VAL @p_cgrlc - VAL_test_mode_flag@
285
286 VAR tfi "TFI value." B
287
288
289 VAR ta_value "Timing Advance Value." B
290
291
292 VAR ti "TLLI indicator." B
293
294 VAL @p_cgrlc - VAL_ti@
295
296 VAR ul_tlli "Uplink TLLI value." L
297
298
299 VAR dl_tlli "Downlink TLLI value." L
300
301
302 VAR cs_mode "Type of Coding Scheme." B
303
304 VAL @p_cgrlc - VAL_cs_mode@
305
306 VAR tlli_cs_mode "Type of Coding Scheme in Contention Resolution." B
307
308 VAL @p_cgrlc - VAL_tlli_cs_mode@
309
310 VAR mac_mode "Type of MAC mode." B
311
312 VAL @p_cgrlc - VAL_mac_mode@
313
314 VAR queue_mode "Type of Queue Mode." B
315
316 VAL @p_cgrlc - VAL_queue_mode@
317
318 VAR rlc_mode "Type of RLC mode." B
319
320 VAL @p_cgrlc - VAL_rlc_mode@
321
322 VAR tbf_mode "Type of TBF." B
323
324 VAL @p_cgrlc - VAL_tbf_mode@
325
326 VAR t3192_val "Value of T3192." B
327
328
329 VAR t3314_val "Value of T3314." L
330
331 VAL @p_cgrlc - VAL_t3314_val@
332
333 VAR t3168_val "T3168 Value" B
334
335
336 VAR ilev "Interference level" B
337
338 VAL @p_cgrlc - VAL_ilev@
339
340 VAR pb "Power reduction value" B
341
342
343 VAR alpha "Alpha" B
344
345 VAL @p_cgrlc - VAL_alpha@
346
347 VAR pc_meas_chan "PC_MEAS_CHAN" B
348
349 VAL @p_cgrlc - VAL_pc_meas_chan@
350
351 VAR t_avg_t "T_AVG_T" B
352
353
354 VAR gamma_ch "Gamma" B
355
356 VAL @p_cgrlc - VAL_gamma_ch@
357
358 VAR bcch_arfcn "ARFCN of the BCCH" S
359
360
361 VAR pdch_hopping "Hopping or no hopping is used on the assigned PDCH" B
362
363
364 VAR disable_class "Disable class." B
365
366 VAL @p_cgrlc - VAL_disable_class@
367
368 VAR ra_prio "Radio priority" B
369
370
371 VAR poll_b_type "Poll burst type" B
372
373 VAL @p_cgrlc - VAL_poll_b_type@
374
375 VAR ctrl_ack "Ctrl_ack" B
376
377
378 VAR burst_type "Default burst type" B
379
380 VAL @p_cgrlc - VAL_burst_type@
381
382 VAR ab_type "Default access burst type" B
383
384 VAL @p_cgrlc - VAL_ab_type@
385
386 VAR inc "Pan increment" B
387
388
389 VAR dec "Pan decrement" B
390
391
392 VAR ctrl_ack_bit "Ctrl ack bit" B
393
394
395 VAR blk_owner "Block owner." B
396
397 VAL @p_cgrlc - VAL_blk_owner@
398
399 VAR nr_blocks "Number of blocks" B
400
401
402 VAR cu_cause "Cell update cause" B
403
404 VAL @p_cgrlc - VAL_cu_cause@
405
406 VAR pmax "Pan maximum" B
407
408 VAL @p_cgrlc - VAL_pmax@
409
410 VAR llc_prim_type "LLC Primitive type" B
411
412 VAL @p_cgrlc - VAL_llc_prim_type@
413
414 VAR peak "Peak value" S
415
416
417 VAR polling_bit "Polling bit" B
418
419
420 VAR rlc_oct_cnt "Number of bytes for TBF" S
421
422
423 VAR r_bit "R bit" B
424
425
426 VAR ac_class "Access control class" B
427
428 VAL @p_cgrlc - VAL_ac_class@
429
430 VAR pwr_max "Maximum output power of the MS." B
431
432
433 VAR c_lev "C-value raw data level" M
434
435
436 VAR c_idx "C-value raw data index" S
437
438
439 VAR c_acrcy "C-value raw data accuracy" S
440
441
442 VAR bitmap_len "Bitmap length" B
443
444
445 VAR final_alloc "Final allocation" B
446
447
448 VAR enable_cause "Enable Cause" B
449
450 VAL @p_cgrlc - VAL_enable_cause@
451
452 VAR change_mark "Change mark value" B
453
454
455 VAR rlc_db_granted "RLCdata block granted" S
456
457 VAL @p_cgrlc - VAL_rlc_db_granted@
458
459 VAR pdch_band "PDCH band" B
460
461 VAL @p_cgrlc - VAL_pdch_band@
462
463 VAR dl_trans_id "DL Assignmnet ID" B
464
465
466
467
468
469 COMP fix_alloc_struct "Fixed Allocation structure"
470 {
471 bitmap_len ; Bitmap length
472 bitmap_array [127] ; Bitmap array
473 end_fn ; End of bitmap framenumber
474 final_alloc ; Final allocation
475 }
476
477
478
479 COMP freq_param "Frequency Parameters"
480 {
481 bcch_arfcn ; ARFCN of the BCCH
482 pdch_hopping ; Hopping or no hopping is used on the assigned PDCH
483 pdch_band ; PDCH band
484 }
485
486
487
488 COMP pwr_ctrl_param "Power Control Parameters"
489 {
490 alpha ; Alpha value
491 gamma_ch [MAX_TIMESLOTS] ; Gamma value for each timeslot
492 }
493
494
495
496 COMP c_value "C-Value"
497 {
498 c_lev ; C-value raw data level
499 c_idx ; C-value raw data index
500 c_acrcy ; C-value raw data accuracy
501 }
502
503
504
505 COMP pan_struct "Pan Structure"
506 {
507 inc ; Pan increment
508 dec ; Pan decrement
509 pmax ; Pan maximum
510 }
511
512
513
514 COMP glbl_pwr_ctrl_param "Global Power Control Parameters"
515 {
516 alpha ; Alpha value
517 t_avg_t ; T_AVG_T
518 pb ; Power reduction value
519 pc_meas_chan ; PC_MEAS_CHAN
520 pwr_max ; Maximum output power of the MS.
521 }
522
523
524
525 COMP pwr_ctrl "Power Control Information"
526 {
527 < () pwr_ctrl_param > ; Power Control Parameters
528 < () glbl_pwr_ctrl_param > ; Global Power Control Parameters
529 < () freq_param > ; Frequency Parameters
530 < () c_value > ; C-Value
531 }
532
533
534
535
536
537
538 ; CGRLC_ENABLE_REQ 0x80000098
539 ; CGRLC_DISABLE_REQ 0x80010098
540 ; CGRLC_UL_TBF_RES 0x80020098
541 ; CGRLC_DL_TBF_REQ 0x80030098
542 ; CGRLC_TBF_REL_REQ 0x80040098
543 ; CGRLC_TBF_REL_IND 0x80004098
544 ; CGRLC_TBF_REL_RES 0x80050098
545 ; CGRLC_UL_TBF_IND 0x80014098
546 ; CGRLC_DATA_REQ 0x80060098
547 ; CGRLC_DATA_IND 0x80024098
548 ; CGRLC_POLL_REQ 0x80070098
549 ; CGRLC_ACCESS_STATUS_REQ 0x80080098
550 ; CGRLC_CTRL_MSG_SENT_IND 0x80034098
551 ; CGRLC_STARTING_TIME_IND 0x80044098
552 ; CGRLC_T3192_STARTED_IND 0x80054098
553 ; CGRLC_CONT_RES_DONE_IND 0x80064098
554 ; CGRLC_TA_VALUE_IND 0x80074098
555 ; CGRLC_STATUS_IND 0x80084098
556 ; CGRLC_TEST_MODE_REQ 0x80090098
557 ; CGRLC_TEST_MODE_CNF 0x80094098
558 ; CGRLC_TEST_END_REQ 0x800A0098
559 ; CGRLC_TRIGGER_IND 0x800A4098
560 ; CGRLC_STANDBY_STATE_IND 0x800B4098
561 ; CGRLC_READY_STATE_IND 0x800C4098
562 ; CGRLC_TA_VALUE_REQ 0x800B0098
563 ; CGRLC_INT_LEVEL_REQ 0x800C0098
564 ; CGRLC_TEST_MODE_IND 0x800E4098
565 ; CGRLC_READY_TIMER_CONFIG_REQ 0x800E0098
566 ; CGRLC_FORCE_TO_STANDBY_REQ 0x800F0098
567 ; CGRLC_PWR_CTRL_REQ 0x800D0098
568 ; CGRLC_PWR_CTRL_CNF 0x800D4098
569
570
571
572 PRIM CGRLC_ENABLE_REQ 0x80000098
573 {
574 enable_cause ; Enable Cause
575 ul_tlli ; Uplink TLLI value
576 dl_tlli ; Downlink TLLI value
577 < () pan_struct > ; Pan Structure
578 queue_mode ; Type of Queue Mode
579 burst_type ; Default bust type
580 ab_type ; Default Access bust type
581 t3168_val ; T3168 Value
582 cu_cause ; Cell update cause
583 ac_class ; Access control class
584 change_mark ; Change mark value
585 }
586
587
588
589
590
591
592 PRIM CGRLC_DISABLE_REQ 0x80010098
593 {
594 disable_class ; Disable Class
595 prim_status ; Primitive Queue Handler
596 }
597
598
599
600
601
602
603 PRIM CGRLC_UL_TBF_RES 0x80020098
604 {
605 starting_time ; TBF starting time
606 tbf_mode ; Type of TBF
607 prim_status ; Primitive Queue Handler
608 polling_bit ; Polling bit
609 cs_mode ; Type of Coding Scheme
610 mac_mode ; Type of MAC mode
611 nts_max ; Number of Timeslots
612 tn_mask ; Timeslot mask
613 tfi ; TFI value
614 ti ; TLLI indicator
615 bs_cv_max ; Maximum Countdown value
616 tlli_cs_mode ; Type of Coding Scheme in Contention Resolution
617 r_bit ; R bit
618 fix_alloc_struct ; Fixed Allocation structure
619 rlc_db_granted ; RLCdata block granted
620 pwr_ctrl ; Power Control Information
621 }
622
623
624
625
626
627
628 PRIM CGRLC_DL_TBF_REQ 0x80030098
629 {
630 starting_time ; TBF starting time
631 rlc_mode ; Type of RLC mode
632 cs_mode ; Type of Coding Scheme
633 mac_mode ; Type of MAC mode
634 nts_max ; Number of Timeslots
635 tn_mask ; Timeslot mask
636 tfi ; TFI value
637 t3192_val ; Value of timer T3192
638 ctrl_ack_bit ; Ctrl ack bit
639 polling_bit ; Polling bit
640 pwr_ctrl ; Power Control Information
641 }
642
643
644
645
646
647
648 PRIM CGRLC_TBF_REL_REQ 0x80040098
649 {
650 tbf_mode ; Type of TBF
651 tbf_rel_cause ; TBF Release Cause
652 rel_fn ; Release after Poll with fn
653 }
654
655
656
657
658
659
660 PRIM CGRLC_TBF_REL_IND 0x80004098
661 {
662 tbf_mode ; Type of TBF
663 tbf_rel_cause ; TBF Release Cause
664 < () c_value > ; Power Control Information
665 dl_trans_id ; DL Assignment Id
666 }
667
668
669
670
671
672
673 PRIM CGRLC_TBF_REL_RES 0x80050098
674 {
675 tbf_mode ; Type of TBF
676 }
677
678
679
680
681
682
683 PRIM CGRLC_UL_TBF_IND 0x80014098
684 {
685 access_type ; Access Type
686 ra_prio ; Radio Priority
687 nr_blocks ; Number of blocks
688 llc_prim_type ; LLC Primitive type
689 peak ; Peak value
690 rlc_oct_cnt ; RLC octet count
691 }
692
693
694
695
696
697
698 PRIM CGRLC_DATA_REQ 0x80060098
699 {
700 blk_owner ; Block Owner
701 data_array [MAX_CTRL_MSG_SIZE] ; Data array
702 }
703
704
705
706
707
708
709 PRIM CGRLC_DATA_IND 0x80024098
710 {
711 fn ; Received frame number
712 tn ; Timeslot number
713 data_array [MAX_CTRL_MSG_SIZE] ; Data array
714 }
715
716
717
718
719
720
721 PRIM CGRLC_POLL_REQ 0x80070098
722 {
723 poll_fn ; Poll frame number
724 tn ; Timeslot number
725 poll_b_type ; Poll burst type
726 ctrl_ack ; Ctrl_ack
727 }
728
729
730
731
732
733
734 PRIM CGRLC_ACCESS_STATUS_REQ 0x80080098
735 {
736 }
737
738
739
740
741
742
743 PRIM CGRLC_CTRL_MSG_SENT_IND 0x80034098
744 {
745 }
746
747
748
749
750
751
752 PRIM CGRLC_STARTING_TIME_IND 0x80044098
753 {
754 tbf_mode ; Type of TBF
755 tfi ; TFI value
756 }
757
758
759
760
761
762
763 PRIM CGRLC_T3192_STARTED_IND 0x80054098
764 {
765 }
766
767
768
769
770
771
772 PRIM CGRLC_CONT_RES_DONE_IND 0x80064098
773 {
774 }
775
776
777
778
779
780
781 PRIM CGRLC_TA_VALUE_IND 0x80074098
782 {
783 ta_value ; Timing Advance Value
784 }
785
786
787
788
789
790
791 PRIM CGRLC_STATUS_IND 0x80084098
792 {
793 failure ; Lower layer failure
794 }
795
796
797
798
799
800
801 PRIM CGRLC_TEST_MODE_REQ 0x80090098
802 {
803 no_of_pdus ; Number of PDUs
804 dl_timeslot_offset ; Downlink Timeslot Offset
805 test_mode_flag ; Test Mode Flag
806 }
807
808
809
810
811
812
813 PRIM CGRLC_TEST_MODE_CNF 0x80094098
814 {
815 }
816
817
818
819
820
821
822 PRIM CGRLC_TEST_END_REQ 0x800A0098
823 {
824 }
825
826
827
828
829
830
831 PRIM CGRLC_TRIGGER_IND 0x800A4098
832 {
833 prim_type ; Type of primitive
834 }
835
836
837
838
839
840
841 PRIM CGRLC_STANDBY_STATE_IND 0x800B4098
842 {
843 }
844
845
846
847
848
849
850 PRIM CGRLC_READY_STATE_IND 0x800C4098
851 {
852 }
853
854
855
856
857
858
859 PRIM CGRLC_TA_VALUE_REQ 0x800B0098
860 {
861 ta_value ; Timing Advance Value
862 }
863
864
865
866
867
868
869 PRIM CGRLC_INT_LEVEL_REQ 0x800C0098
870 {
871 ilev [MAX_TIMESLOTS] ; Interference Level
872 }
873
874
875
876
877
878
879 PRIM CGRLC_TEST_MODE_IND 0x800E4098
880 {
881 test_mode_flag ; indicate the type of testmode
882 }
883
884
885
886
887
888
889 PRIM CGRLC_READY_TIMER_CONFIG_REQ 0x800E0098
890 {
891 t3314_val ; Primitive Item
892 }
893
894
895
896
897
898
899 PRIM CGRLC_FORCE_TO_STANDBY_REQ 0x800F0098
900 {
901 }
902
903
904
905
906
907
908 PRIM CGRLC_PWR_CTRL_REQ 0x800D0098
909 {
910 pwr_ctrl ; Power Control Information
911 }
912
913
914
915
916
917
918 PRIM CGRLC_PWR_CTRL_CNF 0x800D4098
919 {
920 }
921
922
923
924
925
926
927
928
929