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comparison src/cs/system/template/gsm_ds_pirelli_ram.template @ 90:7bd197063b9e

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building RAM fw images for the Pirelli: initial concept
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 02 Oct 2016 16:51:22 +0000
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children a1ed3269da48
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89:6c3881378a31 90:7bd197063b9e
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 * This version of the linker script template has been concocted
9 * by Spacefalcon the Outlaw based on previous hacks.
10 */
11
12 -c /* Autoinitialize variables at runtime */
13
14 /*********************************/
15 /* SPECIFY THE SYSTEM MEMORY MAP */
16 /*********************************/
17
18 MEMORY
19 {
20 /* using XRAM instead of flash */
21 /* Interrupt Vectors Table */
22 I_MEM (RXI) : org = 0x01000000 len = 0x00000100
23
24 /* Boot Sector */
25 B_MEM (RXI) : org = 0x01000100 len = 0x00001f00
26
27 /* Magic Word for Calypso Boot ROM */
28 MWC_MEM (RXI) : org = 0x01002000 len = 0x00000004 fill = 0x0000001
29
30 /* Program Memory */
31 P_MEM1 (RXI) : org = 0x01004000 len = 0x00000700
32 P_MEM2 (RXI) : org = 0x01004700 len = 0x00000004
33 P_MEM3 (RXI) : org = 0x01004704 len = 0x003fb8fc
34
35 /* FFS Area */
36 FFS_MEM (RX) : org = 0x02000000 len = 0x00800000
37 /**************************************************************************/
38
39 /* CS1: External SRAM 1 Mbytes ********************************************/
40 /* Data Memory */
41
42 /*
43 * Huge XRAM on the Pirelli: present it as two banks of 4 MiB each
44 * ... or a little less since we just stole half of it for "flash"
45 */
46
47 D_MEM1 (RW) : org = 0x01400000 len = 0x00380000
48 D_MEM2 (RW) : org = 0x01780000 len = 0x00080000
49 /**************************************************************************/
50
51 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
52 /* Code & Variables Memory */
53 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
54 /**************************************************************************/
55 }
56
57 /***********************************************/
58 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
59 /***********************************************/
60
61 /*
62 * Since the bootloader directly calls the INT_Initialize() routine located
63 * in int.s, this int.s code must always be mapped at the same address
64 * (usually in the second flash sector). Its length is about 0x500 bytes.
65 * Then comes the code that need to be loaded into the internal RAM.
66 */
67
68 SECTIONS
69 {
70 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
71 .monitor : > B_MEM /* Monitor Constants & Code */
72 {
73 $(CONST_BOOT_LIB)
74 }
75
76 .inttext : {} > P_MEM1 /* int.s Code */
77
78 .bss_dar : > D_MEM1 /* DAR SWE Variables */
79 {
80 $(BSS_DAR_LIB)
81 }
82
83 /*
84 * The .bss section should not be split to ensure it is initialized to 0
85 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
86 * or in D_MEM2.
87 *
88 * Falcon's note for K5A3281: see the comments above where the memory
89 * regions are defined.
90 */
91
92 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
93 {
94 $(BSS_BOOT_LIB)
95 }
96
97 /*
98 * All .bss sections, which must be mapped in internal RAM must be
99 * grouped in order to initialized the corresponding memory to 0.
100 * This initialization is done in int.s file before calling the Nucleus
101 * routine.
102 */
103
104 GROUP
105 {
106 S_D_Mem /* Label of start address of .bss section in Int. RAM */
107 .DintMem
108 {
109
110 /*
111 * .bss sections of the application
112 */
113
114 $(BSS_LIBS)
115
116 }
117
118 API_HISR_stack : {}
119
120 E_D_Mem /* Label of end address of .bss section in Int. RAM */
121 } > S_MEM
122
123 /*
124 * .text and .const sections which must be mapped in internal RAM.
125 */
126
127 .ldfl : {} > P_MEM2 /* Used to know the start load address */
128 GROUP load = P_MEM3, run = S_MEM
129 {
130 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
131 .PIntMem
132 {
133 /*
134 * .text and .const sections of the application.
135 *
136 * The .veneer sections correspond exactly to .text:v&n sections
137 * implementing the veneer functions. The .text:v$n -> .veneer
138 * translation is performed by PTOOL software when PTOOL_OPTIONS
139 * environement variable is set to veneer_section.
140 */
141
142 $(CONST_LIBS)
143
144 }
145 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
146 }
147
148 /*
149 * The rest of the code is mapped in flash, however the trampolines
150 * load address should be consistent with .text.
151 */
152 COMMENT2START
153 `trampolines load = P_MEM3, run = S_MEM
154 COMMENT2END
155
156 .text : {} > P_MEM3 /* Code */
157
158 /*
159 * The rest of the constants is mapped in flash.
160 * The .cinit section should not be split.
161 */
162
163 .cinit : {} > P_MEM3 /* Initialization Tables */
164 .const : {} > P_MEM3 /* Constant Data */
165 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
166
167 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
168
169 .stackandheap : > D_MEM1 /* System Stacks, etc... */
170 {
171 /* Leave 20 32bit words for register pushes. */
172 . = align(8);
173 . += 20 * 4;
174
175 /* Stack for abort and/or undefined modes. */
176 exception_stack = .;
177
178 /* Leave 38 32bit words for state saving on exceptions. */
179 _xdump_buffer = .;
180 . += 38 * 4;
181 . = align(8);
182
183 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
184 stack_segment = .;
185 . += 0xB00;
186 }
187
188 .data : {} > D_MEM1 /* Initialized Data */
189 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
190
191 }