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comparison src/cs/layer1/cust0/l1_rf10.c @ 398:91d64e076fb6

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l1_rf10.c: ABB init constant renaming between MV100 and TCS211
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Jan 2018 01:47:05 +0000
parents a513e7682ccf
children
comparison
equal deleted inserted replaced
397:a513e7682ccf 398:91d64e076fb6
1477 /* ABB Initialization words 1477 /* ABB Initialization words
1478 /*------------------------------------------*/ 1478 /*------------------------------------------*/
1479 #if (ANLG_FAM == 1) 1479 #if (ANLG_FAM == 1)
1480 UWORD16 abb[ABB_TABLE_SIZE] = 1480 UWORD16 abb[ABB_TABLE_SIZE] =
1481 { 1481 {
1482 C_AFCCTLADD, // Value at reset 1482 C_AFCCTLADD, // Value at reset
1483 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute 1483 C_VBUCTRL, // Uplink gain amp 0dB, Sidetone gain to mute
1484 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB 1484 C_VBDCTRL, // Downlink gain amp 0dB, Volume control 0 dB
1485 C_BBCTL, // value at reset 1485 C_BBCTRL, // value at reset
1486 C_APCOFF, // value at reset 1486 C_APCOFF, // value at reset
1487 C_BULIOFF, // value at reset 1487 C_BULIOFF, // value at reset
1488 C_BULQOFF, // value at reset 1488 C_BULQOFF, // value at reset
1489 C_DAI_ON_OFF, // value at reset 1489 C_DAI_ON_OFF, // value at reset
1490 C_AUXDAC, // value at reset 1490 C_AUXDAC, // value at reset
1491 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1 1491 C_VBCTRL, // VULSWITCH=0, VDLAUX=1, VDLEAR=1
1492 C_APCDEL // value at reset 1492 C_APCDEL1 // value at reset
1493 }; 1493 };
1494 #elif (ANLG_FAM == 2) 1494 #elif (ANLG_FAM == 2)
1495 UWORD16 abb[ABB_TABLE_SIZE] = 1495 UWORD16 abb[ABB_TABLE_SIZE] =
1496 { 1496 {
1497 C_AFCCTLADD, 1497 C_AFCCTLADD,
1498 C_VBUR, 1498 C_VBUCTRL,
1499 C_VBDR, 1499 C_VBDCTRL,
1500 C_BBCTL, 1500 C_BBCTRL,
1501 C_BULGCAL, 1501 C_BULGCAL,
1502 C_APCOFF, 1502 C_APCOFF,
1503 C_BULIOFF, 1503 C_BULIOFF,
1504 C_BULQOFF, 1504 C_BULQOFF,
1505 C_DAI_ON_OFF, 1505 C_DAI_ON_OFF,
1506 C_AUXDAC, 1506 C_AUXDAC,
1507 C_VBCR, 1507 C_VBCTRL1,
1508 C_VBCR2, 1508 C_VBCTRL2,
1509 C_APCDEL, 1509 C_APCDEL1,
1510 C_APCDEL2 1510 C_APCDEL2
1511 }; 1511 };
1512 1512
1513 #elif (ANLG_FAM == 3) 1513 #elif (ANLG_FAM == 3)
1514 UWORD16 abb[ABB_TABLE_SIZE] = 1514 UWORD16 abb[ABB_TABLE_SIZE] =
1515 { 1515 {
1516 C_AFCCTLADD, 1516 C_AFCCTLADD,
1517 C_VBUR, 1517 C_VBUCTRL,
1518 C_VBDR, 1518 C_VBDCTRL,
1519 C_BBCTL, 1519 C_BBCTRL,
1520 C_BULGCAL, 1520 C_BULGCAL,
1521 C_APCOFF, 1521 C_APCOFF,
1522 C_BULIOFF, 1522 C_BULIOFF,
1523 C_BULQOFF, 1523 C_BULQOFF,
1524 C_DAI_ON_OFF, 1524 C_DAI_ON_OFF,
1525 C_AUXDAC, 1525 C_AUXDAC,
1526 C_VBCR, 1526 C_VBCTRL1,
1527 C_VBCR2, 1527 C_VBCTRL2,
1528 C_APCDEL, 1528 C_APCDEL1,
1529 C_APCDEL2, 1529 C_APCDEL2,
1530 C_VBPOP, 1530 C_VBPOP,
1531 C_VAUDINITD, 1531 C_VAUDINITD,
1532 C_VAUDCR, 1532 C_VAUDCR,
1533 C_VAUOCR, 1533 C_VAUOCR,
1534 C_VAUSCR, 1534 C_VAUSCR,
1535 C_VAUDPLL 1535 C_VAUDPLL