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comparison src/cs/drivers/drv_core/memif/sys_memif.h @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /* @(#) nom : sys_memif.h SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_memif.h */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Francois AMAND
10 *
11 *
12 * Important Note
13 * --------------
14 *
15 * This S/W is a preliminary version. It contains information on a product
16 * under development and is issued for evaluation purposes only. Features
17 * characteristics, data and other information are subject to change.
18 *
19 * The S/W is furnished under Non Disclosure Agreement and may be used or
20 * copied only in accordance with the terms of the agreement. It is an offence
21 * to copy the software in any way except as specifically set out in the
22 * agreement. No part of this document may be reproduced or transmitted in any
23 * form or by any means, electronic or mechanical, including photocopying and
24 * recording, for any purpose without the express written permission of Texas
25 * Instruments Inc.
26 *
27 ******************************************************************************
28 *
29 * FILE NAME: sys_memif.h
30 *
31 *
32 * PURPOSE: Include file to use the ARM memory interface drivers for CALYPSO
33 * PLUS.
34 * The drivers allows ARM memory interface configuration and
35 * control.
36 *
37 *
38 * FILE REFERENCES:
39 *
40 * Name IO Description
41 * ------------- -- ---------------------------------------------
42 *
43 *
44 *
45 * EXTERNAL VARIABLES:
46 *
47 * Source:
48 *
49 * Name Type IO Description
50 * ------------- --------------- -- ------------------------------
51 *
52 *
53 *
54 * EXTERNAL REFERENCES:
55 *
56 * Name Description
57 * ------------------ -------------------------------------------------------
58 *
59 *
60 *
61 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
62 *
63 *
64 *
65 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
66 *
67 *
68 *
69 * NOTES:
70 *
71 *
72 *
73 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
74 *
75 *
76 *
77 *
78 * DEVELOPMENT HISTORY:
79 *
80 * Date Name(s) Version Description
81 * ----------- -------------- ------- -------------------------------------
82 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
83 * 24-Feb-2003 G.Leterrier 0.0.2 change include name for mapping definition
84 * 25 Feb-2003 G.Leterrier 0.0.3 Change MACRO to take in account reserved bit in registers
85 *
86 * ALGORITHM:
87 *
88 *
89 *****************************************************************************/
90
91
92 #ifndef __SYS_MEMIF_H__
93 #define __SYS_MEMIF_H__
94
95 #include "l1sw.cfg"
96 #include "chipset.cfg"
97
98 #if (CHIPSET == 12)
99
100 #if (OP_L1_STANDALONE == 0)
101 #include "main/sys_types.h"
102 #else
103 #include "sys_types.h"
104 #endif
105
106 #include "sys_map.h"
107
108 /****************************************************************************
109 * CONSTANT DEFINITION
110 ***************************************************************************/
111
112 /*
113 * Chip-select offset definition
114 */
115 #define C_MEMIF_CS0_OFFSET 0
116 #define C_MEMIF_CS1_OFFSET 1
117 #define C_MEMIF_CS2_OFFSET 2
118 #define C_MEMIF_CS3_OFFSET 3
119 #define C_MEMIF_CS4_OFFSET 4
120 #define C_MEMIF_CS5_OFFSET 5
121
122 #define C_MEMIF_NB_EXTERNAL_CS 6
123
124 #define C_MEMIF_CS_SIZE_MAX_MB 64
125
126 #define C_MEMIF_INTERNAL_SRAM_START_ADDR 0x08000000
127
128 /*
129 * Registers offset definition
130 */
131 #define C_MEMIF_CONF_CSX_OFFSET(cs_index) (0x00 + 2 * cs_index)
132 #define C_MEMIF_EXWS_CSX_OFFSET(cs_index) (0x20 + 2 * cs_index)
133 #define C_MEMIF_DCCTRL_CSX_OFFSET(cs_index) (0x30 + 2 * cs_index)
134 #define C_MEMIF_API_RHEA_CTRL_OFFSET 0x0E
135 #define C_MEMIF_EX_CTRL_OFFSET 0x10
136 #define C_MEMIF_DSPMS_OFFSET 0x2E
137
138
139 /*
140 * Registers address definition
141 */
142 #define C_MEMIF_CONF_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_CONF_CSX_OFFSET(cs_index))
143 #define C_MEMIF_EXWS_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_EXWS_CSX_OFFSET(cs_index))
144 #define C_MEMIF_DCCTRL_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_DCCTRL_CSX_OFFSET(cs_index))
145 #define C_MEMIF_API_RHEA_CTRL_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_API_RHEA_CTRL_OFFSET)
146 #define C_MEMIF_EX_CTRL_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_EX_CTRL_OFFSET)
147 #define C_MEMIF_DSPMS_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_DSPMS_OFFSET)
148
149
150
151 /*
152 * CONF_CSx register definition
153 */
154 #define C_MEMIF_CONF_CSX_MASK 0x0100
155 /* Bits position in the register */
156 #define C_MEMIF_CONF_WS_POS 0
157 #define C_MEMIF_CONF_DVS_POS 5
158 #define C_MEMIF_CONF_WE_POS 7
159 #define C_MEMIF_CONF_DC_POS 9
160 #define C_MEMIF_CONF_RODC_POS 12
161 #define C_MEMIF_CONF_WRDC_POS 13
162 #define C_MEMIF_CONF_WWS_POS 14
163
164 /* DVS bits definition */
165 #define C_MEMIF_DVS_8 0 /* device size = 8 bits */
166 #define C_MEMIF_DVS_16 1 /* device size = 16 bits */
167 #define C_MEMIF_DVS_32 2 /* device size = 32 bits */
168
169 /* WE bits definition */
170 #define C_MEMIF_WRITE_DIS 0 /* write disable */
171 #define C_MEMIF_WRITE_EN 1 /* write enable */
172
173 /* RODC bits definition */
174 #define C_MEMIF_RODC_DIS 0 /* Read Only Dummy Cycle mode Enable */
175 #define C_MEMIF_RODC_EN 1 /* Read Only Dummy Cycle mode Disable */
176
177 /* WRDC bits definition */
178 #define C_MEMIF_WRDC_DIS 0 /* Write-Read Insertion Dummy Cycle mode Enable */
179 #define C_MEMIF_WRDC_EN 1 /* Write-Read Insertion Dummy Cycle mode Disable */
180
181 /* WWS bits definition */
182 #define C_MEMIF_WWS_VALUE_DIS 1 /* WRSS value use for write and WS for read access */
183 #define C_MEMIF_WWS_VALUE_EN 0 /* WS value use for write and read access */
184
185
186
187 /*
188 * EXWS_CSx register definition
189 */
190 #define C_MEMIF_EXWS_MASK 0x0038
191 /* Bits position in the register */
192 #define C_MEMIF_EXWS_PME_POS 0
193 #define C_MEMIF_EXWS_PMS_POS 1
194 #define C_MEMIF_EXWS_PMWS_POS 6
195 #define C_MEMIF_EXWS_WRWS_POS 11
196
197 /* PME bits definition */
198 #define C_MEMIF_PAGE_MODE_DIS 0 /* Page mode disable */
199 #define C_MEMIF_PAGE_MODE_EN 1 /* Page mode enable */
200
201 /* PMS bits definition */
202 #define C_MEMIF_PMS_2B 0 /* Page size = 2 bytes */
203 #define C_MEMIF_PMS_4B 1 /* Page size = 4 bytes */
204 #define C_MEMIF_PMS_8B 2 /* Page size = 8 bytes */
205 #define C_MEMIF_PMS_16B 3 /* Page size = 16 bytes */
206
207
208
209 /*
210 * DCCTRL_CSx register definition
211 */
212 /* Bits position in the register */
213 #define C_MEMIF_DCCTRL_DCECS0_POS 0
214 #define C_MEMIF_DCCTRL_DCECS1_POS 1
215 #define C_MEMIF_DCCTRL_DCECS2_POS 2
216 #define C_MEMIF_DCCTRL_DCECS3_POS 3
217 #define C_MEMIF_DCCTRL_DCECS4_POS 4
218 #define C_MEMIF_DCCTRL_DCECS5_POS 5
219
220 /* DCECSx bits definition */
221 #define C_MEMIF_DCECS_DIS 0 /* No DC */
222 #define C_MEMIF_DCECS_EN 1 /* Insert Dummy Cycle if previous CSn is CSn */
223
224
225
226 /*
227 * EX_CTRL register definition
228 */
229 #define C_MEMIF_EX_CTRL_MASK 0x0780
230 /* Bits position in the register */
231 #define C_MEMIF_EX_CTRL_WSR_POS 0
232 #define C_MEMIF_EX_CTRL_CTRL_WS0_POS 1
233 #define C_MEMIF_EX_CTRL_CTRL_WS1_POS 2
234 #define C_MEMIF_EX_CTRL_CTRL_WS2_POS 3
235 #define C_MEMIF_EX_CTRL_CTRL_WS3_POS 4
236 #define C_MEMIF_EX_CTRL_CTRL_WS4_POS 5
237 #define C_MEMIF_EX_CTRL_CTRL_WS5_POS 6
238 #define C_MEMIF_EX_CTRL_DISABLE_DU_POS 11
239 #define C_MEMIF_EX_CTRL_CS_MODE_POS 12
240 #define C_MEMIF_EX_CTRL_CS_MODE_EN_POS 14
241 #define C_MEMIF_EX_CTRL_EX_PAGEM_POS 15
242
243 /* DISABLE_DU bit definition */
244 #define C_MEMIF_EX_CTRL_DU_EN 0 /* DU capture is enabled */
245 #define C_MEMIF_EX_CTRL_DU_DIS 1 /* DU capture is disabled */
246
247 /* CS_MODE bits definition */
248 #define C_MEMIF_EX_CTRL_CS_MODE_MASK 0x0003
249
250 #define C_MEMIF_EX_CTRL_CS_MODE_0 0 /* CS_MODE configuration 0 */
251 #define C_MEMIF_EX_CTRL_CS_MODE_1 1 /* CS_MODE configuration 1 */
252 #define C_MEMIF_EX_CTRL_CS_MODE_2 2 /* CS_MODE configuration 2 */
253 #define C_MEMIF_EX_CTRL_CS_MODE_3 3 /* CS_MODE configuration 3 */
254
255 /* CS_MODE_EN bit definition */
256 #define C_MEMIF_EX_CTRL_CS_MODE_FREEZE 1 /* Freeze CS_MODE configuration and access to CS_MODE_EN bit */
257
258 /* EX_PAGEM bit definition */
259 #define C_MEMIF_EX_CTRL_EX_PAGEM_DIS 0 /* Disable extended page-mode */
260 #define C_MEMIF_EX_CTRL_EX_PAGEM_EN 1 /* Enable extended page-mode */
261
262
263
264 /*
265 * API_RHEA_CTRL register definition
266 */
267 #define C_MEMIF_API_RHEA_CTRL_MASK 0x0015
268 /* Bits position in the register */
269 #define C_MEMIF_API_RHEA_CTRL_ADAPT0_POS 1
270 #define C_MEMIF_API_RHEA_CTRL_ADAPT1_POS 3
271 #define C_MEMIF_API_RHEA_CTRL_ADAPTAPI_POS 5
272 #define C_MEMIF_API_RHEA_CTRL_DEBUG_POS 6
273
274 /* ADAPT0, ADAPT1 and ADAPTAPI bits definition */
275 #define C_MEMIF_API_RHEA_NO_ADAPT 0 /* no memory adaptation */
276 #define C_MEMIF_API_RHEA_ADAPT 1 /* memory adaptation */
277
278 /* DEBUG bits definition */
279 #define C_MEMIF_API_RHEA_NO_DEBUG 0 /* no ARM address can be observed */
280 #define C_MEMIF_API_RHEA_DEBUG 1 /* ARM address can be observed */
281
282
283
284 /*
285 * DSPMS register definition
286 */
287 /* Bits position in the register */
288 #define C_MEMIF_DSPMS_POS 0
289
290 /* DSPMS bit definition */
291 #define C_MEMIF_DSPMS_MASK 0x0003
292 #define C_MEMIF_DSPMS_0MBITS_TO_DSP 0x0000
293 #define C_MEMIF_DSPMS_0_5MBITS_TO_DSP 0x0001
294
295
296
297
298 /****************************************************************************
299 * MACRO DEFINITION
300 ***************************************************************************/
301
302 #define F_MEMIF_ENABLE_EXTENDED_PAGE_MODE C_MEMIF_EX_CTRL_REG |= (C_MEMIF_EX_CTRL_EX_PAGEM_EN << C_MEMIF_EX_CTRL_EX_PAGEM_POS)
303
304 #define F_MEMIF_DU_ENABLE C_MEMIF_EX_CTRL_REG &= ~(C_MEMIF_EX_CTRL_DU_DIS << C_MEMIF_EX_CTRL_DISABLE_DU_POS)
305 #define F_MEMIF_DU_DISABLE C_MEMIF_EX_CTRL_REG |= (C_MEMIF_EX_CTRL_DU_DIS << C_MEMIF_EX_CTRL_DISABLE_DU_POS)
306
307
308 #define F_MEMIF_DEBUG_FREEZE C_MEMIF_API_RHEA_CTRL_REG &= ~(C_MEMIF_API_RHEA_DEBUG <<C_MEMIF_API_RHEA_CTRL_DEBUG_POS)
309
310 /****************************************************************************
311 * STRUCTURE DEFINITION
312 ***************************************************************************/
313
314 typedef struct {
315 /* CONF_CSx register configuration */
316 SYS_UWORD8 d_ws;
317 SYS_UWORD8 d_dvs;
318 SYS_UWORD8 d_we;
319 SYS_UWORD8 d_dc;
320 SYS_UWORD8 d_rodc;
321 SYS_UWORD8 d_wrdc;
322 SYS_UWORD8 d_wws;
323
324 /* EXWS_CSx register configuration */
325 SYS_UWORD8 d_pme;
326 SYS_UWORD8 d_pms;
327 SYS_UWORD8 d_pmws;
328 SYS_UWORD8 d_wrws;
329
330 /* DCCTRL_CSx register configuration */
331 SYS_UWORD8 d_dcecs0;
332 SYS_UWORD8 d_dcecs1;
333 SYS_UWORD8 d_dcecs2;
334 SYS_UWORD8 d_dcecs3;
335 SYS_UWORD8 d_dcecs4;
336 SYS_UWORD8 d_dcecs5;
337
338 } T_MEMIF_CS_CONFIG;
339
340
341
342 /****************************************************************************
343 * PROTOTYPE DEFINITION
344 ***************************************************************************/
345
346 void f_memif_init_cs(SYS_UWORD8 d_cs, T_MEMIF_CS_CONFIG *p_cs_config);
347
348 void f_memif_init_api_rhea_ctrl(SYS_UWORD8 d_adap0,
349 SYS_UWORD8 d_adap1,
350 SYS_UWORD8 d_adap_api,
351 SYS_UWORD8 d_debug);
352
353 void f_memif_du_enable(void);
354
355 void f_memif_du_disable(void);
356
357 void f_memif_extended_page_mode_enable(void);
358
359 void f_memif_shared_sram_allocation(SYS_UWORD16 d_allocation_cfg);
360
361 void f_memif_cs_mode(SYS_UWORD16 d_cs_mode_cfg);
362
363 void f_memif_debug_freeze(void);
364
365 #endif /* (CHIPSET == 12) */
366
367 #endif /* __SYS_MEMIF_H__ */