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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /*******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : ulpd.h
12
13 Description : Header for HYPERION/ULPD module tests
14 Target : Arm
15
16 Project : Hyperion
17
18 Author : smunsch@tif.ti.com Sylvain Munsch.
19
20 Version number : 1.11
21
22 Date and time : 12/20/00 10:17:22
23
24 Previous delta : 12/06/00 17:31:50
25
26 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P/drivers1/common/SCCS/s.ulpd.h
27
28 Sccs Id (SID) : '@(#) ulpd.h 1.11 12/20/00 10:17:22 '
29
30
31 *****************************************************************************/
32
33 #ifndef _WINDOWS
34 #include "chipset.cfg"
35 #include "board.cfg"
36 #include "rf.cfg"
37 #endif
38
39 #include <limits.h>
40 #include <float.h>
41
42 // SLEEP MODES
43 //=======================
44 #define DO_NOT_SLEEP 00
45 #define FRAME_STOP 01 // little BIG SLEEP (CUST5...)
46 #define CLOCK_STOP 02 // Deep sleep
47
48
49 // ULPD registers address
50 //=======================
51
52 #define ULPD_XIO_START 0xfffe2000
53
54 #define ULPD_INC_FRAC_REG (SYS_UWORD16 *)(ULPD_XIO_START)
55 #define ULDP_INC_SIXTEENTH_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 1)
56 #define ULDP_SIXTEENTH_START_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 2)
57 #define ULDP_SIXTEENTH_STOP_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 3)
58 #define ULDP_COUNTER_32_LSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 4)
59 #define ULDP_COUNTER_32_MSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 5)
60 #define ULDP_COUNTER_HI_FREQ_LSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 6)
61 #define ULDP_COUNTER_HI_FREQ_MSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 7)
62 #define ULDP_GAUGING_CTRL_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 8)
63 #define ULDP_GAUGING_STATUS_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 9)
64 #define ULDP_GSM_TIMER_CTRL_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 10)
65 #define ULDP_GSM_TIMER_INIT_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 11)
66 #define ULDP_GSM_TIMER_VALUE_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 12)
67 #define ULDP_GSM_TIMER_IT_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 13)
68 #define ULDP_SETUP_CLK13_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 14)
69 #define ULDP_SETUP_SLICER_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 15)
70 #define ULDP_SETUP_VTCXO_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 16)
71 #define ULDP_SETUP_FRAME_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 17)
72 #define ULPD_SETUP_RF_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 18)
73
74
75 // ULPD gauging control register description
76 //==========================================
77
78 #define ULDP_GAUGING_EN 0x0001 // Gauging is running
79 #define ULDP_GAUGING_TYPE_HF 0x0002 // Gauging versus HFclock
80 #define ULDP_SEL_HF_PLL 0x0004 // High freq clock = PLL DSP
81
82 // ULPD gauging status register description
83 //==========================================
84
85 #define ULDP_IT_GAUGING 0x0001 // Interrupt it_gauging occurence
86 #define ULDP_OVF_HF 0x0002 // Overflow on the HF counter
87 #define ULDP_OVF_32 0x0004 // Overflow on the 32 Khz counter
88
89 // WAKEup time
90 //==========================================
91 // the setup time unit is the number of 32 Khz clock periods
92
93 #if (BOARD == 34)
94
95 #define SETUP_RF 75 // adujstement time to minimize big_sleep duration
96 // The SETUP_RF value must be used to delay as much as possible the true
97 // start time of the deep_sleep wake-up sequence for power consumption saving.
98 // This is required because the unit of the SETUP_FRAME counter is the
99 // GSM TDMA frame and not a T32K time period.
100
101 #define SETUP_VTCXO 320 // The setup_vtcxo is the time the external RF device takes to deliver
102 // stable signals to the VTCXO
103
104
105 #define SETUP_SLICER 180 // The setup_slicer is the time that the vtcxo takes to deliver
106 // a stable output when vtcxo is enabled : usually 2 to 5ms
107 // The SETUP_SLICER value should be smaller than 160(=4,8ms) but this
108 // parameter is directly related to the VTCXO device used in the phone
109 // and consequently must be retrieved from the VTCXO data-sheet.
110
111 #define SETUP_CLK13 31 // The setup_clk13 is time that the slicer takes to deliver
112 // a stable output when slicer is enabled : max conservative value 1ms
113
114 #else
115
116 #define SETUP_RF 0 // adujstement time to minimize big_sleep duration
117 // The SETUP_RF value must be used to delay as much as possible the true
118 // start time of the deep_sleep wake-up sequence for power consumption saving.
119 // This is required because the unit of the SETUP_FRAME counter is the
120 // GSM TDMA frame and not a T32K time period.
121 #if (CHIPSET == 2)
122 #define SETUP_VTCXO 31 // The setup_vtcxo is the time the external RF device takes to deliver
123 #else // stable signals to the VTCXO
124 #define SETUP_VTCXO 1114 // 34 ms for ABB LDO stabilization before 13MHz switch ON
125 // Minimum value to be sure that ABB is awake while the DBB start running for
126 // SETUP_VTCXO = ((SLPDLY*16)+4+145)*T32KHz
127 #endif
128
129 #if (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
130 #if (RF_FAM==12)
131 #define SETUP_SLICER 660
132 #else
133 #define SETUP_SLICER 600 // 600/32x10^3 = 18.75ms required for VCXO stabilization
134 #endif
135 #else
136 #define SETUP_SLICER 180 // The setup_slicer is the time that the vtcxo takes to deliver
137 // a stable output when vtcxo is enabled : usually 2 to 5ms
138 // The SETUP_SLICER value should be smaller than 160(=4,8ms) but this
139 // parameter is directly related to the VTCXO device used in the phone
140 // and consequently must be retrieved from the VTCXO data-sheet.
141 #endif
142
143 #define SETUP_CLK13 31 // The setup_clk13 is time that the slicer takes to deliver
144 // a stable output when slicer is enabled : max conservative value 1ms
145
146 #endif // BOARD == 34
147
148 // SETUP_FRAME:
149 //-------------
150 // CF. Reference document: ULYS015 v1.1 page 24
151 // 1) Nominal Frequency = 32.768 Khz => 0.03051757 ms
152 // (0.03051757 ms / 4.615 ms) = 0.006612692 Frames
153 // 2) The use of the RFEN signal is optional. It is necessary if the VTCXO function
154 // is part of an RF IC which must be first powered before enabling the VTCXO.
155 // However it can be use for any other purpose.
156 // 3) The term (1-DBL_EPSILON) corresponds to the rounding up of SETUP_FRAME.
157 #ifndef DBL_EPSILON //CQ16723: For non TI compiler, DBL_EPSILON can be undefined.
158 #define DBL_EPSILON 0
159 #endif
160
161 #define SETUP_FRAME ((( SETUP_RF+SETUP_VTCXO+SETUP_SLICER+SETUP_CLK13)*0.006612692)+(1-DBL_EPSILON))
162
163 #define MAX_GSM_TIMER 65535 // max duration for the wake up timer
164
165
166 // Default values for Cell selection and CS_MODE0
167 //===============================================
168 #define DEFAULT_HFMHZ_VALUE (13000000*l1_config.dpll)
169 #define DEFAULT_32KHZ_VALUE (32768) // real value 32768.29038 hz
170 //with l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE) and dpll = 65Mhz
171 // => DEFAULT_INCSIXTEEN 132
172 // => DEFAULT_INCFRAC 15915
173
174
175
176
177
178 // ULPD GSM timer control register description
179 //============================================
180
181 #define ULDP_TM_LOAD 0x0001 // load the timer with init value
182 #define ULDP_TM_FREEZE 0x0002 // 1=> GSM timer is frozen
183 #define ULPD_IT_TIMER_GSM 0x0001 // Interrupt timer occurrence
184
185
186 // ULDP_INCFRAC_UPDATE : update INCFRAC (16 bits)
187 //================================================
188 #define ULDP_INCFRAC_UPDATE(frac) (* (volatile SYS_UWORD16 *)ULPD_INC_FRAC_REG = frac)
189
190
191 // ULDP_INCSIXTEEN_UPDATE : update INCSIXTEEN (12 bits)
192 //======================================================
193 #define ULDP_INCSIXTEEN_UPDATE(inc) (* (volatile SYS_UWORD16 *)ULDP_INC_SIXTEENTH_REG = inc)
194
195
196 // ULDP_GAUGING_RUN : Start the gauging
197 //=====================================
198 #define ULDP_GAUGING_RUN (* (volatile SYS_UWORD16 *)ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_EN)
199
200
201 // ULDP_GAUGING_STATUS : Return if it gauging occurence
202 //======================================================
203 #define ULDP_GAUGING_STATUS ((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_GAUGING_EN )
204
205 // ULDP_GAUGING_STOP : Stop the gauging
206 //=====================================
207 #define ULDP_GAUGING_STOP (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG &= ~ULDP_GAUGING_EN)
208
209 // ULDP_GAUGING_START : Stop the gauging
210 //=====================================
211 #define ULDP_GAUGING_START (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_EN)
212
213 // ULDP_GAUGING_SET_HF : Set the gauging versus HF clock
214 //======================================================
215 #define ULDP_GAUGING_SET_HF (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_TYPE_HF)
216
217 // ULDP_GAUGING_HF_PLL : Set the gauging HF versus PLL clock
218 //===========================================================
219 #define ULDP_GAUGING_HF_PLL (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_SEL_HF_PLL)
220
221
222 // ULDP_GET_IT_GAG : Return if the interrupt it gauging occurence
223 //================================================================
224 #define ULDP_GET_IT_GAG ((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING )
225
226 // ULDP_GET_OVF_HF : Return overflow occured on the HF counter
227 //=============================================================
228 #define ULDP_GET_OVF_HF (((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_OVF_HF)>>1)
229
230 // ULDP_GET_OVF_32 : Return overflow occured on the 32 counter
231 //=============================================================
232 #define ULDP_GET_OVF_32 (((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_OVF_32)>>2)
233
234 // ULDP_TIMER_INIT : Load the timer_init value
235 //=========================================================
236 #define ULDP_TIMER_INIT(value) ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_INIT_REG) = value)
237
238 // READ_ULDP_TIMER_INIT : Read the timer_init value
239 //=========================================================
240 #define READ_ULDP_TIMER_INIT (* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_INIT_REG)
241
242 // READ_ULDP_TIMER_VALUE : Read the timer_init value
243 //=========================================================
244 #define READ_ULDP_TIMER_VALUE (* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_VALUE_REG)
245
246 // ULDP_TIMER_LD : Load the timer with timer_init value
247 //=========================================================
248 #define ULDP_TIMER_LD ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) |= ULDP_TM_LOAD)
249
250 // ULDP_TIMER_FREEZE : Freeze the timer
251 //=========================================================
252 #define ULDP_TIMER_FREEZE ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) |= ULDP_TM_FREEZE)
253
254 // ULDP_GSM_TIME_START : Run the GSM timer
255 //=========================================
256 #define ULDP_TIMER_START ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) &= ~ULDP_TM_FREEZE)
257
258 // ULDP_GET_IT_TIMER : Return the it GSM timer occurence
259 //===========================================================
260 #define ULDP_GET_IT_TIMER ((* (volatile SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM )
261
262