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comparison src/cs/layer1/cust0/l1_rf35.h @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf35.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 /************************************/
13 /* SYNTHESIZER setup time... */
14 /************************************/
15 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
16 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
17
18 /************************************/
19 /* time for TPU scenario ending... */
20 /************************************/
21 #define RX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BDLENA down
22 // minus serialization time
23 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BULON down
24 // minus serialization time
25
26 /******************************************************/
27 /* TXPWR configuration... */
28 /* Fixed TXPWR value when GSM management is disabled. */
29 /******************************************************/
30 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
31 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252
32 // #define FIXED_TXPWR 0x0a12 // TXPWR=15, value=40
33 #define FIXED_TXPWR 0x1a12 // TXPWR=15, EVA4, CRTP1
34 #endif
35
36
37 /************************************/
38 /* ANALOG delay (in qbits) */
39 /************************************/
40 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
41 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
42 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
43 #if (ANLG_FAM == 1)
44 #define UL_ABB_DELAY 6 // modulator input to output delay
45 #endif
46 #if (ANLG_FAM == 2)
47 #define UL_ABB_DELAY 3 // modulator input to output delay
48 #endif
49
50 /************************************/
51 /* TX Propagation delay... */
52 /************************************/
53 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
54 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 + NB_MARGIN
55 #endif
56
57 /************************************/
58 /* Initial value for APC DELAY */
59 /************************************/
60 #if (ANLG_FAM == 1)
61 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
62 #define APCDEL_DOWN 2 // minimum value: 2
63 #define APCDEL_UP (6+5) // minimum value: 6
64 #endif
65 #if (ANLG_FAM == 2)
66 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
67 #define APCDEL_DOWN 2 // minimum value: 2
68 #define APCDEL_UP (6+2) // minimum value: 6
69 #endif
70
71 #define GUARD_BITS 7
72
73 /************************************/
74 /* Initial value for AFC... */
75 /************************************/
76 #define EEPROM_AFC ((-55)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
77
78 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC (in Frames)
79 // !! minimum Value : 1 Frame due to the fact there is no
80 // hisr() in the first wake-up frame !!!!
81
82 /************************************/
83 /* Baseband registers */
84 /************************************/
85 #if (ANLG_FAM == 1)
86 // Omega registers values will be programmed at 1st DSP communication interrupt
87 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG
88 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
89 #define C_VBUCTRL 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute
90 #define C_VBDCTRL 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB
91 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
92 #define C_APCOFF 0x1016 | (0x34 << 6)/*(0x3c << 6)*/ | TRUE // value at reset-Changed from 0x0016- CR 27.12
93 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
94 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
95 #define C_DAI_ON_OFF 0x0000 // value at reset
96 #define C_AUXDAC 0x0018 | TRUE // value at reset
97 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
98 // BULRUDEL will be initialized on rach only ....
99 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
100 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
101 #endif
102 #if (ANLG_FAM == 2)
103 // IOTA registers values will be programmed at 1st DSP communication interrupt
104 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
105 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
106 #define C_VBUCTRL 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB
107 #define C_VBDCTRL 0x098c | TRUE // PGA_DL 0dB, Volume 0dB
108 #define C_APCOFF 0x1016 | TRUE // x2 slope 128
109 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
110 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
111 #define C_DAI_ON_OFF 0x0000 // value at reset
112 #define C_AUXDAC 0x0018 | TRUE // value at reset
113 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
114 #define C_VBCTRL2 0x0016 | TRUE // MICBIASEL=0, VDLHSO=0, MICAUX=0
115
116 // BULRUDEL will be initialized on rach only ....
117 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
118 #define C_APCDEL2 0x0034
119 #define C_BBCTRL 0x304c | TRUE // Internal autocalibration, Output common mode=1.35V
120 // Monoslot, Vpp=8/15*Vref
121 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
122 #endif
123
124 /************************************/
125 /* Automatic frequency compensation */
126 /************************************/
127 /********************* C_Psi_sta definition *****************************/
128 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
129 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
130 /* regarding Vega V/N = 2.4/4096 */
131 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
132 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
133 /* = 0.000195748 */
134 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
135 /************************************************************************/
136 #define C_Psi_sta_inv 11677L // (1/C_Psi_sta)
137 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
138 #define C_Psi_st_32 294257L // F0.32
139 #define C_Psi_st_inv 14596L // (1/C_Psi_st)
140
141 typedef struct
142 {
143 WORD16 eeprom_afc;
144 UWORD32 psi_sta_inv;
145 UWORD32 psi_st;
146 UWORD32 psi_st_32;
147 UWORD32 psi_st_inv;
148 }
149 T_AFC_PARAMS;
150
151 /************************************/
152 /* Swap IQ definitions... */
153 /************************************/
154 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
155 #define SWAP_IQ_GSM 0
156 #define SWAP_IQ_DCS 3
157 #define SWAP_IQ_PCS 3
158 #define SWAP_IQ_GSM850 0 //TBD
159
160 /************************************/
161 /* RF bands supported */
162 /************************************/
163 #define RF_HW_BAND_SUPPORT (0x0020 | 0x0004) // radio_band_support E-GSM/DCS + PC
164
165 /************************************/
166 /************************************/
167 // typedef
168 /************************************/
169 /************************************/
170
171 /*************************************************************/
172 /* Define structure for apc of TX Power ******/
173 /*************************************************************/
174 typedef struct
175 { // pcm-file "rf/tx/level.gsm|dcs"
176 UWORD16 apc; // 0..31
177 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
178 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
179 }
180 T_TX_LEVEL;
181
182 /************************************/
183 /* Automatic Gain Control */
184 /************************************/
185 /* Define structure for sub-band definition of TX Power ******/
186 typedef struct
187 {
188 UWORD16 upper_bound; //highest physical arfcn of the sub-band
189 WORD16 agc_calib; // AGC for each TXPWR
190 }T_RF_AGC_BAND;
191
192 /************************************/
193 /* Ramp definitions */
194 /************************************/
195 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
196 typedef struct
197 {
198 UWORD8 ramp_up [16]; // Ramp-up profile
199 UWORD8 ramp_down [16]; // Ramp-down profile
200 }
201 T_TX_RAMP;
202 #endif
203
204
205 // RF structure definition
206 //========================
207
208 enum RfRevision {
209 RF_IGNORE = 0x0000,
210 RF_SL2 = 0x1000,
211 RF_GAIA_20X = 0x2000,
212 RF_GAIA_20A = 0x2001,
213 RF_GAIA_20B = 0x2002,
214 RF_ATLAS_20B = 0x2020,
215 RF_PASCAL_20 = 0x2030
216 };
217
218 // Number of bands supported
219 #define GSM_BANDS 2
220
221 #define MULTI_BAND1 0
222 #define MULTI_BAND2 1
223 // RF table sizes
224 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
225 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
226
227 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
228 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
229 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
230 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
231 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
232
233 #define AGC_TABLE_SIZE 36
234
235 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
236
237
238 // RX parameters and tables
239 //-------------------------
240
241 // AGC parameters and tables
242 typedef struct
243 {
244 UWORD16 low_agc_noise_thr;
245 UWORD16 high_agc_sat_thr;
246 UWORD16 low_agc;
247 UWORD16 high_agc;
248 UWORD8 il2agc_pwr[121];
249 UWORD8 il2agc_max[121];
250 UWORD8 il2agc_av[121];
251 }
252 T_AGC;
253
254 // Calibration parameters
255 typedef struct
256 {
257 UWORD16 g_magic;
258 UWORD16 lna_att;
259 UWORD16 lna_switch_thr_low;
260 UWORD16 lna_switch_thr_high;
261 }
262 T_RX_CAL_PARAMS;
263
264 // RX temperature compensation
265 typedef struct
266 {
267 WORD16 temperature;
268 WORD16 agc_calib;
269 }
270 T_RX_TEMP_COMP;
271
272 // RF RX structure
273 typedef struct
274 {
275 T_AGC agc;
276 }
277 T_RF_RX; //common
278
279 // RF RX structure
280 typedef struct
281 {
282 T_RX_CAL_PARAMS rx_cal_params;
283 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
284 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
285 }
286 T_RF_RX_BAND;
287
288
289 // TX parameters and tables
290 //-------------------------
291
292 // TX temperature compensation
293 typedef struct
294 {
295 WORD16 temperature;
296 WORD16 apc_calib;
297 }
298 T_TX_TEMP_CAL;
299
300 // Ramp up and ramp down delay
301 typedef struct
302 {
303 UWORD16 up;
304 UWORD16 down;
305 }
306 T_RAMP_DELAY;
307
308 typedef struct
309 {
310 UWORD16 arfcn_limit;
311 WORD16 chan_cal;
312 }
313 T_TX_CHAN_CAL;
314
315 // RF TX structure
316 typedef struct
317 {
318 T_RAMP_DELAY ramp_delay;
319 UWORD8 guard_bits; // number of guard bits needed for ramp up
320 UWORD8 prg_tx;
321 }
322 T_RF_TX; //common
323
324 // RF TX structure
325 typedef struct
326 {
327 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
328 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
329 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
330 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
331 }
332 T_RF_TX_BAND;
333
334 // band structure
335 typedef struct
336 {
337 T_RF_RX_BAND rx;
338 T_RF_TX_BAND tx;
339 UWORD8 swap_iq;
340 }
341 T_RF_BAND;
342
343 // RF structure
344 typedef struct
345 {
346 // common for all bands
347 UWORD8 rf_revision;
348 UWORD16 radio_band_support;
349 T_RF_RX rx;
350 T_RF_TX tx;
351 T_AFC_PARAMS afc;
352 }
353 T_RF;
354
355 /************************************/
356 /* MADC definitions */
357 /************************************/
358 // Omega: 5 external channels if touch screen not used, 3 otherwise
359 enum ADC_INDEX {
360 ADC_VBAT,
361 ADC_VCHARG,
362 ADC_ICHARG,
363 ADC_VBACKUP,
364 ADC_BATTEMP,
365 ADC_RFTEMP,
366 ADC_ADC3,
367 ADC_ADC4,
368 ADC_ADC5,
369 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
370 };
371
372 typedef struct
373 {
374 WORD16 converted[ADC_INDEX_END]; // converted
375 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
376 }
377 T_ADC;
378
379 /************************************/
380 /* MADC calibration */
381 /************************************/
382 typedef struct
383 {
384 UWORD16 a[ADC_INDEX_END];
385 WORD16 b[ADC_INDEX_END];
386 }
387 T_ADCCAL;
388
389 // Conversion table: ADC value -> temperature
390 typedef struct
391 {
392 UWORD16 adc; // ADC reading is 10 bits
393 WORD16 temp; // temp is in approx. range -30..+80
394 }
395 T_TEMP;
396
397 typedef struct
398 {
399 char *name;
400 void *addr;
401 int size;
402 }
403 T_CONFIG_FILE;
404
405 typedef struct
406 {
407 char *name; // name of ffs file suffix
408 T_RF_BAND *addr; // address to default flash structure
409 UWORD16 max_carrier; // max carrier
410 UWORD16 max_txpwr; // max tx power
411 }
412 T_BAND_CONFIG;
413
414 typedef struct
415 {
416 UWORD8 band[GSM_BANDS]; // index to band address
417 UWORD8 txpwr_tp; // tx power turning point
418 UWORD16 first_arfcn; // first index
419 }
420 T_STD_CONFIG;
421
422 enum GSMBAND_DEF
423 {
424 BAND_NONE,
425 BAND_EGSM900,
426 BAND_DCS1800,
427 BAND_PCS1900,
428 BAND_GSM850,
429 // put new bands here
430 BAND_GSM900 //last entry
431 };
432
433
434 /************************************/
435 /* ABB (Omega) Initialization */
436 /************************************/
437
438 #define ABB_TABLE_SIZE 16
439
440 // Note that this translation is probably not needed at all. But until L1 is
441 // (maybe) changed to simply initialize the ABB from a table of words, we
442 // use this to make things more easy-readable.
443 #if (ANLG_FAM == 1)
444 enum ABB_REGISTERS {
445 ABB_AFCCTLADD = 0,
446 ABB_VBUCTRL,
447 ABB_VBDCTRL,
448 ABB_BBCTRL,
449 ABB_APCOFF,
450 ABB_BULIOFF,
451 ABB_BULQOFF,
452 ABB_DAI_ON_OFF,
453 ABB_AUXDAC,
454 ABB_VBCTRL,
455 ABB_APCDEL1
456 };
457 #elif (ANLG_FAM == 2)
458 enum ABB_REGISTERS {
459 ABB_AFCCTLADD = 0,
460 ABB_VBUCTRL,
461 ABB_VBDCTRL,
462 ABB_BBCTRL,
463 ABB_BULGCAL,
464 ABB_APCOFF,
465 ABB_BULIOFF,
466 ABB_BULQOFF,
467 ABB_DAI_ON_OFF,
468 ABB_AUXDAC,
469 ABB_VBCTRL,
470 ABB_VBCTRL2,
471 ABB_APCDEL1,
472 ABB_APCDEL2
473 };
474 #endif
475 #endif