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comparison src/cs/layer1/include/l1_time.h @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_TIME.H
4 *
5 * Filename l1_time.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 // *********************************************************************
11 // * *
12 // * This file contains only RF independant defines. *
13 // * *
14 // *********************************************************************
15 // Remarks:
16 // --------
17 // PRG_TX is RF dependant, it is therefore provided within
18 // "l1_rf#.h".
19 // **************************************************************************
20 //
21 // measurements
22 // ------------
23 //
24 // | +-----+
25 // | | PW |
26 // -------------------|--------+ +--------------
27 // clk=offset | |
28 // (frame int.) >|-----|<-PW_BURST_DURATION
29 // | | |
30 // | SYNTH_SETUP_TIME | |
31 // |<--------------------------|< |
32 // | | |
33 // | |
34 // >|--------|<-PROVISION_TIME
35 //
36 //
37 // Normal Burst reception
38 // ----------------------
39 //
40 // | +---------+
41 // | | RX WIN |
42 // ---------------------|--------+ +----------
43 // clk=offset | |
44 // (frame int.) >|---------|<-NB_BURST_DURATION_DL
45 // | | |
46 // | SYNTH_SETUP_TIME | |
47 // |<--------------------------|< |
48 // | | |
49 // | |
50 // >|--------|<-PROVISION_TIME
51 //
52 //
53 // Normal Burst transmission
54 // -------------------------
55 //
56 // .
57 // +---------+
58 // | TX WIN |
59 // --------------------------+ +----------
60 // . |
61 // clk=offset |
62 // . |
63 // . |<--STOP_TX_**
64 // | SYNTH_SETUP_TIME .
65 // |<---------------------->.<--START_TX
66 // | .
67 //
68 //
69 //
70 // Frequency Burst search in Dedicated TCH
71 // ---------------------------------------
72 //
73 // . +-----------(...)-------------+
74 // . | FB search in TCH |
75 // -------------------.--------+ +--------------
76 // . | |
77 // (FB26_ANCHORING_TIME)| |
78 // . | |
79 // SYNTH_SETUP_TIME | |
80 // |<------------------------->| |<-STOP_RX_FB26
81 // . |
82 // . |<-START_RX_FB26
83 // . |
84 // . |
85 // >.--------|<-PROVISION_TIME
86 //
87 //
88 // **************************************************************************
89
90
91 #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task.
92 #if (CODE_VERSION==SIMULATION)
93 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
94 #else
95 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 32) || (DSP == 36)
96 #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task.
97 #else
98 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
99 #endif
100 #endif
101
102
103 #define IMM ( 5000L ) // Immediate command for TPU.
104 #define TN_WIDTH ( 625L )
105 #define BP_DURATION TN_WIDTH
106 #define TAIL_WIDTH ( 3L * 4L ) // = 12
107 #define EXTENDED_TAIL_WIDTH ( 8L * 4L )
108 #define TPU_CLOCK_RANGE ( 5000L )
109 #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change.
110
111 #define PROVISION_TIME ( 66L )
112 #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec.
113 #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec.
114 #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas
115 #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore
116 #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep
117 #if (CODE_VERSION==SIMULATION)
118 #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay
119 #else
120 #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay
121 #endif
122
123 // DMA threshold used for sample acquisition by the DSP
124 #if (CODE_VERSION==SIMULATION)
125 #define RX_DMA_THRES ( 1L )
126 #else
127 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
128 #define RX_DMA_THRES ( 2L )
129 #else
130 #define RX_DMA_THRES ( 1L )
131 #endif
132 #endif
133
134 // BDLENA durations are calculated for a DMA threshold of 1
135 // For a DMA threshold > 1 additional I/Q samples have to be acquired
136 // An increase of BDLENA length by 2qbit is sufficient to acquire one additional I/Q sample
137 // (ABB always outputs pairs of I/Q samples)
138 #define RX_DMA_DELAY (RX_DMA_THRES - 1) * 2
139
140 #if (CODE_VERSION==SIMULATION)
141 #define TULSET_DURATION ( 16L ) // Uplink power on setup time
142 #define BULRUDEL_DURATION ( 2L )
143 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
144 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit
145 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB)
146 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay
147 #endif
148 #endif
149
150 #define SB_MARGIN ( 23L * 4L ) // = 92
151 #define NB_MARGIN ( 3L * 4L ) // = 12
152 #define TA_MAX ( 63L * 4L ) // = 252
153
154 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
155 #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
156 #define PW_BURST_DURATION ( 64L * 4L ) // = 256
157 #define RA_BURST_DURATION ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) ) // = 352 = 88*4
158 #define NB_BURST_DURATION_UL ( 2*TAIL_WIDTH + ( 142L * 4L) ) // = 592 = 148 * 4
159
160 // PRG_TX has become a variable and will be substracted directly in the code
161 #define TIME_OFFSET_TX ( PROVISION_TIME + (3L * TN_WIDTH)) // = 1902, Offset difference for TX with TA=0.
162
163 //================================
164 // Definitions used by TPU drivers
165 //================================
166
167 // BENA durations...
168 //------------------
169 #define SB_ACQUIS_DURATION ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 796 + DMA delay
170 #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay
171 #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay
172 #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay
173 #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay
174
175 #define START_RX_FB ( PROVISION_TIME ) // = 66
176 #define START_RX_SB ( PROVISION_TIME ) // = 66
177 #define START_RX_SNB ( PROVISION_TIME ) // = 66
178 #define START_RX_PW_1 ( PROVISION_TIME ) // = 66
179 #define START_RX_FB26 ( PROVISION_TIME ) // = 66
180
181 #define START_TX_NB ( 0L )
182 #define START_TX_RA ( 0L )
183
184 #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122
185 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862
186 #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702
187 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354
188 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314
189
190
191 //================================
192 // Definitions used for GPRS
193 //================================
194
195 #if L1_GPRS
196 #ifdef L1P_DRIVE_C
197
198 // Window positions for RX normal burst reception durations
199 const UWORD16 RX_DOWN_TABLE[8] =
200 {
201 PROVISION_TIME + NB_ACQUIS_DURATION, //special case: only 1 RX, 151 IQ samples
202 PROVISION_TIME + 2*BP_DURATION + DL_ABB_DELAY, // 2 * 156.25 samples
203 PROVISION_TIME + 3*BP_DURATION + DL_ABB_DELAY, // 3 * 156.25 samples
204 PROVISION_TIME + 4*BP_DURATION + DL_ABB_DELAY, // 4 * 156.25 samples
205 PROVISION_TIME + 5*BP_DURATION + DL_ABB_DELAY, // 5 * 156.25 samples
206 PROVISION_TIME + 6*BP_DURATION + DL_ABB_DELAY, // 6 * 156.25 samples
207 PROVISION_TIME + 7*BP_DURATION + DL_ABB_DELAY, // 7 * 156.25 samples
208 PROVISION_TIME + 8*BP_DURATION + DL_ABB_DELAY // 8 * 156.25 samples
209 };
210
211 // Window positions for TX normal burst and PRACH transmission
212 const UWORD16 TX_TABLE[8] =
213 {
214 0,
215 BP_DURATION,
216 2*BP_DURATION,
217 3*BP_DURATION,
218 4*BP_DURATION,
219 5*BP_DURATION,
220 6*BP_DURATION,
221 7*BP_DURATION
222 };
223
224 #else
225
226 extern UWORD16 RX_DOWN_TABLE[8];
227 extern UWORD16 TX_TABLE[8];
228
229 #endif
230 #endif
231
232 //===============================================
233 // New Definitions for new WIN-ID implementation
234 //===============================================
235
236 #define BP_SPLIT_PW2 5
237 #define BP_SPLIT 32
238 #define FRAME_SPLIT 8*BP_SPLIT
239
240 // Load for TPU activity according to frame split
241 #define PWR_LOAD 1 + PW_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
242 #define RX_LOAD 1 + NB_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
243
244 #if L1_GPRS
245 #ifdef L1P_DRIVE_C
246
247 // RX split load in case of multislot
248 const UWORD16 RX_SPLIT_TABLE[8] =
249 {
250 1 + (NB_ACQUIS_DURATION ) / (BP_DURATION/BP_SPLIT),
251 1 + (2*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
252 1 + (3*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
253 1 + (4*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
254 1 + (5*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
255 1 + (6*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
256 1 + (7*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
257 1 + (8*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT)
258 };
259
260 #else
261
262 extern UWORD16 RX_SPLIT_TABLE[8];
263
264 #endif
265 #endif
266