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comparison src/cs/system/Main/init.asm @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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-1:000000000000 0:945cf7f506b2
1 ;******************************************************************************
2 ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3 ;
4 ; Property of Texas Instruments -- For Unrestricted Internal Use Only
5 ; Unauthorized reproduction and/or distribution is strictly prohibited. This
6 ; product is protected under copyright law and trade secret law as an
7 ; unpublished work. Created 1987, (C) Copyright 1996 Texas Instruments. All
8 ; rights reserved.
9 ;
10 ;
11 ; Filename : init.asm
12 ;
13 ; Description : Environment configuration
14 ;
15 ; Project : drivers
16 ;
17 ; Author : pmonteil@tif.ti.com Patrice Monteil.
18 ;
19 ; Version number : 1.4
20 ;
21 ; Date and time : 03/06/01 10:44:19
22 ;
23 ; Previous delta : 12/19/00 14:28:47
24 ;
25 ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_C_SAMPLE_REQ1145_BIS/drivers1/board_7/SCCS/s.init.asm
26 ;
27 ; Sccs Id (SID) : '@(#) init.asm 1.4 03/06/01 10:44:19 '
28 ;
29 ;
30 ;*****************************************************************************
31
32 ; use in int.s for first initializations
33
34 .if BOARD = 6
35
36 .if CHIPSET != 12
37 CS0_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little
38 CS1_MEM_REG .short 0x281 ;RAM init : 1 WS, 8 bits, little
39 CS2_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
40 CS3_MEM_REG .short 0x283 ;RAM init : 5 WS, 8 bits, little
41 CS4_MEM_REG .short 0xe85 ;RAM init : 5 WS, 8 bits, little
42 .endif
43
44 .if CHIPSET = 3
45 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
46 .elseif CHIPSET = 4
47 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
48 CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
49 .elseif CHIPSET = 5
50 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
51 .elseif CHIPSET = 6
52 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
53 .elseif CHIPSET = 7
54 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
55 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
56 .elseif CHIPSET = 8
57 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
58 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
59 .elseif CHIPSET = 10
60 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
61 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
62 .elseif CHIPSET = 11
63 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
64 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
65 .elseif CHIPSET = 12
66 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED - RAM init : 1 WS, 16 bits, little
67 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
68 CS5_MEM_REG .short 0x2A1 ;ROM init : 0 WS, 16 bits, little
69 .endif ; CHIPSET = 3, 4, 5, 6, 7, 8, 10 or 11 or 12
70
71 .elseif BOARD = 7
72
73 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
74 .if OP_WCP = 1
75 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
76 .else
77 CS1_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
78 .endif
79 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
80 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
81 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
82 .if CHIPSET = 3
83 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
84 .elseif CHIPSET = 4
85 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
86 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
87 .elseif CHIPSET = 5
88 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
89 .elseif CHIPSET = 6
90 .if OP_WCP = 1
91 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
92 .else
93 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
94 .endif
95 .endif ; CHIPSET = 3, 4, 5 or 6
96
97 .elseif BOARD = 8
98
99 CS0_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
100 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
101 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
102 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
103 CS4_MEM_REG .short 0xe85 ; default reset value
104 .if CHIPSET = 4
105 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
106 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
107 .elseif CHIPSET = 7
108 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
109 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
110 .elseif CHIPSET = 8
111 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
112 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
113 .endif ; CHIPSET = 4, 7 or 8
114 .elseif BOARD = 9
115
116 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
117 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
118 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
119 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
120 CS4_MEM_REG .short 0xe85 ; default reset value
121 .if CHIPSET = 4
122 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
123 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
124 .elseif CHIPSET = 7
125 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
126 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
127 .elseif CHIPSET = 8
128 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
129 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
130 .endif ; CHIPSET = 4, 7 or 8
131
132 .elseif BOARD = 35
133
134 CS0_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
135 CS1_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
136 CS2_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
137 CS6_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
138 CS7_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
139
140 API_ADAPT .equ 0x6A
141 CS7_SIZE .equ 0x2000 ; 8 kB
142 CS7_ADDR .equ 0x03800000 ; Initial address before toggling nIBOOT
143 SRAM_ADDR .equ 0x00800000 ; Internal SRAM start address
144 SRAM_SIZE .equ 0x00050000 ; 2.5 MBits
145 armio_in .word 0xFFFE4800 ; ARMIO_IN register address
146 armio_out .word 0xFFFE4802 ; ARMIO_OUT register address
147 addrExtraConf .word 0xFFFFFB10 ; Extra configuration
148 addrCS7 .word 0xFFFFFB08 ; CS7 configuration
149 DEF_EXTRA_CONF .short 0x033E ; Default configuration
150 EXTRA_CONF .short 0x013E ; Boot configuration
151
152 .elseif BOARD = 40
153
154 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
155 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
156 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
157 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
158 CS4_MEM_REG .short 0xe85 ; default reset value
159
160 .if CHIPSET = 8
161 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
162 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
163 .elseif CHIPSET = 10
164 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
165 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
166 .elseif CHIPSET = 11
167 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
168 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
169 .endif ; CHIPSET = 8, 10 or 11
170
171 .elseif BOARD = 41
172
173 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
174 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
175 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
176 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
177 CS4_MEM_REG .short 0xe85 ; default reset value
178
179 .if CHIPSET = 8
180 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
181 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
182 .elseif CHIPSET = 10
183 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
184 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
185 .elseif CHIPSET = 11
186 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
187 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
188 .endif ; CHIPSET = 8, 10 or 11
189
190 .elseif BOARD = 43
191
192 .if CHIPSET = 12
193 CS0_MEM_REG .short 0x2A0 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little
194 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
195 CS5_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little
196 .endif ; CHIPSET = 12
197
198 .elseif BOARD = 45
199
200 .if CHIPSET = 12
201 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little
202 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
203 CS5_MEM_REG .short 0x2A1 ; init : 0 WS, 16 bits, little
204 .endif ; CHIPSET = 12
205
206 .endif ; BOARD
207
208 CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
209 CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation