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comparison src/cs/layer1/cust0/l1_rf10.c @ 397:a513e7682ccf

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l1_rf10.c: s/ANALOG/ANLG_FAM/
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Jan 2018 01:41:00 +0000
parents 525d9f565947
children 91d64e076fb6
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396:525d9f565947 397:a513e7682ccf
1474 }; 1474 };
1475 1475
1476 /*------------------------------------------*/ 1476 /*------------------------------------------*/
1477 /* ABB Initialization words 1477 /* ABB Initialization words
1478 /*------------------------------------------*/ 1478 /*------------------------------------------*/
1479 #if (ANALOG == 1) 1479 #if (ANLG_FAM == 1)
1480 UWORD16 abb[ABB_TABLE_SIZE] = 1480 UWORD16 abb[ABB_TABLE_SIZE] =
1481 { 1481 {
1482 C_AFCCTLADD, // Value at reset 1482 C_AFCCTLADD, // Value at reset
1483 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute 1483 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute
1484 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB 1484 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB
1489 C_DAI_ON_OFF, // value at reset 1489 C_DAI_ON_OFF, // value at reset
1490 C_AUXDAC, // value at reset 1490 C_AUXDAC, // value at reset
1491 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1 1491 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1
1492 C_APCDEL // value at reset 1492 C_APCDEL // value at reset
1493 }; 1493 };
1494 #elif (ANALOG == 2) 1494 #elif (ANLG_FAM == 2)
1495 UWORD16 abb[ABB_TABLE_SIZE] = 1495 UWORD16 abb[ABB_TABLE_SIZE] =
1496 { 1496 {
1497 C_AFCCTLADD, 1497 C_AFCCTLADD,
1498 C_VBUR, 1498 C_VBUR,
1499 C_VBDR, 1499 C_VBDR,
1508 C_VBCR2, 1508 C_VBCR2,
1509 C_APCDEL, 1509 C_APCDEL,
1510 C_APCDEL2 1510 C_APCDEL2
1511 }; 1511 };
1512 1512
1513 #elif (ANALOG == 3) 1513 #elif (ANLG_FAM == 3)
1514 UWORD16 abb[ABB_TABLE_SIZE] = 1514 UWORD16 abb[ABB_TABLE_SIZE] =
1515 { 1515 {
1516 C_AFCCTLADD, 1516 C_AFCCTLADD,
1517 C_VBUR, 1517 C_VBUR,
1518 C_VBDR, 1518 C_VBDR,