FreeCalypso > hg > fc-magnetite
comparison src/cs/system/main/init.asm @ 604:a7ed7d4483b0
main assembly boot path code: MEMIF change for 26 MHz targets
as explained in the MEMIF-wait-states document
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 17 Jun 2019 02:11:17 +0000 |
parents | 838eeafb0051 |
children |
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603:b13731665274 | 604:a7ed7d4483b0 |
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168 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable | 168 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
169 .endif ; CHIPSET = 8, 10 or 11 | 169 .endif ; CHIPSET = 8, 10 or 11 |
170 | 170 |
171 .elseif BOARD = 41 | 171 .elseif BOARD = 41 |
172 | 172 |
173 ; FreeCalypso change, please see MEMIF-wait-states document | |
174 ; in the freecalypso-docs repository for the explanation. | |
175 | |
176 .if VCXO_26MHZ = 1 | |
177 CS0_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable | |
178 CS1_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable | |
179 CS2_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable | |
180 .else | |
173 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable | 181 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
174 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable | 182 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
175 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable | 183 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
184 .endif | |
185 | |
176 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable | 186 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
177 CS4_MEM_REG .short 0xe85 ; default reset value | 187 CS4_MEM_REG .short 0xe85 ; default reset value |
178 | 188 |
179 .if CHIPSET = 8 | 189 .if CHIPSET = 8 |
180 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable | 190 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |