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comparison cdg3/cdginc-locosto/ccdid.h @ 16:c15047b3d00d

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cdg3: import from freecalypso-citrine/cdg
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 27 Sep 2016 16:27:34 +0000
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15:c8bdae60fcb1 16:c15047b3d00d
1 /*
2 +--------------------------------------------------------------------------+
3 | PROJECT : PROTOCOL STACK |
4 | FILE : ccdid.h |
5 | SOURCE : "msg\rr_com.mdf" |
6 | LastModified : "2004-01-16" |
7 | IdAndVersion : "8010.606.02.008" |
8 | SrcFileTime : "Wed Nov 28 10:20:42 2007" |
9 | Generated by CCDGEN_2.5.5A on Thu Sep 25 09:18:53 2014 |
10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! |
11 +--------------------------------------------------------------------------+
12 */
13
14 typedef enum
15 {
16 /* melemIdx CCD_ID_$(Prefix|Filename)__$(COMP-name)__$(AS-name|VAR-name|COMP-name etc.)*/
17
18 /* 0*/ CCD_ID_RR_COM__a5_bits__a5_1,
19 /* 1*/ CCD_ID_RR_COM__a5_bits__a5_2,
20 /* 2*/ CCD_ID_RR_COM__a5_bits__a5_3,
21 /* 3*/ CCD_ID_RR_COM__a5_bits__a5_4,
22 /* 4*/ CCD_ID_RR_COM__a5_bits__a5_5,
23 /* 5*/ CCD_ID_RR_COM__a5_bits__a5_6,
24 /* 6*/ CCD_ID_RR_COM__a5_bits__a5_7,
25 /* 7*/ CCD_ID_RR_COM__add_acc_tech_elem__acc_tech_typ,
26 /* 8*/ CCD_ID_RR_COM__add_acc_tech_elem__pow_class,
27 /* 9*/ CCD_ID_RR_COM__add_acc_tech_elem__pow_8psk_cap,
28 /* 10*/ CCD_ID_RR_COM__add_acc_tech__add_acc_tech_elem,
29 /* 11*/ CCD_ID_RR_COM__bsic_struct__freq_scroll,
30 /* 12*/ CCD_ID_RR_COM__bsic_struct__bsic,
31 /* 13*/ CCD_ID_RR_COM__gprs_bsic__ba_start_bsic,
32 /* 14*/ CCD_ID_RR_COM__gprs_bsic__bsic,
33 /* 15*/ CCD_ID_RR_COM__gprs_bsic__rem_bsic,
34 /* 16*/ CCD_ID_RR_COM__gprs_bsic__bsic_struct,
35 /* 17*/ CCD_ID_RR_COM__mob_class_1__spare_0,
36 /* 18*/ CCD_ID_RR_COM__mob_class_1__rev_lev,
37 /* 19*/ CCD_ID_RR_COM__mob_class_1__es_ind,
38 /* 20*/ CCD_ID_RR_COM__mob_class_1__a5_1,
39 /* 21*/ CCD_ID_RR_COM__mob_class_1__rf_pow_cap,
40 /* 22*/ CCD_ID_RR_COM__mob_class_2__spare_0,
41 /* 23*/ CCD_ID_RR_COM__mob_class_2__rev_lev,
42 /* 24*/ CCD_ID_RR_COM__mob_class_2__es_ind,
43 /* 25*/ CCD_ID_RR_COM__mob_class_2__a5_1,
44 /* 26*/ CCD_ID_RR_COM__mob_class_2__rf_pow_cap,
45 /* 27*/ CCD_ID_RR_COM__mob_class_2__spare_1,
46 /* 28*/ CCD_ID_RR_COM__mob_class_2__ps,
47 /* 29*/ CCD_ID_RR_COM__mob_class_2__ss_screen,
48 /* 30*/ CCD_ID_RR_COM__mob_class_2__mt_pp_sms,
49 /* 31*/ CCD_ID_RR_COM__mob_class_2__vbs,
50 /* 32*/ CCD_ID_RR_COM__mob_class_2__vgcs,
51 /* 33*/ CCD_ID_RR_COM__mob_class_2__egsm,
52 /* 34*/ CCD_ID_RR_COM__mob_class_2__class3,
53 /* 35*/ CCD_ID_RR_COM__mob_class_2__spare_2,
54 /* 36*/ CCD_ID_RR_COM__mob_class_2__lcsva,
55 /* 37*/ CCD_ID_RR_COM__mob_class_2__ucs2_treat,
56 /* 38*/ CCD_ID_RR_COM__mob_class_2__solsa,
57 /* 39*/ CCD_ID_RR_COM__mob_class_2__cmsp,
58 /* 40*/ CCD_ID_RR_COM__mob_class_2__a5_3,
59 /* 41*/ CCD_ID_RR_COM__mob_class_2__a5_2,
60 /* 42*/ CCD_ID_RR_COM__dtm_ms__dtm_g_ms_class,
61 /* 43*/ CCD_ID_RR_COM__dtm_ms__mac_support,
62 /* 44*/ CCD_ID_RR_COM__dtm_ms__dtm_e_ms_class,
63 /* 45*/ CCD_ID_RR_COM__dtm_high_ms__dtm_g_high_ms_class,
64 /* 46*/ CCD_ID_RR_COM__dtm_high_ms__offset_required,
65 /* 47*/ CCD_ID_RR_COM__dtm_high_ms__dtm_e_high_ms_class,
66 /* 48*/ CCD_ID_RR_COM__egde_struct__mod,
67 /* 49*/ CCD_ID_RR_COM__egde_struct__egde_pow1,
68 /* 50*/ CCD_ID_RR_COM__egde_struct__egde_pow2,
69 /* 51*/ CCD_ID_RR_COM__gprs_rep_prio__num_cells,
70 /* 52*/ CCD_ID_RR_COM__gprs_rep_prio__rep_priority,
71 /* 53*/ CCD_ID_RR_COM__gsm400_struct__gsm400_supp,
72 /* 54*/ CCD_ID_RR_COM__gsm400_struct__gsm400_cap,
73 /* 55*/ CCD_ID_RR_COM__t_gsm400_struct__t_gsm400_supp,
74 /* 56*/ CCD_ID_RR_COM__t_gsm400_struct__t_gsm400_cap,
75 /* 57*/ CCD_ID_RR_COM__measurement__sms_val,
76 /* 58*/ CCD_ID_RR_COM__measurement__sm_val,
77 /* 59*/ CCD_ID_RR_COM__pos_method__assist_eotd,
78 /* 60*/ CCD_ID_RR_COM__pos_method__based_eotd,
79 /* 61*/ CCD_ID_RR_COM__pos_method__assist_gps,
80 /* 62*/ CCD_ID_RR_COM__pos_method__based_gps,
81 /* 63*/ CCD_ID_RR_COM__pos_method__conv_gps,
82 /* 64*/ CCD_ID_RR_COM__pow_class4__spare_0,
83 /* 65*/ CCD_ID_RR_COM__pow_class4__pow_class,
84 /* 66*/ CCD_ID_RR_COM__dtm_struct__dtm_g_ms_class,
85 /* 67*/ CCD_ID_RR_COM__dtm_struct__mac_support,
86 /* 68*/ CCD_ID_RR_COM__dtm_struct__dtm_e_ms_class,
87 /* 69*/ CCD_ID_RR_COM__egprs_struct__egprs_ms_class,
88 /* 70*/ CCD_ID_RR_COM__egprs_struct__egprs_eda,
89 /* 71*/ CCD_ID_RR_COM__gprs_struct__gprs_ms_class,
90 /* 72*/ CCD_ID_RR_COM__gprs_struct__gprs_eda,
91 /* 73*/ CCD_ID_RR_COM__rf_ms__gsm_ms_class,
92 /* 74*/ CCD_ID_RR_COM__rf_ms__spare_0,
93 /* 75*/ CCD_ID_RR_COM__rf_ms__edge_ms_class,
94 /* 76*/ CCD_ID_RR_COM__rf_ms__spare_1,
95 /* 77*/ CCD_ID_RR_COM__rf_ms__hscsd_ms_class,
96 /* 78*/ CCD_ID_RR_COM__rf_ms__spare_2,
97 /* 79*/ CCD_ID_RR_COM__rf_ms__gprs_ms_class,
98 /* 80*/ CCD_ID_RR_COM__rf_ms__dtm_g,
99 /* 81*/ CCD_ID_RR_COM__rf_ms__dtm_g_ms_class,
100 /* 82*/ CCD_ID_RR_COM__rf_ms__ecsd_ms_class,
101 /* 83*/ CCD_ID_RR_COM__rf_ms__spare_3,
102 /* 84*/ CCD_ID_RR_COM__rf_ms__egprs_ms_class,
103 /* 85*/ CCD_ID_RR_COM__rf_ms__dtm_e,
104 /* 86*/ CCD_ID_RR_COM__rf_ms__dtm_e_ms_class,
105 /* 87*/ CCD_ID_RR_COM__rtds6__rtd6,
106 /* 88*/ CCD_ID_RR_COM__rtdd6__ba_start_rtd,
107 /* 89*/ CCD_ID_RR_COM__rtdd6__rtds6,
108 /* 90*/ CCD_ID_RR_COM__rtdd6__rtds6_add,
109 /* 91*/ CCD_ID_RR_COM__rtds12__rtd12,
110 /* 92*/ CCD_ID_RR_COM__rtdd12__ba_start_rtd,
111 /* 93*/ CCD_ID_RR_COM__rtdd12__rtds12,
112 /* 94*/ CCD_ID_RR_COM__rtdd12__rtds12_add,
113 /* 95*/ CCD_ID_RR_COM__rtdd__rtdd6,
114 /* 96*/ CCD_ID_RR_COM__rtdd__rtdd12,
115 /* 97*/ CCD_ID_RR_COM__report_900__rep_offset_900,
116 /* 98*/ CCD_ID_RR_COM__report_900__th_rep_900,
117 /* 99*/ CCD_ID_RR_COM__report_1800__rep_offset_1800,
118 /* 100*/ CCD_ID_RR_COM__report_1800__th_rep_1800,
119 /* 101*/ CCD_ID_RR_COM__report_400__rep_offset_400,
120 /* 102*/ CCD_ID_RR_COM__report_400__th_rep_400,
121 /* 103*/ CCD_ID_RR_COM__report_1900__rep_offset_1900,
122 /* 104*/ CCD_ID_RR_COM__report_1900__th_rep_1900,
123 /* 105*/ CCD_ID_RR_COM__report_850__rep_offset_850,
124 /* 106*/ CCD_ID_RR_COM__report_850__th_rep_850,
125 /* 107*/ CCD_ID_RR_COM__sms_sm_value__sms_val,
126 /* 108*/ CCD_ID_RR_COM__sms_sm_value__sm_val,
127 /* 109*/ CCD_ID_RR_COM__ms_struct__hscsd_ms_class,
128 /* 110*/ CCD_ID_RR_COM__ms_struct__gprs_struct,
129 /* 111*/ CCD_ID_RR_COM__ms_struct__sms_sm_value,
130 /* 112*/ CCD_ID_RR_COM__ms_struct__ecsd_ms_class,
131 /* 113*/ CCD_ID_RR_COM__ms_struct__egprs_struct,
132 /* 114*/ CCD_ID_RR_COM__ms_struct__dtm_struct,
133 /* 115*/ CCD_ID_RR_COM__acc_cap__pow_class,
134 /* 116*/ CCD_ID_RR_COM__acc_cap__a5_bits,
135 /* 117*/ CCD_ID_RR_COM__acc_cap__es_ind,
136 /* 118*/ CCD_ID_RR_COM__acc_cap__ps,
137 /* 119*/ CCD_ID_RR_COM__acc_cap__vgcs,
138 /* 120*/ CCD_ID_RR_COM__acc_cap__vbs,
139 /* 121*/ CCD_ID_RR_COM__acc_cap__ms_struct,
140 /* 122*/ CCD_ID_RR_COM__acc_cap__pow_8psk_cap,
141 /* 123*/ CCD_ID_RR_COM__acc_cap__compact,
142 /* 124*/ CCD_ID_RR_COM__acc_cap__rev99,
143 /* 125*/ CCD_ID_RR_COM__acc_cap__umts_fdd,
144 /* 126*/ CCD_ID_RR_COM__acc_cap__umts_tdd,
145 /* 127*/ CCD_ID_RR_COM__acc_cap__cdma2000,
146 /* 128*/ CCD_ID_RR_COM__ra_cap_values__acc_tech_typ,
147 /* 129*/ CCD_ID_RR_COM__ra_cap_values__acc_cap,
148 /* 130*/ CCD_ID_RR_COM__ra_cap_values__add_acc_tech,
149 /* 131*/ CCD_ID_RR_COM__ra_cap_r__ra_cap_values,
150 /* 132*/ CCD_ID_RR_COM__ra_cap__ra_cap_values,
151 /* 133*/ CCD_ID_RR_COM__ra_cap__ra_cap_r,
152 /* 134*/ CCD_ID_RR_COM__ra_cap__acc_tech_typ,
153 /* 135*/ CCD_ID_RR_COM__ra_cap__acc_cap,
154 /* 136*/ CCD_ID_RR_COM__rf_power__pow_class4,
155 /* 137*/ CCD_ID_RR_COM__rf_power__egde_pow1,
156 /* 138*/ CCD_ID_RR_COM__rf_power__egde_pow2,
157 /* 139*/ CCD_ID_RR_COM__rf_cap__setbands,
158 /* 140*/ CCD_ID_RR_COM__rf_cap__bands,
159 /* 141*/ CCD_ID_RR_COM__rf_cap__rf_power,
160 /* 142*/ CCD_ID_RR_COM__rf_cap__rf_ms,
161 /* 143*/ CCD_ID_RR_COM__rf_cap__es_ind,
162 /* 144*/ CCD_ID_RR_COM__rf_cap__ps,
163 /* 145*/ CCD_ID_RR_COM__rf_cap__mt_pp_sms,
164 /* 146*/ CCD_ID_RR_COM__rf_cap__lcsva,
165 /* 147*/ CCD_ID_RR_COM__rf_cap__solsa,
166 /* 148*/ CCD_ID_RR_COM__rf_cap__cmsp,
167 /* 149*/ CCD_ID_RR_COM__rf_cap__mod,
168 /* 150*/ CCD_ID_RR_COM__rf_cap__mac_support,
169 /* 151*/ CCD_ID_RR_COM__rf_cap__meas,
170 /* 152*/ CCD_ID_RR_COM__rf_cap__ext_meas,
171 /* 153*/ CCD_ID_RR_COM__rf_cap__compact,
172 /* 154*/ CCD_ID_RR_COM__rf_cap__vbs,
173 /* 155*/ CCD_ID_RR_COM__rf_cap__vgcs,
174 /* 156*/ CCD_ID_RR_COM__rf_cap__ucs2_treat,
175 /* 157*/ CCD_ID_RR_COM__rf_cap__ss_screen,
176 /* 158*/ CCD_ID_RR_COM__rf_cap__sms_val,
177 /* 159*/ CCD_ID_RR_COM__rf_cap__sm_val,
178 /* 160*/ CCD_ID_RR_COM__rf_cap__a5_bits,
179 /* 161*/ CCD_ID_RR_COM__rf_cap__spare_0,
180 /* 162*/ CCD_ID_RR_COM__rf_cap__assist_eotd,
181 /* 163*/ CCD_ID_RR_COM__rf_cap__based_eotd,
182 /* 164*/ CCD_ID_RR_COM__rf_cap__assist_gps,
183 /* 165*/ CCD_ID_RR_COM__rf_cap__based_gps,
184 /* 166*/ CCD_ID_RR_COM__rf_cap__conv_gps,
185 /* 167*/ CCD_ID_RR_COM__rf_cap__gprs_eda,
186 /* 168*/ CCD_ID_RR_COM__rf_cap__egprs_eda,
187 /* 169*/ CCD_ID_RR_COM__rf_cap__spare_1,
188 /* 170*/ CCD_ID_RR_COM__pan_struct__dec,
189 /* 171*/ CCD_ID_RR_COM__pan_struct__inc,
190 /* 172*/ CCD_ID_RR_COM__pan_struct__pmax,
191 /* 173*/ CCD_ID_RR_COM__ccn_support_description__num_cells,
192 /* 174*/ CCD_ID_RR_COM__ccn_support_description__ccn_support,
193 /* 175*/ CCD_ID_RR_COM__ext_dtm_ms__ext_dtm_g_ms_class,
194 /* 176*/ CCD_ID_RR_COM__ext_dtm_ms__ext_dtm_e_ms_class,
195 /* 177*/ CCD_ID_RR_COM__mob_class_3__spare_0,
196 /* 178*/ CCD_ID_RR_COM__mob_class_3__mb_value,
197 /* 179*/ CCD_ID_RR_COM__mob_class_3__a5_7,
198 /* 180*/ CCD_ID_RR_COM__mob_class_3__a5_6,
199 /* 181*/ CCD_ID_RR_COM__mob_class_3__a5_5,
200 /* 182*/ CCD_ID_RR_COM__mob_class_3__a5_4,
201 /* 183*/ CCD_ID_RR_COM__mob_class_3__radio_cap_2,
202 /* 184*/ CCD_ID_RR_COM__mob_class_3__spare_1,
203 /* 185*/ CCD_ID_RR_COM__mob_class_3__radio_cap_1,
204 /* 186*/ CCD_ID_RR_COM__mob_class_3__rgsm_class,
205 /* 187*/ CCD_ID_RR_COM__mob_class_3__ms_class,
206 /* 188*/ CCD_ID_RR_COM__mob_class_3__ucs2_treat,
207 /* 189*/ CCD_ID_RR_COM__mob_class_3__ext_meas,
208 /* 190*/ CCD_ID_RR_COM__mob_class_3__measurement,
209 /* 191*/ CCD_ID_RR_COM__mob_class_3__pos_method,
210 /* 192*/ CCD_ID_RR_COM__mob_class_3__edge_ms_class,
211 /* 193*/ CCD_ID_RR_COM__mob_class_3__egde_struct,
212 /* 194*/ CCD_ID_RR_COM__mob_class_3__gsm400_struct,
213 /* 195*/ CCD_ID_RR_COM__mob_class_3__gsm850_cap,
214 /* 196*/ CCD_ID_RR_COM__mob_class_3__pcs1900_cap,
215 /* 197*/ CCD_ID_RR_COM__mob_class_3__umts_fdd,
216 /* 198*/ CCD_ID_RR_COM__mob_class_3__umts_tdd,
217 /* 199*/ CCD_ID_RR_COM__mob_class_3__cdma2000,
218 /* 200*/ CCD_ID_RR_COM__mob_class_3__dtm_ms,
219 /* 201*/ CCD_ID_RR_COM__mob_class_3__single_band,
220 /* 202*/ CCD_ID_RR_COM__mob_class_3__gsm700_cap,
221 /* 203*/ CCD_ID_RR_COM__mob_class_3__umts_tdd_128,
222 /* 204*/ CCD_ID_RR_COM__mob_class_3__geran_feat_pack_1,
223 /* 205*/ CCD_ID_RR_COM__mob_class_3__ext_dtm_ms,
224 /* 206*/ CCD_ID_RR_COM__mob_class_3__high_ms_cap,
225 /* 207*/ CCD_ID_RR_COM__mob_class_3__geran_iu_mod_cap,
226 /* 208*/ CCD_ID_RR_COM__mob_class_3__geran_feat_pack_2,
227 /* 209*/ CCD_ID_RR_COM__mob_class_3__gmsk_ms_pwr_prof,
228 /* 210*/ CCD_ID_RR_COM__mob_class_3__psk8_ms_pwr_prof,
229 /* 211*/ CCD_ID_RR_COM__mob_class_3__t_gsm400_struct,
230 /* 212*/ CCD_ID_RR_COM__mob_class_3__t_gsm900_cap,
231 /* 213*/ CCD_ID_RR_COM__mob_class_3__dl_adv_rx_per,
232 /* 214*/ CCD_ID_RR_COM__mob_class_3__dtm_enhance_cap,
233 /* 215*/ CCD_ID_RR_COM__mob_class_3__dtm_high_ms,
234 /* 216*/ CCD_ID_RR_COM__mob_class_3__rep_acch_cap,
235 /* 217*/ CCD_ID_RR_COM__mob_class_3__spare_2,
236 /* 218*/ CCD_ID_RR_COM__tdd_ci_struct__tdd_indic0,
237 /* 219*/ CCD_ID_RR_COM__tdd_ci_struct__tdd_ncell_data,
238 /* 220*/ CCD_ID_RR_COM__fdd_ci_struct__fdd_indic0,
239 /* 221*/ CCD_ID_RR_COM__fdd_ci_struct__fdd_ncell_data,
240 /* 222*/ CCD_ID_RR_COM__rep_u_tdd_cells__flag,
241 /* 223*/ CCD_ID_RR_COM__rep_u_tdd_cells__tdd_arfcn,
242 /* 224*/ CCD_ID_RR_COM__rep_u_tdd_cells__tdd_arfcn_index,
243 /* 225*/ CCD_ID_RR_COM__rep_u_tdd_cells__tdd_ci_struct,
244 /* 226*/ CCD_ID_RR_COM__rep_u_fdd_cells__flag,
245 /* 227*/ CCD_ID_RR_COM__rep_u_fdd_cells__fdd_arfcn,
246 /* 228*/ CCD_ID_RR_COM__rep_u_fdd_cells__fdd_arfcn_index,
247 /* 229*/ CCD_ID_RR_COM__rep_u_fdd_cells__fdd_ci_struct,
248 /* 230*/ CCD_ID_RR_COM__utran_tdd__bw_tdd,
249 /* 231*/ CCD_ID_RR_COM__utran_tdd__rep_u_tdd_cells,
250 /* 232*/ CCD_ID_RR_COM__utran_fdd__bw_fdd,
251 /* 233*/ CCD_ID_RR_COM__utran_fdd__rep_u_fdd_cells,
252 /* 234*/ CCD_ID_RR_COM__threeg_cells__index_start_3g,
253 /* 235*/ CCD_ID_RR_COM__threeg_cells__abs_index_emr,
254 /* 236*/ CCD_ID_RR_COM__threeg_cells__utran_fdd,
255 /* 237*/ CCD_ID_RR_COM__threeg_cells__utran_tdd,
256 /* 238*/ CCD_ID_RR_COM__cd2k_str_000__td_mode,
257 /* 239*/ CCD_ID_RR_COM__cd2k_str_000__td_power_level,
258 /* 240*/ CCD_ID_RR_COM__cd2k_str_001__qof,
259 /* 241*/ CCD_ID_RR_COM__cd2k_str_001__walsh_len_a,
260 /* 242*/ CCD_ID_RR_COM__cd2k_str_001__aux_pilot_walsh,
261 /* 243*/ CCD_ID_RR_COM__cd2k_str_010__qof,
262 /* 244*/ CCD_ID_RR_COM__cd2k_str_010__walsh_len_b,
263 /* 245*/ CCD_ID_RR_COM__cd2k_str_010__aux_td_walsh,
264 /* 246*/ CCD_ID_RR_COM__cd2k_str_010__aux_td_power_level,
265 /* 247*/ CCD_ID_RR_COM__cd2k_str_010__td_mode,
266 /* 248*/ CCD_ID_RR_COM__cd2k_str_011__sr3_prim_pilot,
267 /* 249*/ CCD_ID_RR_COM__cd2k_str_011__sr3_pilot_power1,
268 /* 250*/ CCD_ID_RR_COM__cd2k_str_011__sr3_pilot_power2,
269 /* 251*/ CCD_ID_RR_COM__cd2k_str_110_1__qof1,
270 /* 252*/ CCD_ID_RR_COM__cd2k_str_110_1__walsh_length1,
271 /* 253*/ CCD_ID_RR_COM__cd2k_str_110_1__aux_pilot_walsh1,
272 /* 254*/ CCD_ID_RR_COM__cd2k_str_110_2__qof2,
273 /* 255*/ CCD_ID_RR_COM__cd2k_str_110_2__walsh_length2,
274 /* 256*/ CCD_ID_RR_COM__cd2k_str_110_2__aux_pilot_walsh2,
275 /* 257*/ CCD_ID_RR_COM__cd2k_str_110__cd2k_str_011,
276 /* 258*/ CCD_ID_RR_COM__cd2k_str_110__qof,
277 /* 259*/ CCD_ID_RR_COM__cd2k_str_110__walsh_len_c,
278 /* 260*/ CCD_ID_RR_COM__cd2k_str_110__aux_walsh_len,
279 /* 261*/ CCD_ID_RR_COM__cd2k_str_110__cd2k_str_110_1,
280 /* 262*/ CCD_ID_RR_COM__cd2k_str_110__cd2k_str_110_2,
281 /* 263*/ CCD_ID_RR_COM__cd2k_str_all__flag_3bit,
282 /* 264*/ CCD_ID_RR_COM__cd2k_str_all__cd2k_str_000,
283 /* 265*/ CCD_ID_RR_COM__cd2k_str_all__cd2k_str_001,
284 /* 266*/ CCD_ID_RR_COM__cd2k_str_all__cd2k_str_010,
285 /* 267*/ CCD_ID_RR_COM__cd2k_str_all__cd2k_str_011,
286 /* 268*/ CCD_ID_RR_COM__cd2k_str_all__cd2k_str_110,
287 /* 269*/ CCD_ID_RR_COM__cd2k_cell_str__pilot_PN_offset,
288 /* 270*/ CCD_ID_RR_COM__cd2k_cell_str__cd2k_str_all,
289 /* 271*/ CCD_ID_RR_COM__cdma2000_cell_desc__cdma2000_frequency_band,
290 /* 272*/ CCD_ID_RR_COM__cdma2000_cell_desc__cdma2000_frequency,
291 /* 273*/ CCD_ID_RR_COM__cdma2000_cell_desc__number_cdma2000_cells,
292 /* 274*/ CCD_ID_RR_COM__cdma2000_cell_desc__cd2k_cell_str,
293 /* 275*/ CCD_ID_RR_COM__fdd_report__fdd_rep_offset,
294 /* 276*/ CCD_ID_RR_COM__fdd_report__fdd_rep_thres,
295 /* 277*/ CCD_ID_RR_COM__tdd_rep__tdd_rep_offset,
296 /* 278*/ CCD_ID_RR_COM__tdd_rep__tdd_rep_thres,
297 /* 279*/ CCD_ID_RR_COM__cdma2000_rep__cdma2000_rep_offset,
298 /* 280*/ CCD_ID_RR_COM__cdma2000_rep__cdma2000_rep_thres,
299 /* 281*/ CCD_ID_RR_COM__egprs_pck_ch_req_bep_per__egprs_packet_channel_request,
300 /* 282*/ CCD_ID_RR_COM__egprs_pck_ch_req_bep_per__bep_period,
301 /* 283*/ CCD_ID_RR_COM__gprs_ext_info__flag,
302 /* 284*/ CCD_ID_RR_COM__gprs_ext_info__egprs_pck_ch_req_bep_per,
303 /* 285*/ CCD_ID_RR_COM__gprs_ext_info__pfc_feature_mode,
304 /* 286*/ CCD_ID_RR_COM__gprs_ext_info__dtm_support,
305 /* 287*/ CCD_ID_RR_COM__gprs_ext_info__bss_paging_coord,
306 /* 288*/ CCD_ID_RR_COM__gprs_ext_info__ccn_active,
307 /* 289*/ CCD_ID_RR_COM__gprs_ext_info__nw_ext_ul_tbf,
308 /* 290*/ CCD_ID_RR_COM__gprs_ext_bits__ext_len,
309 /* 291*/ CCD_ID_RR_COM__gprs_ext_bits__gprs_ext_info,
310 /* 292*/ CCD_ID_RR_COM__gprs_ext_bits__ext_len,
311 /* 293*/ CCD_ID_RR_COM__gprs_cell_opt__nmo,
312 /* 294*/ CCD_ID_RR_COM__gprs_cell_opt__t3168,
313 /* 295*/ CCD_ID_RR_COM__gprs_cell_opt__t3192,
314 /* 296*/ CCD_ID_RR_COM__gprs_cell_opt__drx_t_max,
315 /* 297*/ CCD_ID_RR_COM__gprs_cell_opt__ab_type,
316 /* 298*/ CCD_ID_RR_COM__gprs_cell_opt__ctrl_ack_type,
317 /* 299*/ CCD_ID_RR_COM__gprs_cell_opt__bs_cv_max,
318 /* 300*/ CCD_ID_RR_COM__gprs_cell_opt__pan_struct,
319 /* 301*/ CCD_ID_RR_COM__gprs_cell_opt__gprs_ext_bits,
320 /* 302*/ CCD_ID_RR_COM__MS_RF_CAPABILITY__msg_type,
321 /* 303*/ CCD_ID_RR_COM__MS_RF_CAPABILITY__rf_cap,
322 /* 304*/ CCD_ID_RR__alpha_gamma__alpha,
323 /* 305*/ CCD_ID_RR__alpha_gamma__gamma,
324 /* 306*/ CCD_ID_RR__apdu_data__apdu_info,
325 /* 307*/ CCD_ID_RR__apdu_flags__spare_0,
326 /* 308*/ CCD_ID_RR__apdu_flags__c_r,
327 /* 309*/ CCD_ID_RR__apdu_flags__f_seg,
328 /* 310*/ CCD_ID_RR__apdu_flags__l_seg,
329 /* 311*/ CCD_ID_RR__apdu_id__protoc_ident,
330 /* 312*/ CCD_ID_RR__cell_desc__bcch_arfcn_hi,
331 /* 313*/ CCD_ID_RR__cell_desc__ncc,
332 /* 314*/ CCD_ID_RR__cell_desc__bcc,
333 /* 315*/ CCD_ID_RR__cell_desc__bcch_arfcn_lo,
334 /* 316*/ CCD_ID_RR__cell_opt_bcch__spare_0,
335 /* 317*/ CCD_ID_RR__cell_opt_bcch__pow_ctrl,
336 /* 318*/ CCD_ID_RR__cell_opt_bcch__dtx_b,
337 /* 319*/ CCD_ID_RR__cell_opt_bcch__rlt,
338 /* 320*/ CCD_ID_RR__cell_opt_sacch__dtx2_s,
339 /* 321*/ CCD_ID_RR__cell_opt_sacch__pow_ctrl,
340 /* 322*/ CCD_ID_RR__cell_opt_sacch__dtx_s,
341 /* 323*/ CCD_ID_RR__cell_opt_sacch__rlt,
342 /* 324*/ CCD_ID_RR__cell_select__cell_resel_hyst,
343 /* 325*/ CCD_ID_RR__cell_select__ms_txpwr_max_cch,
344 /* 326*/ CCD_ID_RR__cell_select__acs,
345 /* 327*/ CCD_ID_RR__cell_select__neci,
346 /* 328*/ CCD_ID_RR__cell_select__rxlev_access_min,
347 /* 329*/ CCD_ID_RR__chan_desc__chan_type,
348 /* 330*/ CCD_ID_RR__chan_desc__tn,
349 /* 331*/ CCD_ID_RR__chan_desc__tsc,
350 /* 332*/ CCD_ID_RR__chan_desc__hop,
351 /* 333*/ CCD_ID_RR__chan_desc__spare_0,
352 /* 334*/ CCD_ID_RR__chan_desc__arfcn,
353 /* 335*/ CCD_ID_RR__chan_desc__maio,
354 /* 336*/ CCD_ID_RR__chan_desc__hsn,
355 /* 337*/ CCD_ID_RR__chan_needed__cn2,
356 /* 338*/ CCD_ID_RR__chan_needed__cn1,
357 /* 339*/ CCD_ID_RR__chan_needed3_4__cn3,
358 /* 340*/ CCD_ID_RR__chan_needed3_4__cn4,
359 /* 341*/ CCD_ID_RR__chan_req_desc__or_ty,
360 /* 342*/ CCD_ID_RR__chan_req_desc__spare_0,
361 /* 343*/ CCD_ID_RR__chan_req_desc__spare_1,
362 /* 344*/ CCD_ID_RR__chan_req_desc__spare_2,
363 /* 345*/ CCD_ID_RR__chan_req_desc__crd_prio,
364 /* 346*/ CCD_ID_RR__chan_req_desc__rlc_mode,
365 /* 347*/ CCD_ID_RR__chan_req_desc__llc_fr_type,
366 /* 348*/ CCD_ID_RR__chan_req_desc__rbw,
367 /* 349*/ CCD_ID_RR__chan_req_desc__rlc_c_oct,
368 /* 350*/ CCD_ID_RR__ciph_key_num__spare_0,
369 /* 351*/ CCD_ID_RR__ciph_key_num__key_seq,
370 /* 352*/ CCD_ID_RR__ciph_mode_set__algo_ident,
371 /* 353*/ CCD_ID_RR__ciph_mode_set__sc,
372 /* 354*/ CCD_ID_RR__ciph_res__spare_0,
373 /* 355*/ CCD_ID_RR__ciph_res__cr,
374 /* 356*/ CCD_ID_RR__cod_prop__codec_thr,
375 /* 357*/ CCD_ID_RR__cod_prop__codec_hyst,
376 /* 358*/ CCD_ID_RR__ctrl_chan_desc__mscr,
377 /* 359*/ CCD_ID_RR__ctrl_chan_desc__att,
378 /* 360*/ CCD_ID_RR__ctrl_chan_desc__bs_ag_blks_res,
379 /* 361*/ CCD_ID_RR__ctrl_chan_desc__ccch_conf,
380 /* 362*/ CCD_ID_RR__ctrl_chan_desc__spare_0,
381 /* 363*/ CCD_ID_RR__ctrl_chan_desc__bs_pa_mfrms,
382 /* 364*/ CCD_ID_RR__ctrl_chan_desc__t3212,
383 /* 365*/ CCD_ID_RR__dgcr__gcr,
384 /* 366*/ CCD_ID_RR__dgcr__sf,
385 /* 367*/ CCD_ID_RR__dgcr__af,
386 /* 368*/ CCD_ID_RR__dgcr__call_prio,
387 /* 369*/ CCD_ID_RR__dgcr__group_ckn,
388 /* 370*/ CCD_ID_RR__ext_meas_res__sc_used,
389 /* 371*/ CCD_ID_RR__ext_meas_res__dtx_used,
390 /* 372*/ CCD_ID_RR__ext_meas_res__rx_lev_ncell,
391 /* 373*/ CCD_ID_RR__freq_chan_seq__spare_0,
392 /* 374*/ CCD_ID_RR__freq_chan_seq__low_arfcn,
393 /* 375*/ CCD_ID_RR__freq_chan_seq__inc_skip,
394 /* 376*/ CCD_ID_RR__freq_range__freq_lower,
395 /* 377*/ CCD_ID_RR__freq_range__freq_higher,
396 /* 378*/ CCD_ID_RR__ba_list_pref__freq_range,
397 /* 379*/ CCD_ID_RR__ba_list_pref__arfcn,
398 /* 380*/ CCD_ID_RR__ba_list_pref__spare_0,
399 /* 381*/ CCD_ID_RR__ba_range__num_range,
400 /* 382*/ CCD_ID_RR__ba_range__freq_range,
401 /* 383*/ CCD_ID_RR__gprs_indic__ra_color,
402 /* 384*/ CCD_ID_RR__gprs_indic__si13_pos,
403 /* 385*/ CCD_ID_RR__gprs_meas_res__c_val,
404 /* 386*/ CCD_ID_RR__gprs_meas_res__rxqual,
405 /* 387*/ CCD_ID_RR__gprs_meas_res__spare_0,
406 /* 388*/ CCD_ID_RR__gprs_meas_res__sign_var,
407 /* 389*/ CCD_ID_RR__gprs_ma__hsn,
408 /* 390*/ CCD_ID_RR__gprs_ma__rfln,
409 /* 391*/ CCD_ID_RR__gprs_ma__hop,
410 /* 392*/ CCD_ID_RR__gprs_ma__allo_len6,
411 /* 393*/ CCD_ID_RR__gprs_ma__allo_bmp6,
412 /* 394*/ CCD_ID_RR__gprs_ma__arfcn_idx,
413 /* 395*/ CCD_ID_RR__gprs_resum__spare_0,
414 /* 396*/ CCD_ID_RR__gprs_resum__res_ack,
415 /* 397*/ CCD_ID_RR__group_chan_desc__chan_type,
416 /* 398*/ CCD_ID_RR__group_chan_desc__tn,
417 /* 399*/ CCD_ID_RR__group_chan_desc__tsc,
418 /* 400*/ CCD_ID_RR__group_chan_desc__hop,
419 /* 401*/ CCD_ID_RR__group_chan_desc__spare_0,
420 /* 402*/ CCD_ID_RR__group_chan_desc__arfcn,
421 /* 403*/ CCD_ID_RR__group_chan_desc__maio,
422 /* 404*/ CCD_ID_RR__group_chan_desc__hsn,
423 /* 405*/ CCD_ID_RR__group_chan_desc__mac,
424 /* 406*/ CCD_ID_RR__hop_freq__flag,
425 /* 407*/ CCD_ID_RR__hop_freq__ma_len,
426 /* 408*/ CCD_ID_RR__hop_freq__mac,
427 /* 409*/ CCD_ID_RR__hop_freq__freq_short_list2,
428 /* 410*/ CCD_ID_RR__gr_ch_desc__chan_type,
429 /* 411*/ CCD_ID_RR__gr_ch_desc__tn,
430 /* 412*/ CCD_ID_RR__gr_ch_desc__tsc,
431 /* 413*/ CCD_ID_RR__gr_ch_desc__hop,
432 /* 414*/ CCD_ID_RR__gr_ch_desc__spare_0,
433 /* 415*/ CCD_ID_RR__gr_ch_desc__arfcn,
434 /* 416*/ CCD_ID_RR__gr_ch_desc__maio,
435 /* 417*/ CCD_ID_RR__gr_ch_desc__hsn,
436 /* 418*/ CCD_ID_RR__gr_ch_desc__hop_freq,
437 /* 419*/ CCD_ID_RR__gr_call_info__dgcr,
438 /* 420*/ CCD_ID_RR__gr_call_info__gr_ch_desc,
439 /* 421*/ CCD_ID_RR__ia_freq_par__fp_len,
440 /* 422*/ CCD_ID_RR__ia_freq_par__spare_0,
441 /* 423*/ CCD_ID_RR__ia_freq_par__maio,
442 /* 424*/ CCD_ID_RR__ia_freq_par__mac,
443 /* 425*/ CCD_ID_RR__ia_2nd_part__ext_ra,
444 /* 426*/ CCD_ID_RR__iar_rest_oct__ext_ra,
445 /* 427*/ CCD_ID_RR__iar_rest_oct__spare_0,
446 /* 428*/ CCD_ID_RR__loc_area_ident__mcc,
447 /* 429*/ CCD_ID_RR__loc_area_ident__mnc,
448 /* 430*/ CCD_ID_RR__loc_area_ident__lac,
449 /* 431*/ CCD_ID_RR__lsa_id_info__lsa_id,
450 /* 432*/ CCD_ID_RR__lsa_id_info__lsa_id_add,
451 /* 433*/ CCD_ID_RR__chan_coding__mac_mode,
452 /* 434*/ CCD_ID_RR__chan_coding__cod_scheme,
453 /* 435*/ CCD_ID_RR__mob_alloc__mac,
454 /* 436*/ CCD_ID_RR__mob_ident__ident_type,
455 /* 437*/ CCD_ID_RR__mob_ident__odd_even,
456 /* 438*/ CCD_ID_RR__mob_ident__ident_dig,
457 /* 439*/ CCD_ID_RR__mob_ident__spare_0,
458 /* 440*/ CCD_ID_RR__mob_ident__tmsi_1,
459 /* 441*/ CCD_ID_RR__mob_time_diff__diff,
460 /* 442*/ CCD_ID_RR__mob_time_diff__spare_0,
461 /* 443*/ CCD_ID_RR__multirate_conf__tlv_len,
462 /* 444*/ CCD_ID_RR__multirate_conf__mr_vers,
463 /* 445*/ CCD_ID_RR__multirate_conf__nscb,
464 /* 446*/ CCD_ID_RR__multirate_conf__icmi,
465 /* 447*/ CCD_ID_RR__multirate_conf__spare_0,
466 /* 448*/ CCD_ID_RR__multirate_conf__st_mode,
467 /* 449*/ CCD_ID_RR__multirate_conf__set_amr,
468 /* 450*/ CCD_ID_RR__multirate_conf__spare_1,
469 /* 451*/ CCD_ID_RR__multirate_conf__cod_prop,
470 /* 452*/ CCD_ID_RR__multirate_conf__spare_2,
471 /* 453*/ CCD_ID_RR__multirate_conf__spare_3,
472 /* 454*/ CCD_ID_RR__multislot_alloc__dab,
473 /* 455*/ CCD_ID_RR__multislot_alloc__uab,
474 /* 456*/ CCD_ID_RR__multislot_alloc__chan_set,
475 /* 457*/ CCD_ID_RR__nc_mode__spare_0,
476 /* 458*/ CCD_ID_RR__nc_mode__ncm,
477 /* 459*/ CCD_ID_RR__ncell__rx_lev_ncell,
478 /* 460*/ CCD_ID_RR__ncell__bcch_ncell,
479 /* 461*/ CCD_ID_RR__ncell__bsic,
480 /* 462*/ CCD_ID_RR__meas_result__ba_used,
481 /* 463*/ CCD_ID_RR__meas_result__dtx_used,
482 /* 464*/ CCD_ID_RR__meas_result__rxlev_full,
483 /* 465*/ CCD_ID_RR__meas_result__spare_0,
484 /* 466*/ CCD_ID_RR__meas_result__meas_valid,
485 /* 467*/ CCD_ID_RR__meas_result__rxlev_sub,
486 /* 468*/ CCD_ID_RR__meas_result__spare_1,
487 /* 469*/ CCD_ID_RR__meas_result__rxqual_full,
488 /* 470*/ CCD_ID_RR__meas_result__rxqual_sub,
489 /* 471*/ CCD_ID_RR__meas_result__num_ncell,
490 /* 472*/ CCD_ID_RR__meas_result__ncell,
491 /* 473*/ CCD_ID_RR__nc_meas_struct__nc_non_drx,
492 /* 474*/ CCD_ID_RR__nc_meas_struct__nc_rep_i,
493 /* 475*/ CCD_ID_RR__nc_meas_struct__nc_rep_t,
494 /* 476*/ CCD_ID_RR__nc_meas_para__nco,
495 /* 477*/ CCD_ID_RR__nc_meas_para__nc_meas_struct,
496 /* 478*/ CCD_ID_RR__nln_stat__nln_pch,
497 /* 479*/ CCD_ID_RR__nln_stat__nln_status,
498 /* 480*/ CCD_ID_RR__nt_rest_oct__nln_pch,
499 /* 481*/ CCD_ID_RR__nt_rest_oct__gr_call_info,
500 /* 482*/ CCD_ID_RR__nt_rest_oct__spare_0,
501 /* 483*/ CCD_ID_RR__opt_mcc__mcc,
502 /* 484*/ CCD_ID_RR__lsa_param__prio_thr,
503 /* 485*/ CCD_ID_RR__lsa_param__lsa_offs,
504 /* 486*/ CCD_ID_RR__lsa_param__opt_mcc,
505 /* 487*/ CCD_ID_RR__lsa_param__mnc,
506 /* 488*/ CCD_ID_RR__lsa_par_id__lsa_param,
507 /* 489*/ CCD_ID_RR__lsa_par_id__lsa_id_info,
508 /* 490*/ CCD_ID_RR__opt_sel_par__cell_bar_qual,
509 /* 491*/ CCD_ID_RR__opt_sel_par__cell_resel_offs,
510 /* 492*/ CCD_ID_RR__opt_sel_par__temp_offs,
511 /* 493*/ CCD_ID_RR__opt_sel_par__penalty_time,
512 /* 494*/ CCD_ID_RR__p0_pwr_ctrl_mode__p0,
513 /* 495*/ CCD_ID_RR__p0_pwr_ctrl_mode__pwr_ctrl_mode,
514 /* 496*/ CCD_ID_RR__p0_prmode__p0,
515 /* 497*/ CCD_ID_RR__p0_prmode__pr_mode,
516 /* 498*/ CCD_ID_RR__p0_bts_prmode__p0,
517 /* 499*/ CCD_ID_RR__p0_bts_prmode__pwr_ctrl_mode,
518 /* 500*/ CCD_ID_RR__p0_bts_prmode__pr_mode,
519 /* 501*/ CCD_ID_RR__pck_chan_desc__pck_chan_type,
520 /* 502*/ CCD_ID_RR__pck_chan_desc__tn,
521 /* 503*/ CCD_ID_RR__pck_chan_desc__tsc,
522 /* 504*/ CCD_ID_RR__pck_chan_desc__hop,
523 /* 505*/ CCD_ID_RR__pck_chan_desc__indir,
524 /* 506*/ CCD_ID_RR__pck_chan_desc__spare_0,
525 /* 507*/ CCD_ID_RR__pck_chan_desc__arfcn,
526 /* 508*/ CCD_ID_RR__pck_chan_desc__maio,
527 /* 509*/ CCD_ID_RR__pck_chan_desc__ma_num,
528 /* 510*/ CCD_ID_RR__pck_chan_desc__flag,
529 /* 511*/ CCD_ID_RR__pck_chan_desc__spare_1,
530 /* 512*/ CCD_ID_RR__pck_chan_desc__ch_mark1,
531 /* 513*/ CCD_ID_RR__pck_chan_desc__hsn,
532 /* 514*/ CCD_ID_RR__pda_egprs_par__e_window,
533 /* 515*/ CCD_ID_RR__pda_egprs_par__lqm_mode,
534 /* 516*/ CCD_ID_RR__pda_egprs_par__bep_period,
535 /* 517*/ CCD_ID_RR__page_mode__spare_0,
536 /* 518*/ CCD_ID_RR__page_mode__pm,
537 /* 519*/ CCD_ID_RR__pbcch_des__pb,
538 /* 520*/ CCD_ID_RR__pbcch_des__tsc,
539 /* 521*/ CCD_ID_RR__pbcch_des__tn,
540 /* 522*/ CCD_ID_RR__pbcch_des__flag,
541 /* 523*/ CCD_ID_RR__pbcch_des__flag2,
542 /* 524*/ CCD_ID_RR__pbcch_des__arfcn,
543 /* 525*/ CCD_ID_RR__pbcch_des__maio,
544 /* 526*/ CCD_ID_RR__pch_nch_info__pch_restruct,
545 /* 527*/ CCD_ID_RR__pch_nch_info__nln_sacch,
546 /* 528*/ CCD_ID_RR__pch_nch_info__call_prio,
547 /* 529*/ CCD_ID_RR__pch_nch_info__nln_status,
548 /* 530*/ CCD_ID_RR__pos__mod,
549 /* 531*/ CCD_ID_RR__pos__rel_pos,
550 /* 532*/ CCD_ID_RR__pos__bcch_type,
551 /* 533*/ CCD_ID_RR__poss__pos,
552 /* 534*/ CCD_ID_RR__poss__poso,
553 /* 535*/ CCD_ID_RR__itp__flag,
554 /* 536*/ CCD_ID_RR__itp__it4,
555 /* 537*/ CCD_ID_RR__itp__flag1,
556 /* 538*/ CCD_ID_RR__itp__it5,
557 /* 539*/ CCD_ID_RR__itp__it6,
558 /* 540*/ CCD_ID_RR__itp__poss,
559 /* 541*/ CCD_ID_RR__pow_cmd__spare_0,
560 /* 542*/ CCD_ID_RR__pow_cmd__pow,
561 /* 543*/ CCD_ID_RR__pow_cmd_access__atc,
562 /* 544*/ CCD_ID_RR__pow_cmd_access__spare_0,
563 /* 545*/ CCD_ID_RR__pow_cmd_access__pow,
564 /* 546*/ CCD_ID_RR__rach_ctrl__max_retrans,
565 /* 547*/ CCD_ID_RR__rach_ctrl__tx_integer,
566 /* 548*/ CCD_ID_RR__rach_ctrl__cell_bar_access,
567 /* 549*/ CCD_ID_RR__rach_ctrl__re,
568 /* 550*/ CCD_ID_RR__rach_ctrl__ac,
569 /* 551*/ CCD_ID_RR__req_ref__ra,
570 /* 552*/ CCD_ID_RR__req_ref__t1,
571 /* 553*/ CCD_ID_RR__req_ref__t3,
572 /* 554*/ CCD_ID_RR__req_ref__t2,
573 /* 555*/ CCD_ID_RR__rout_area_id__mcc,
574 /* 556*/ CCD_ID_RR__rout_area_id__mnc,
575 /* 557*/ CCD_ID_RR__rout_area_id__lac,
576 /* 558*/ CCD_ID_RR__rout_area_id__rac,
577 /* 559*/ CCD_ID_RR__sched__itp,
578 /* 560*/ CCD_ID_RR__sched__itpo,
579 /* 561*/ CCD_ID_RR__si1_rest_oct__nch_position,
580 /* 562*/ CCD_ID_RR__si1_rest_oct__band_indicator,
581 /* 563*/ CCD_ID_RR__si1_rest_oct__spare_0,
582 /* 564*/ CCD_ID_RR__meas_para__report_type,
583 /* 565*/ CCD_ID_RR__meas_para__serv_band_rep,
584 /* 566*/ CCD_ID_RR__gprs_meas_para__report_type,
585 /* 567*/ CCD_ID_RR__gprs_meas_para__reporting_rate,
586 /* 568*/ CCD_ID_RR__gprs_meas_para__inv_bsic_rep,
587 /* 569*/ CCD_ID_RR__gprs_meas_para__mr,
588 /* 570*/ CCD_ID_RR__gprs_meas_para__serv_band_rep,
589 /* 571*/ CCD_ID_RR__gprs_meas_para__scale_ord,
590 /* 572*/ CCD_ID_RR__gprs_meas_para__report_900,
591 /* 573*/ CCD_ID_RR__gprs_meas_para__report_1800,
592 /* 574*/ CCD_ID_RR__gprs_meas_para__report_400,
593 /* 575*/ CCD_ID_RR__gprs_meas_para__report_1900,
594 /* 576*/ CCD_ID_RR__gprs_meas_para__report_850,
595 /* 577*/ CCD_ID_RR__si4_rest_octets_s__lsa_param,
596 /* 578*/ CCD_ID_RR__si4_rest_octets_s__cell_ident,
597 /* 579*/ CCD_ID_RR__si4_rest_octets_s__lsa_id_info,
598 /* 580*/ CCD_ID_RR__si4_rest_octets_bs__flag,
599 /* 581*/ CCD_ID_RR__si4_rest_octets_bs__break_ind,
600 /* 582*/ CCD_ID_RR__si4_rest_octets_bs__si4_rest_octets_s,
601 /* 583*/ CCD_ID_RR__si4_rest_oct__opt_sel_par,
602 /* 584*/ CCD_ID_RR__si4_rest_oct__pow_offs,
603 /* 585*/ CCD_ID_RR__si4_rest_oct__gprs_indic,
604 /* 586*/ CCD_ID_RR__si4_rest_oct__si4_rest_octets_bs,
605 /* 587*/ CCD_ID_RR__si4_rest_oct__spare_0,
606 /* 588*/ CCD_ID_RR__si7_rest_oct__opt_sel_par,
607 /* 589*/ CCD_ID_RR__si7_rest_oct__pow_offs,
608 /* 590*/ CCD_ID_RR__si7_rest_oct__gprs_indic,
609 /* 591*/ CCD_ID_RR__si7_rest_oct__si4_rest_octets_s,
610 /* 592*/ CCD_ID_RR__si7_rest_oct__spare_0,
611 /* 593*/ CCD_ID_RR__si9_rest_oct__sched,
612 /* 594*/ CCD_ID_RR__si9_rest_oct__spare_0,
613 /* 595*/ CCD_ID_RR__si13_info__bcch_cm,
614 /* 596*/ CCD_ID_RR__si13_info__si_cf,
615 /* 597*/ CCD_ID_RR__si13_info__flag,
616 /* 598*/ CCD_ID_RR__si13_info__si13_cm,
617 /* 599*/ CCD_ID_RR__si13_info__gprs_ma,
618 /* 600*/ CCD_ID_RR__si13_info__flag1,
619 /* 601*/ CCD_ID_RR__si13_info__rac,
620 /* 602*/ CCD_ID_RR__si13_info__spgc,
621 /* 603*/ CCD_ID_RR__si13_info__prio_acc_thr,
622 /* 604*/ CCD_ID_RR__si13_info__nco,
623 /* 605*/ CCD_ID_RR__si13_info__gprs_cell_opt,
624 /* 606*/ CCD_ID_RR__si13_info__alpha,
625 /* 607*/ CCD_ID_RR__si13_info__t_avg_w,
626 /* 608*/ CCD_ID_RR__si13_info__t_avg_t,
627 /* 609*/ CCD_ID_RR__si13_info__pc_meas_chan,
628 /* 610*/ CCD_ID_RR__si13_info__n_avg_i,
629 /* 611*/ CCD_ID_RR__si13_info__psi1_period,
630 /* 612*/ CCD_ID_RR__si13_info__pbcch_des,
631 /* 613*/ CCD_ID_RR__si13_info__sgsnr,
632 /* 614*/ CCD_ID_RR__si13_rest_oct__si13_info,
633 /* 615*/ CCD_ID_RR__si13_rest_oct__spare_0,
634 /* 616*/ CCD_ID_RR__si16_rest_oct__lsa_par_id,
635 /* 617*/ CCD_ID_RR__si16_rest_oct__spare_0,
636 /* 618*/ CCD_ID_RR__single_alloc__tn,
637 /* 619*/ CCD_ID_RR__single_alloc__alpha_gamma,
638 /* 620*/ CCD_ID_RR__single_alloc__p0_pwr_ctrl_mode,
639 /* 621*/ CCD_ID_RR__start_time__t1,
640 /* 622*/ CCD_ID_RR__start_time__t3,
641 /* 623*/ CCD_ID_RR__start_time__t2,
642 /* 624*/ CCD_ID_RR__pck_meas_par__meas_start,
643 /* 625*/ CCD_ID_RR__pck_meas_par__meas_int,
644 /* 626*/ CCD_ID_RR__pck_meas_par__meas_bmp,
645 /* 627*/ CCD_ID_RR__mb_alloc__alpha,
646 /* 628*/ CCD_ID_RR__mb_alloc__gamma,
647 /* 629*/ CCD_ID_RR__mb_alloc__tbf_start_time,
648 /* 630*/ CCD_ID_RR__mb_alloc__nr_rb,
649 /* 631*/ CCD_ID_RR__mb_alloc__p0_bts_prmode,
650 /* 632*/ CCD_ID_RR__synch_ind__nci,
651 /* 633*/ CCD_ID_RR__synch_ind__rot,
652 /* 634*/ CCD_ID_RR__synch_ind__si,
653 /* 635*/ CCD_ID_RR__t_ext_ra__ext_ra,
654 /* 636*/ CCD_ID_RR__tagged_gamma__gamma,
655 /* 637*/ CCD_ID_RR__pwr_ctrl__alpha,
656 /* 638*/ CCD_ID_RR__pwr_ctrl__tagged_gamma,
657 /* 639*/ CCD_ID_RR__tagged_call_prio__call_prio,
658 /* 640*/ CCD_ID_RR__p3_rest_oct__chan_needed3_4,
659 /* 641*/ CCD_ID_RR__p3_rest_oct__nln_stat,
660 /* 642*/ CCD_ID_RR__p3_rest_oct__tagged_call_prio,
661 /* 643*/ CCD_ID_RR__p3_rest_oct__spare_0,
662 /* 644*/ CCD_ID_RR__p2_rest_oct__cn3,
663 /* 645*/ CCD_ID_RR__p2_rest_oct__nln_stat,
664 /* 646*/ CCD_ID_RR__p2_rest_oct__tagged_call_prio,
665 /* 647*/ CCD_ID_RR__p2_rest_oct__pck_page3,
666 /* 648*/ CCD_ID_RR__p2_rest_oct__spare_0,
667 /* 649*/ CCD_ID_RR__p1_rest_oct__nln_stat,
668 /* 650*/ CCD_ID_RR__p1_rest_oct__tagged_call_prio,
669 /* 651*/ CCD_ID_RR__p1_rest_oct__gr_call_info,
670 /* 652*/ CCD_ID_RR__p1_rest_oct__pck_page1,
671 /* 653*/ CCD_ID_RR__p1_rest_oct__pck_page2,
672 /* 654*/ CCD_ID_RR__p1_rest_oct__spare_0,
673 /* 655*/ CCD_ID_RR__tagged_usf_tn__usf,
674 /* 656*/ CCD_ID_RR__time_advance__spare_0,
675 /* 657*/ CCD_ID_RR__time_advance__ta,
676 /* 658*/ CCD_ID_RR__ta_idx_nm__ta_idx,
677 /* 659*/ CCD_ID_RR__ta_idx_nm__ta_nm,
678 /* 660*/ CCD_ID_RR__pck_ta__ta,
679 /* 661*/ CCD_ID_RR__pck_ta__ta_idx_nm,
680 /* 662*/ CCD_ID_RR__pck_dl_ass__mac_mode,
681 /* 663*/ CCD_ID_RR__pck_dl_ass__rlc_mode,
682 /* 664*/ CCD_ID_RR__pck_dl_ass__ts_all,
683 /* 665*/ CCD_ID_RR__pck_dl_ass__pck_ta,
684 /* 666*/ CCD_ID_RR__pck_dl_ass__pwr_ctrl,
685 /* 667*/ CCD_ID_RR__pck_dl_ass__tfi,
686 /* 668*/ CCD_ID_RR__pck_dl_ass__pck_meas_par,
687 /* 669*/ CCD_ID_RR__pck_dl_ass__spare_0,
688 /* 670*/ CCD_ID_RR__tfi_ass_alloc__tfi,
689 /* 671*/ CCD_ID_RR__tfi_ass_alloc__poll,
690 /* 672*/ CCD_ID_RR__tfi_ass_alloc__allo_flag,
691 /* 673*/ CCD_ID_RR__tfi_ass_alloc__usf,
692 /* 674*/ CCD_ID_RR__tfi_ass_alloc__usf_gran,
693 /* 675*/ CCD_ID_RR__tfi_ass_alloc__p0_prmode,
694 /* 676*/ CCD_ID_RR__tfi_ass_alloc__allo_len5,
695 /* 677*/ CCD_ID_RR__tfi_ass_alloc__allo_bmp5,
696 /* 678*/ CCD_ID_RR__tfi_ass_alloc__p0_bts_prmode,
697 /* 679*/ CCD_ID_RR__tfi_ass_alloc__ccm,
698 /* 680*/ CCD_ID_RR__tfi_ass_alloc__tlli_bcc,
699 /* 681*/ CCD_ID_RR__tfi_ass_alloc__alpha,
700 /* 682*/ CCD_ID_RR__tfi_ass_alloc__gamma,
701 /* 683*/ CCD_ID_RR__tfi_ass_alloc__ta_idx,
702 /* 684*/ CCD_ID_RR__tfi_ass_alloc__tbf_start_time,
703 /* 685*/ CCD_ID_RR__tfi_ass_rlc__tfi,
704 /* 686*/ CCD_ID_RR__tfi_ass_rlc__rlc_mode,
705 /* 687*/ CCD_ID_RR__tfi_ass_rlc__alpha,
706 /* 688*/ CCD_ID_RR__tfi_ass_rlc__gamma,
707 /* 689*/ CCD_ID_RR__tfi_ass_rlc__poll,
708 /* 690*/ CCD_ID_RR__tfi_ass_rlc__ta_valid,
709 /* 691*/ CCD_ID_RR__pck_downl_ass_ia__ded_tlli,
710 /* 692*/ CCD_ID_RR__pck_downl_ass_ia__tfi_ass_rlc,
711 /* 693*/ CCD_ID_RR__pck_downl_ass_ia__ta_idx,
712 /* 694*/ CCD_ID_RR__pck_downl_ass_ia__tbf_start_time,
713 /* 695*/ CCD_ID_RR__pck_downl_ass_ia__p0_bts_prmode,
714 /* 696*/ CCD_ID_RR__pck_downl_ass_ia__pda_egprs_par,
715 /* 697*/ CCD_ID_RR__usf_gamma__usf,
716 /* 698*/ CCD_ID_RR__usf_gamma__gamma,
717 /* 699*/ CCD_ID_RR__usf_gamma_csn1__usf_gamma,
718 /* 700*/ CCD_ID_RR__dyn_alloc__ext_dyn_all,
719 /* 701*/ CCD_ID_RR__dyn_alloc__p0,
720 /* 702*/ CCD_ID_RR__dyn_alloc__usf_gran,
721 /* 703*/ CCD_ID_RR__dyn_alloc__tfi,
722 /* 704*/ CCD_ID_RR__dyn_alloc__rlc_blks,
723 /* 705*/ CCD_ID_RR__dyn_alloc__flag_pp,
724 /* 706*/ CCD_ID_RR__dyn_alloc__tagged_usf_tn,
725 /* 707*/ CCD_ID_RR__dyn_alloc__alpha,
726 /* 708*/ CCD_ID_RR__dyn_alloc__usf_gamma_csn1,
727 /* 709*/ CCD_ID_RR__utran_freq_list__length,
728 /* 710*/ CCD_ID_RR__utran_freq_list__fdd_arfcn,
729 /* 711*/ CCD_ID_RR__utran_freq_list__tdd_arfcn,
730 /* 712*/ CCD_ID_RR__utran_freq_list__spare_0,
731 /* 713*/ CCD_ID_RR__vbs_vgcs_opt__inband_not,
732 /* 714*/ CCD_ID_RR__vbs_vgcs_opt__inband_pag,
733 /* 715*/ CCD_ID_RR__vgcs_tmi__tm,
734 /* 716*/ CCD_ID_RR__vgcs_tmi__group_ckn,
735 /* 717*/ CCD_ID_RR__vgcs_tmi__spare_0,
736 /* 718*/ CCD_ID_RR__fa_blk_ia__blp,
737 /* 719*/ CCD_ID_RR__fa_blk_ia__allo_len7,
738 /* 720*/ CCD_ID_RR__fa_blk_ia__allo_bmp7,
739 /* 721*/ CCD_ID_RR__fix_alloc__tfi,
740 /* 722*/ CCD_ID_RR__fix_alloc__final,
741 /* 723*/ CCD_ID_RR__fix_alloc__dl_ctrl_tn,
742 /* 724*/ CCD_ID_RR__fix_alloc__p0_pwr_ctrl_mode,
743 /* 725*/ CCD_ID_RR__fix_alloc__flag,
744 /* 726*/ CCD_ID_RR__fix_alloc__ts_all,
745 /* 727*/ CCD_ID_RR__fix_alloc__pwr_ctrl,
746 /* 728*/ CCD_ID_RR__fix_alloc__hdm,
747 /* 729*/ CCD_ID_RR__fix_alloc__spare_0,
748 /* 730*/ CCD_ID_RR__fix_alloc__flag1,
749 /* 731*/ CCD_ID_RR__fix_alloc__fa_blk_ia,
750 /* 732*/ CCD_ID_RR__fix_alloc__allo_var,
751 /* 733*/ CCD_ID_RR__pck_ul_ass__ccm,
752 /* 734*/ CCD_ID_RR__pck_ul_ass__tlli_bcc,
753 /* 735*/ CCD_ID_RR__pck_ul_ass__pck_ta,
754 /* 736*/ CCD_ID_RR__pck_ul_ass__flag,
755 /* 737*/ CCD_ID_RR__pck_ul_ass__flag1,
756 /* 738*/ CCD_ID_RR__pck_ul_ass__dyn_alloc,
757 /* 739*/ CCD_ID_RR__pck_ul_ass__single_alloc,
758 /* 740*/ CCD_ID_RR__pck_ul_ass__fix_alloc,
759 /* 741*/ CCD_ID_RR__pck_ul_ass__spare_0,
760 /* 742*/ CCD_ID_RR__sngl_block_alloc__alpha,
761 /* 743*/ CCD_ID_RR__sngl_block_alloc__gamma,
762 /* 744*/ CCD_ID_RR__sngl_block_alloc__spare_0,
763 /* 745*/ CCD_ID_RR__sngl_block_alloc__tbf_start_time,
764 /* 746*/ CCD_ID_RR__sngl_block_alloc__p0_bts_prmode,
765 /* 747*/ CCD_ID_RR__pck_upl_ass_ia__flag,
766 /* 748*/ CCD_ID_RR__pck_upl_ass_ia__tfi_ass_alloc,
767 /* 749*/ CCD_ID_RR__pck_upl_ass_ia__sngl_block_alloc,
768 /* 750*/ CCD_ID_RR__pck_upl_ass_ia__t_ext_ra,
769 /* 751*/ CCD_ID_RR__ia_assign_par__flag,
770 /* 752*/ CCD_ID_RR__ia_assign_par__flag1,
771 /* 753*/ CCD_ID_RR__ia_assign_par__pck_upl_ass_ia,
772 /* 754*/ CCD_ID_RR__ia_assign_par__pck_downl_ass_ia,
773 /* 755*/ CCD_ID_RR__ia_assign_par__ia_2nd_part,
774 /* 756*/ CCD_ID_RR__class_enq_mask__class_req,
775 /* 757*/ CCD_ID_RR__class_enq_mask__utran_class_req,
776 /* 758*/ CCD_ID_RR__class_enq_mask__cdma_class_req,
777 /* 759*/ CCD_ID_RR__class_enq_mask__spare_0,
778 /* 760*/ CCD_ID_RR__si2q_extn_info__ccn_support_description,
779 /* 761*/ CCD_ID_RR__si2q_extn_bits__ext_length,
780 /* 762*/ CCD_ID_RR__si2q_extn_bits__si2q_extn_info,
781 /* 763*/ CCD_ID_RR__si_2qua_octets__ba_ind,
782 /* 764*/ CCD_ID_RR__si_2qua_octets__threeg_ba_ind,
783 /* 765*/ CCD_ID_RR__si_2qua_octets__mp_change_mark,
784 /* 766*/ CCD_ID_RR__si_2qua_octets__si2qua_index,
785 /* 767*/ CCD_ID_RR__si_2qua_octets__si2qua_count,
786 /* 768*/ CCD_ID_RR__si_2qua_octets__meas_para,
787 /* 769*/ CCD_ID_RR__si_2qua_octets__rtdd,
788 /* 770*/ CCD_ID_RR__si_2qua_octets__gprs_bsic,
789 /* 771*/ CCD_ID_RR__si_2qua_octets__gprs_rep_prio,
790 /* 772*/ CCD_ID_RR__si_2qua_octets__gprs_meas_para,
791 /* 773*/ CCD_ID_RR__si_2qua_octets__nc_meas_para,
792 /* 774*/ CCD_ID_RR__si_2qua_octets__si2q_extn_bits,
793 /* 775*/ CCD_ID_RR__si2quater_ind__si2quater_pos,
794 /* 776*/ CCD_ID_RR__si3_rest_oct__opt_sel_par,
795 /* 777*/ CCD_ID_RR__si3_rest_oct__pow_offs,
796 /* 778*/ CCD_ID_RR__si3_rest_oct__si2ter_ind,
797 /* 779*/ CCD_ID_RR__si3_rest_oct__es_ind_tag,
798 /* 780*/ CCD_ID_RR__si3_rest_oct__if_and_where,
799 /* 781*/ CCD_ID_RR__si3_rest_oct__gprs_indic,
800 /* 782*/ CCD_ID_RR__si3_rest_oct__threeg_es_tag_ind,
801 /* 783*/ CCD_ID_RR__si3_rest_oct__si2quater_ind,
802 /* 784*/ CCD_ID_RR__si3_rest_oct__spare_0,
803 /* 785*/ CCD_ID_RR__d_alloc__usf,
804 /* 786*/ CCD_ID_RR__d_alloc__usf_gran,
805 /* 787*/ CCD_ID_RR__d_alloc__p0_prmode,
806 /* 788*/ CCD_ID_RR__f_alloc__allo_len5,
807 /* 789*/ CCD_ID_RR__f_alloc__allo_bmp5,
808 /* 790*/ CCD_ID_RR__f_alloc__p0_bts_prmode,
809 /* 791*/ CCD_ID_RR__d_f_alloc__tfi,
810 /* 792*/ CCD_ID_RR__d_f_alloc__poll,
811 /* 793*/ CCD_ID_RR__d_f_alloc__allo_flag,
812 /* 794*/ CCD_ID_RR__d_f_alloc__d_alloc,
813 /* 795*/ CCD_ID_RR__d_f_alloc__f_alloc,
814 /* 796*/ CCD_ID_RR__d_f_alloc__mcs,
815 /* 797*/ CCD_ID_RR__d_f_alloc__tlli_bcc,
816 /* 798*/ CCD_ID_RR__d_f_alloc__bep_period,
817 /* 799*/ CCD_ID_RR__d_f_alloc__resegm,
818 /* 800*/ CCD_ID_RR__d_f_alloc__e_window,
819 /* 801*/ CCD_ID_RR__d_f_alloc__alpha,
820 /* 802*/ CCD_ID_RR__d_f_alloc__gamma,
821 /* 803*/ CCD_ID_RR__d_f_alloc__ta_idx,
822 /* 804*/ CCD_ID_RR__d_f_alloc__tbf_start_time,
823 /* 805*/ CCD_ID_RR__egprs_pua__ext_ra,
824 /* 806*/ CCD_ID_RR__egprs_pua__acc_tt,
825 /* 807*/ CCD_ID_RR__egprs_pua__flag,
826 /* 808*/ CCD_ID_RR__egprs_pua__d_f_alloc,
827 /* 809*/ CCD_ID_RR__egprs_pua__mb_alloc,
828 /* 810*/ CCD_ID_RR__ia_egprs_par__flag,
829 /* 811*/ CCD_ID_RR__ia_egprs_par__flag1,
830 /* 812*/ CCD_ID_RR__ia_egprs_par__egprs_pua,
831 /* 813*/ CCD_ID_RR__ia_rest_oct__flag_2bit,
832 /* 814*/ CCD_ID_RR__ia_rest_oct__ia_egprs_par,
833 /* 815*/ CCD_ID_RR__ia_rest_oct__ia_freq_par,
834 /* 816*/ CCD_ID_RR__ia_rest_oct__ia_assign_par,
835 /* 817*/ CCD_ID_RR__ia_rest_oct__spare_0,
836 /* 818*/ CCD_ID_RR__si6_rest_oct_dtm__rac,
837 /* 819*/ CCD_ID_RR__si6_rest_oct_dtm__max_lapdm,
838 /* 820*/ CCD_ID_RR__si6_rest_oct__pch_nch_info,
839 /* 821*/ CCD_ID_RR__si6_rest_oct__vbs_vgcs_opt,
840 /* 822*/ CCD_ID_RR__si6_rest_oct__si6_rest_oct_dtm,
841 /* 823*/ CCD_ID_RR__si6_rest_oct__band_indicator,
842 /* 824*/ CCD_ID_RR__si6_rest_oct__spare_0,
843 /* 825*/ CCD_ID_RR__B_APPLIC_INFO__msg_type,
844 /* 826*/ CCD_ID_RR__B_APPLIC_INFO__apdu_id,
845 /* 827*/ CCD_ID_RR__B_APPLIC_INFO__apdu_flags,
846 /* 828*/ CCD_ID_RR__B_APPLIC_INFO__apdu_data,
847 /* 829*/ CCD_ID_RR__D_ADD_ASSIGN__msg_type,
848 /* 830*/ CCD_ID_RR__D_ADD_ASSIGN__chan_desc,
849 /* 831*/ CCD_ID_RR__D_ADD_ASSIGN__mob_alloc,
850 /* 832*/ CCD_ID_RR__D_ADD_ASSIGN__start_time,
851 /* 833*/ CCD_ID_RR__D_ASSIGN_CMD__msg_type,
852 /* 834*/ CCD_ID_RR__D_ASSIGN_CMD__chan_desc,
853 /* 835*/ CCD_ID_RR__D_ASSIGN_CMD__pow_cmd,
854 /* 836*/ CCD_ID_RR__D_ASSIGN_CMD__freq_list_after,
855 /* 837*/ CCD_ID_RR__D_ASSIGN_CMD__cell_chan_desc,
856 /* 838*/ CCD_ID_RR__D_ASSIGN_CMD__multislot_alloc,
857 /* 839*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode,
858 /* 840*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode2,
859 /* 841*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode3,
860 /* 842*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode4,
861 /* 843*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode5,
862 /* 844*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode6,
863 /* 845*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode7,
864 /* 846*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode8,
865 /* 847*/ CCD_ID_RR__D_ASSIGN_CMD__chan_desc_after_2,
866 /* 848*/ CCD_ID_RR__D_ASSIGN_CMD__chan_mode_2,
867 /* 849*/ CCD_ID_RR__D_ASSIGN_CMD__mob_alloc_after,
868 /* 850*/ CCD_ID_RR__D_ASSIGN_CMD__start_time,
869 /* 851*/ CCD_ID_RR__D_ASSIGN_CMD__freq_list_before,
870 /* 852*/ CCD_ID_RR__D_ASSIGN_CMD__chan_desc_before,
871 /* 853*/ CCD_ID_RR__D_ASSIGN_CMD__chan_desc_before_2,
872 /* 854*/ CCD_ID_RR__D_ASSIGN_CMD__freq_chan_seq,
873 /* 855*/ CCD_ID_RR__D_ASSIGN_CMD__mob_alloc_before,
874 /* 856*/ CCD_ID_RR__D_ASSIGN_CMD__ciph_mode_set,
875 /* 857*/ CCD_ID_RR__D_ASSIGN_CMD__vgcs_tmi,
876 /* 858*/ CCD_ID_RR__D_ASSIGN_CMD__multirate_conf,
877 /* 859*/ CCD_ID_RR__U_ASSIGN_COMP__msg_type,
878 /* 860*/ CCD_ID_RR__U_ASSIGN_COMP__rr_cause,
879 /* 861*/ CCD_ID_RR__U_ASSIGN_FAIL__msg_type,
880 /* 862*/ CCD_ID_RR__U_ASSIGN_FAIL__rr_cause,
881 /* 863*/ CCD_ID_RR__D_CHAN_MOD__msg_type,
882 /* 864*/ CCD_ID_RR__D_CHAN_MOD__chan_desc,
883 /* 865*/ CCD_ID_RR__D_CHAN_MOD__chan_mode,
884 /* 866*/ CCD_ID_RR__D_CHAN_MOD__vgcs_tmi,
885 /* 867*/ CCD_ID_RR__D_CHAN_MOD__multirate_conf,
886 /* 868*/ CCD_ID_RR__U_CHAN_MOD_ACK__msg_type,
887 /* 869*/ CCD_ID_RR__U_CHAN_MOD_ACK__chan_desc,
888 /* 870*/ CCD_ID_RR__U_CHAN_MOD_ACK__chan_mode,
889 /* 871*/ CCD_ID_RR__D_CHAN_REL__msg_type,
890 /* 872*/ CCD_ID_RR__D_CHAN_REL__rr_cause,
891 /* 873*/ CCD_ID_RR__D_CHAN_REL__ba_range,
892 /* 874*/ CCD_ID_RR__D_CHAN_REL__group_chan_desc,
893 /* 875*/ CCD_ID_RR__D_CHAN_REL__group_ckn,
894 /* 876*/ CCD_ID_RR__D_CHAN_REL__gprs_resum,
895 /* 877*/ CCD_ID_RR__D_CHAN_REL__ba_list_pref,
896 /* 878*/ CCD_ID_RR__D_CHAN_REL__utran_freq_list,
897 /* 879*/ CCD_ID_RR__D_CHAN_REL__cell_chan_desc,
898 /* 880*/ CCD_ID_RR__D_CIPH_CMD__msg_type,
899 /* 881*/ CCD_ID_RR__D_CIPH_CMD__ciph_mode_set,
900 /* 882*/ CCD_ID_RR__D_CIPH_CMD__ciph_res,
901 /* 883*/ CCD_ID_RR__U_CIPH_COMP__msg_type,
902 /* 884*/ CCD_ID_RR__U_CIPH_COMP__mob_ident,
903 /* 885*/ CCD_ID_RR__U_CLASS_CHNG__msg_type,
904 /* 886*/ CCD_ID_RR__U_CLASS_CHNG__mob_class_2,
905 /* 887*/ CCD_ID_RR__U_CLASS_CHNG__mob_class_3,
906 /* 888*/ CCD_ID_RR__D_CLASS_ENQ__msg_type,
907 /* 889*/ CCD_ID_RR__D_CLASS_ENQ__class_enq_mask,
908 /* 890*/ CCD_ID_RR__D_CONF_CHANGE_CMD__msg_type,
909 /* 891*/ CCD_ID_RR__D_CONF_CHANGE_CMD__multislot_alloc,
910 /* 892*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode,
911 /* 893*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode2,
912 /* 894*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode3,
913 /* 895*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode4,
914 /* 896*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode5,
915 /* 897*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode6,
916 /* 898*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode7,
917 /* 899*/ CCD_ID_RR__D_CONF_CHANGE_CMD__chan_mode8,
918 /* 900*/ CCD_ID_RR__D_CONF_CHANGE_ACK__msg_type,
919 /* 901*/ CCD_ID_RR__D_CONFIG_CHANGE_REJ__msg_type,
920 /* 902*/ CCD_ID_RR__D_CONFIG_CHANGE_REJ__rr_cause,
921 /* 903*/ CCD_ID_RR__D_EXT_MEAS_ORDER__msg_type,
922 /* 904*/ CCD_ID_RR__D_EXT_MEAS_ORDER__ext_meas_freq,
923 /* 905*/ CCD_ID_RR__U_EXT_MEAS_REPORT__msg_type,
924 /* 906*/ CCD_ID_RR__U_EXT_MEAS_REPORT__ext_meas_res,
925 /* 907*/ CCD_ID_RR__D_FREQ_REDEF__msg_type,
926 /* 908*/ CCD_ID_RR__D_FREQ_REDEF__chan_desc,
927 /* 909*/ CCD_ID_RR__D_FREQ_REDEF__mob_alloc,
928 /* 910*/ CCD_ID_RR__D_FREQ_REDEF__start_time,
929 /* 911*/ CCD_ID_RR__D_FREQ_REDEF__cell_chan_desc,
930 /* 912*/ CCD_ID_RR__U_GPRS_SUSP_REQ__msg_type,
931 /* 913*/ CCD_ID_RR__U_GPRS_SUSP_REQ__ded_tlli,
932 /* 914*/ CCD_ID_RR__U_GPRS_SUSP_REQ__rout_area_id,
933 /* 915*/ CCD_ID_RR__U_GPRS_SUSP_REQ__susp_cause,
934 /* 916*/ CCD_ID_RR__D_HANDOV_CMD__msg_type,
935 /* 917*/ CCD_ID_RR__D_HANDOV_CMD__cell_desc,
936 /* 918*/ CCD_ID_RR__D_HANDOV_CMD__chan_desc_after,
937 /* 919*/ CCD_ID_RR__D_HANDOV_CMD__handov_ref,
938 /* 920*/ CCD_ID_RR__D_HANDOV_CMD__pow_cmd_access,
939 /* 921*/ CCD_ID_RR__D_HANDOV_CMD__synch_ind,
940 /* 922*/ CCD_ID_RR__D_HANDOV_CMD__freq_short_list_after,
941 /* 923*/ CCD_ID_RR__D_HANDOV_CMD__freq_list_after,
942 /* 924*/ CCD_ID_RR__D_HANDOV_CMD__cell_chan_desc,
943 /* 925*/ CCD_ID_RR__D_HANDOV_CMD__multislot_alloc,
944 /* 926*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode,
945 /* 927*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode2,
946 /* 928*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode3,
947 /* 929*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode4,
948 /* 930*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode5,
949 /* 931*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode6,
950 /* 932*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode7,
951 /* 933*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode8,
952 /* 934*/ CCD_ID_RR__D_HANDOV_CMD__chan_desc_after_2,
953 /* 935*/ CCD_ID_RR__D_HANDOV_CMD__chan_mode_2,
954 /* 936*/ CCD_ID_RR__D_HANDOV_CMD__freq_chan_seq_after,
955 /* 937*/ CCD_ID_RR__D_HANDOV_CMD__mob_alloc_after,
956 /* 938*/ CCD_ID_RR__D_HANDOV_CMD__start_time,
957 /* 939*/ CCD_ID_RR__D_HANDOV_CMD__time_diff,
958 /* 940*/ CCD_ID_RR__D_HANDOV_CMD__time_advance,
959 /* 941*/ CCD_ID_RR__D_HANDOV_CMD__freq_short_list_before,
960 /* 942*/ CCD_ID_RR__D_HANDOV_CMD__freq_list_before,
961 /* 943*/ CCD_ID_RR__D_HANDOV_CMD__chan_desc_before,
962 /* 944*/ CCD_ID_RR__D_HANDOV_CMD__chan_desc_before_2,
963 /* 945*/ CCD_ID_RR__D_HANDOV_CMD__freq_chan_seq_before,
964 /* 946*/ CCD_ID_RR__D_HANDOV_CMD__mob_alloc_before,
965 /* 947*/ CCD_ID_RR__D_HANDOV_CMD__ciph_mode_set,
966 /* 948*/ CCD_ID_RR__D_HANDOV_CMD__vgcs_tmi,
967 /* 949*/ CCD_ID_RR__D_HANDOV_CMD__multirate_conf,
968 /* 950*/ CCD_ID_RR__U_HANDOV_COMP__msg_type,
969 /* 951*/ CCD_ID_RR__U_HANDOV_COMP__rr_cause,
970 /* 952*/ CCD_ID_RR__U_HANDOV_COMP__mob_time_diff,
971 /* 953*/ CCD_ID_RR__U_HANDOV_FAIL__msg_type,
972 /* 954*/ CCD_ID_RR__U_HANDOV_FAIL__rr_cause,
973 /* 955*/ CCD_ID_RR__D_IMM_ASSIGN__msg_type,
974 /* 956*/ CCD_ID_RR__D_IMM_ASSIGN__spare_0,
975 /* 957*/ CCD_ID_RR__D_IMM_ASSIGN__tma,
976 /* 958*/ CCD_ID_RR__D_IMM_ASSIGN__dl,
977 /* 959*/ CCD_ID_RR__D_IMM_ASSIGN__d_t,
978 /* 960*/ CCD_ID_RR__D_IMM_ASSIGN__page_mode,
979 /* 961*/ CCD_ID_RR__D_IMM_ASSIGN__chan_desc,
980 /* 962*/ CCD_ID_RR__D_IMM_ASSIGN__pck_chan_desc,
981 /* 963*/ CCD_ID_RR__D_IMM_ASSIGN__req_ref,
982 /* 964*/ CCD_ID_RR__D_IMM_ASSIGN__time_advance,
983 /* 965*/ CCD_ID_RR__D_IMM_ASSIGN__mob_alloc,
984 /* 966*/ CCD_ID_RR__D_IMM_ASSIGN__start_time,
985 /* 967*/ CCD_ID_RR__D_IMM_ASSIGN__ia_rest_oct,
986 /* 968*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__msg_type,
987 /* 969*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__page_mode,
988 /* 970*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__spare_0,
989 /* 971*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__chan_desc,
990 /* 972*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__req_ref,
991 /* 973*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__time_advance,
992 /* 974*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__chan_desc_2,
993 /* 975*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__req_ref_2,
994 /* 976*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__time_advance_2,
995 /* 977*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__mob_alloc,
996 /* 978*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__start_time,
997 /* 979*/ CCD_ID_RR__D_IMM_ASSIGN_EXT__spare_1,
998 /* 980*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__msg_type,
999 /* 981*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__page_mode,
1000 /* 982*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__spare_0,
1001 /* 983*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__req_ref,
1002 /* 984*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__t3122,
1003 /* 985*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__req_ref_2,
1004 /* 986*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__t3122_2,
1005 /* 987*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__req_ref_3,
1006 /* 988*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__t3122_3,
1007 /* 989*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__req_ref_4,
1008 /* 990*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__t3122_4,
1009 /* 991*/ CCD_ID_RR__D_IMM_ASSIGN_REJ__iar_rest_oct,
1010 /* 992*/ CCD_ID_RR__U_MEAS_REP__msg_type,
1011 /* 993*/ CCD_ID_RR__U_MEAS_REP__meas_result,
1012 /* 994*/ CCD_ID_RR__D_NOTIFY_NCH__msg_type,
1013 /* 995*/ CCD_ID_RR__D_NOTIFY_NCH__nt_rest_oct,
1014 /* 996*/ CCD_ID_RR__D_PAG_REQ_1__msg_type,
1015 /* 997*/ CCD_ID_RR__D_PAG_REQ_1__page_mode,
1016 /* 998*/ CCD_ID_RR__D_PAG_REQ_1__chan_needed,
1017 /* 999*/ CCD_ID_RR__D_PAG_REQ_1__mob_ident,
1018 /* 1000*/ CCD_ID_RR__D_PAG_REQ_1__mob_ident_2,
1019 /* 1001*/ CCD_ID_RR__D_PAG_REQ_1__p1_rest_oct,
1020 /* 1002*/ CCD_ID_RR__D_PAG_REQ_2__msg_type,
1021 /* 1003*/ CCD_ID_RR__D_PAG_REQ_2__page_mode,
1022 /* 1004*/ CCD_ID_RR__D_PAG_REQ_2__chan_needed,
1023 /* 1005*/ CCD_ID_RR__D_PAG_REQ_2__tmsi_1,
1024 /* 1006*/ CCD_ID_RR__D_PAG_REQ_2__tmsi_2,
1025 /* 1007*/ CCD_ID_RR__D_PAG_REQ_2__mob_ident,
1026 /* 1008*/ CCD_ID_RR__D_PAG_REQ_2__p2_rest_oct,
1027 /* 1009*/ CCD_ID_RR__D_PAG_REQ_3__msg_type,
1028 /* 1010*/ CCD_ID_RR__D_PAG_REQ_3__page_mode,
1029 /* 1011*/ CCD_ID_RR__D_PAG_REQ_3__chan_needed,
1030 /* 1012*/ CCD_ID_RR__D_PAG_REQ_3__tmsi_1,
1031 /* 1013*/ CCD_ID_RR__D_PAG_REQ_3__tmsi_2,
1032 /* 1014*/ CCD_ID_RR__D_PAG_REQ_3__tmsi_3,
1033 /* 1015*/ CCD_ID_RR__D_PAG_REQ_3__tmsi_4,
1034 /* 1016*/ CCD_ID_RR__D_PAG_REQ_3__p3_rest_oct,
1035 /* 1017*/ CCD_ID_RR__U_PAG_RES__msg_type,
1036 /* 1018*/ CCD_ID_RR__U_PAG_RES__ciph_key_num,
1037 /* 1019*/ CCD_ID_RR__U_PAG_RES__spare_0,
1038 /* 1020*/ CCD_ID_RR__U_PAG_RES__mob_class_2,
1039 /* 1021*/ CCD_ID_RR__U_PAG_RES__mob_ident,
1040 /* 1022*/ CCD_ID_RR__D_PART_REL__msg_type,
1041 /* 1023*/ CCD_ID_RR__D_PART_REL__chan_desc,
1042 /* 1024*/ CCD_ID_RR__U_PART_REL_COMP__msg_type,
1043 /* 1025*/ CCD_ID_RR__D_PDCH_ASS_CMD__msg_type,
1044 /* 1026*/ CCD_ID_RR__D_PDCH_ASS_CMD__chan_desc,
1045 /* 1027*/ CCD_ID_RR__D_PDCH_ASS_CMD__cell_chan_desc,
1046 /* 1028*/ CCD_ID_RR__D_PDCH_ASS_CMD__freq_list_after,
1047 /* 1029*/ CCD_ID_RR__D_PDCH_ASS_CMD__mob_alloc_after,
1048 /* 1030*/ CCD_ID_RR__D_PDCH_ASS_CMD__start_time,
1049 /* 1031*/ CCD_ID_RR__D_PDCH_ASS_CMD__freq_list_before,
1050 /* 1032*/ CCD_ID_RR__D_PDCH_ASS_CMD__chan_desc_before,
1051 /* 1033*/ CCD_ID_RR__D_PDCH_ASS_CMD__freq_chan_seq,
1052 /* 1034*/ CCD_ID_RR__D_PDCH_ASS_CMD__mob_alloc_before,
1053 /* 1035*/ CCD_ID_RR__D_PDCH_ASS_CMD__pck_ul_ass,
1054 /* 1036*/ CCD_ID_RR__D_PDCH_ASS_CMD__pck_dl_ass,
1055 /* 1037*/ CCD_ID_RR__D_PHYS_INFO__msg_type,
1056 /* 1038*/ CCD_ID_RR__D_PHYS_INFO__time_advance,
1057 /* 1039*/ CCD_ID_RR__D_CHANGE_ORDER__msg_type,
1058 /* 1040*/ CCD_ID_RR__D_CHANGE_ORDER__cell_desc,
1059 /* 1041*/ CCD_ID_RR__D_CHANGE_ORDER__nc_mode,
1060 /* 1042*/ CCD_ID_RR__D_RR_INIT_REQ__msg_type,
1061 /* 1043*/ CCD_ID_RR__D_RR_INIT_REQ__ciph_key_num,
1062 /* 1044*/ CCD_ID_RR__D_RR_INIT_REQ__chan_coding,
1063 /* 1045*/ CCD_ID_RR__D_RR_INIT_REQ__mob_class_2,
1064 /* 1046*/ CCD_ID_RR__D_RR_INIT_REQ__ded_tlli,
1065 /* 1047*/ CCD_ID_RR__D_RR_INIT_REQ__chan_req_desc,
1066 /* 1048*/ CCD_ID_RR__D_RR_INIT_REQ__gprs_meas_res,
1067 /* 1049*/ CCD_ID_RR__B_RR_STATUS__msg_type,
1068 /* 1050*/ CCD_ID_RR__B_RR_STATUS__rr_cause,
1069 /* 1051*/ CCD_ID_RR__D_SYS_INFO_1__msg_type,
1070 /* 1052*/ CCD_ID_RR__D_SYS_INFO_1__cell_chan_desc,
1071 /* 1053*/ CCD_ID_RR__D_SYS_INFO_1__rach_ctrl,
1072 /* 1054*/ CCD_ID_RR__D_SYS_INFO_1__si1_rest_oct,
1073 /* 1055*/ CCD_ID_RR__D_SYS_INFO_2__msg_type,
1074 /* 1056*/ CCD_ID_RR__D_SYS_INFO_2__neigh_cell_desc,
1075 /* 1057*/ CCD_ID_RR__D_SYS_INFO_2__ncc_permit,
1076 /* 1058*/ CCD_ID_RR__D_SYS_INFO_2__rach_ctrl,
1077 /* 1059*/ CCD_ID_RR__D_SYS_INFO_2BIS__msg_type,
1078 /* 1060*/ CCD_ID_RR__D_SYS_INFO_2BIS__neigh_cell_desc,
1079 /* 1061*/ CCD_ID_RR__D_SYS_INFO_2BIS__rach_ctrl,
1080 /* 1062*/ CCD_ID_RR__D_SYS_INFO_2BIS__spare_0,
1081 /* 1063*/ CCD_ID_RR__D_SYS_INFO_2QUATER__msg_type,
1082 /* 1064*/ CCD_ID_RR__D_SYS_INFO_2QUATER__si_2qua_octets,
1083 /* 1065*/ CCD_ID_RR__D_SYS_INFO_2TER__msg_type,
1084 /* 1066*/ CCD_ID_RR__D_SYS_INFO_2TER__neigh_cell_desc,
1085 /* 1067*/ CCD_ID_RR__D_SYS_INFO_2TER__spare_0,
1086 /* 1068*/ CCD_ID_RR__D_SYS_INFO_3__msg_type,
1087 /* 1069*/ CCD_ID_RR__D_SYS_INFO_3__cell_ident,
1088 /* 1070*/ CCD_ID_RR__D_SYS_INFO_3__loc_area_ident,
1089 /* 1071*/ CCD_ID_RR__D_SYS_INFO_3__ctrl_chan_desc,
1090 /* 1072*/ CCD_ID_RR__D_SYS_INFO_3__cell_opt_bcch,
1091 /* 1073*/ CCD_ID_RR__D_SYS_INFO_3__cell_select,
1092 /* 1074*/ CCD_ID_RR__D_SYS_INFO_3__rach_ctrl,
1093 /* 1075*/ CCD_ID_RR__D_SYS_INFO_3__si3_rest_oct,
1094 /* 1076*/ CCD_ID_RR__D_SYS_INFO_4__msg_type,
1095 /* 1077*/ CCD_ID_RR__D_SYS_INFO_4__loc_area_ident,
1096 /* 1078*/ CCD_ID_RR__D_SYS_INFO_4__cell_select,
1097 /* 1079*/ CCD_ID_RR__D_SYS_INFO_4__rach_ctrl,
1098 /* 1080*/ CCD_ID_RR__D_SYS_INFO_4__chan_desc,
1099 /* 1081*/ CCD_ID_RR__D_SYS_INFO_4__mob_alloc,
1100 /* 1082*/ CCD_ID_RR__D_SYS_INFO_4__si4_rest_oct,
1101 /* 1083*/ CCD_ID_RR__D_SYS_INFO_4__spare_0,
1102 /* 1084*/ CCD_ID_RR__D_SYS_INFO_5__msg_type,
1103 /* 1085*/ CCD_ID_RR__D_SYS_INFO_5__neigh_cell_desc,
1104 /* 1086*/ CCD_ID_RR__D_SYS_INFO_5BIS__msg_type,
1105 /* 1087*/ CCD_ID_RR__D_SYS_INFO_5BIS__neigh_cell_desc,
1106 /* 1088*/ CCD_ID_RR__D_SYS_INFO_5TER__msg_type,
1107 /* 1089*/ CCD_ID_RR__D_SYS_INFO_5TER__neigh_cell_desc,
1108 /* 1090*/ CCD_ID_RR__D_SYS_INFO_6__msg_type,
1109 /* 1091*/ CCD_ID_RR__D_SYS_INFO_6__cell_ident,
1110 /* 1092*/ CCD_ID_RR__D_SYS_INFO_6__loc_area_ident,
1111 /* 1093*/ CCD_ID_RR__D_SYS_INFO_6__cell_opt_sacch,
1112 /* 1094*/ CCD_ID_RR__D_SYS_INFO_6__ncc_permit,
1113 /* 1095*/ CCD_ID_RR__D_SYS_INFO_6__si6_rest_oct,
1114 /* 1096*/ CCD_ID_RR__D_SYS_INFO_7__msg_type,
1115 /* 1097*/ CCD_ID_RR__D_SYS_INFO_7__si7_rest_oct,
1116 /* 1098*/ CCD_ID_RR__D_SYS_INFO_8__msg_type,
1117 /* 1099*/ CCD_ID_RR__D_SYS_INFO_8__si8_rest_oct,
1118 /* 1100*/ CCD_ID_RR__D_SYS_INFO_9__msg_type,
1119 /* 1101*/ CCD_ID_RR__D_SYS_INFO_9__rach_ctrl,
1120 /* 1102*/ CCD_ID_RR__D_SYS_INFO_9__si9_rest_oct,
1121 /* 1103*/ CCD_ID_RR__D_SYS_INFO_13__msg_type,
1122 /* 1104*/ CCD_ID_RR__D_SYS_INFO_13__si13_rest_oct,
1123 /* 1105*/ CCD_ID_RR__D_SYS_INFO_16__msg_type,
1124 /* 1106*/ CCD_ID_RR__D_SYS_INFO_16__si16_rest_oct,
1125 /* 1107*/ CCD_ID_RR__D_SYS_INFO_17__msg_type,
1126 /* 1108*/ CCD_ID_RR__D_SYS_INFO_17__si17_rest_oct,
1127 /* 1109*/ CCD_ID_RR__TALKER_IND__msg_type,
1128 /* 1110*/ CCD_ID_RR__TALKER_IND__mob_class_2,
1129 /* 1111*/ CCD_ID_RR__TALKER_IND__mob_ident,
1130 /* 1112*/ CCD_ID_RR__D_UPLINK_BUSY__msg_type,
1131 /* 1113*/ CCD_ID_RR__B_UPLINK_REL__msg_type,
1132 /* 1114*/ CCD_ID_RR__B_UPLINK_REL__rr_cause,
1133 /* 1115*/ CCD_ID_RR__D_VGCS_UPLINK_GRANT__msg_type,
1134 /* 1116*/ CCD_ID_RR__D_VGCS_UPLINK_GRANT__req_ref,
1135 /* 1117*/ CCD_ID_RR__D_VGCS_UPLINK_GRANT__time_advance,
1136 /* 1118*/ CCD_ID_RR_SHORT__emp__mr,
1137 /* 1119*/ CCD_ID_RR_SHORT__emp__serv_band_rep,
1138 /* 1120*/ CCD_ID_RR_SHORT__emp__scale_ord,
1139 /* 1121*/ CCD_ID_RR_SHORT__emp__report_900,
1140 /* 1122*/ CCD_ID_RR_SHORT__emp__report_1800,
1141 /* 1123*/ CCD_ID_RR_SHORT__emp__report_400,
1142 /* 1124*/ CCD_ID_RR_SHORT__emp__report_1900,
1143 /* 1125*/ CCD_ID_RR_SHORT__emp__report_850,
1144 /* 1126*/ CCD_ID_RR_SHORT__i_bsic_i__ba_start_bsic,
1145 /* 1127*/ CCD_ID_RR_SHORT__i_bsic_i__bsic,
1146 /* 1128*/ CCD_ID_RR_SHORT__i_bsic_i__rxlev,
1147 /* 1129*/ CCD_ID_RR_SHORT__mi_ext__e_len,
1148 /* 1130*/ CCD_ID_RR_SHORT__mi_ext__extens,
1149 /* 1131*/ CCD_ID_RR_SHORT__scdata__dtx_used,
1150 /* 1132*/ CCD_ID_RR_SHORT__scdata__rxlev,
1151 /* 1133*/ CCD_ID_RR_SHORT__scdata__rxqual_full,
1152 /* 1134*/ CCD_ID_RR_SHORT__scdata__mean_bep,
1153 /* 1135*/ CCD_ID_RR_SHORT__scdata__cv_bep,
1154 /* 1136*/ CCD_ID_RR_SHORT__scdata__nr_rcvd_bl,
1155 /* 1137*/ CCD_ID_RR_SHORT__rep_q_arr__rep_q,
1156 /* 1138*/ CCD_ID_RR_SHORT__em_rep__rep_q_arr,
1157 /* 1139*/ CCD_ID_RR_SHORT__U_EMR__msg_type,
1158 /* 1140*/ CCD_ID_RR_SHORT__U_EMR__sl2h,
1159 /* 1141*/ CCD_ID_RR_SHORT__U_EMR__ba_ind,
1160 /* 1142*/ CCD_ID_RR_SHORT__U_EMR__ba_ind_3g,
1161 /* 1143*/ CCD_ID_RR_SHORT__U_EMR__bsic_seen,
1162 /* 1144*/ CCD_ID_RR_SHORT__U_EMR__scale,
1163 /* 1145*/ CCD_ID_RR_SHORT__U_EMR__scdata,
1164 /* 1146*/ CCD_ID_RR_SHORT__U_EMR__i_bsic_i,
1165 /* 1147*/ CCD_ID_RR_SHORT__U_EMR__em_rep,
1166 /* 1148*/ CCD_ID_RR_SHORT__U_EMR__spare_0,
1167 /* 1149*/ CCD_ID_RR_SHORT__D_MEAS_INF__msg_type,
1168 /* 1150*/ CCD_ID_RR_SHORT__D_MEAS_INF__sl2h,
1169 /* 1151*/ CCD_ID_RR_SHORT__D_MEAS_INF__ba_ind,
1170 /* 1152*/ CCD_ID_RR_SHORT__D_MEAS_INF__ba_ind_3g,
1171 /* 1153*/ CCD_ID_RR_SHORT__D_MEAS_INF__mp_cm,
1172 /* 1154*/ CCD_ID_RR_SHORT__D_MEAS_INF__mi_idx,
1173 /* 1155*/ CCD_ID_RR_SHORT__D_MEAS_INF__mi_c,
1174 /* 1156*/ CCD_ID_RR_SHORT__D_MEAS_INF__pow_ctrl,
1175 /* 1157*/ CCD_ID_RR_SHORT__D_MEAS_INF__report_type,
1176 /* 1158*/ CCD_ID_RR_SHORT__D_MEAS_INF__rep_rate,
1177 /* 1159*/ CCD_ID_RR_SHORT__D_MEAS_INF__inv_bsic_rep,
1178 /* 1160*/ CCD_ID_RR_SHORT__D_MEAS_INF__rtdd,
1179 /* 1161*/ CCD_ID_RR_SHORT__D_MEAS_INF__gprs_bsic,
1180 /* 1162*/ CCD_ID_RR_SHORT__D_MEAS_INF__gprs_rep_prio,
1181 /* 1163*/ CCD_ID_RR_SHORT__D_MEAS_INF__emp,
1182 /* 1164*/ CCD_ID_RR_SHORT__D_MEAS_INF__mi_ext,
1183 /* 1165*/ CCD_ID_RR_SHORT__D_MEAS_INF__spare_0,
1184 /* 1166*/ CCD_ID_MM__auth_rand__rand,
1185 /* 1167*/ CCD_ID_MM__ciph_key_num__spare_0,
1186 /* 1168*/ CCD_ID_MM__ciph_key_num__key_seq,
1187 /* 1169*/ CCD_ID_MM__ident__spare_0,
1188 /* 1170*/ CCD_ID_MM__ident__ident_type,
1189 /* 1171*/ CCD_ID_MM__loc_area_ident__mcc,
1190 /* 1172*/ CCD_ID_MM__loc_area_ident__mnc,
1191 /* 1173*/ CCD_ID_MM__loc_area_ident__lac,
1192 /* 1174*/ CCD_ID_MM__loc_upd_type__follow,
1193 /* 1175*/ CCD_ID_MM__loc_upd_type__spare_0,
1194 /* 1176*/ CCD_ID_MM__loc_upd_type__lut,
1195 /* 1177*/ CCD_ID_MM__mob_id__ident_type,
1196 /* 1178*/ CCD_ID_MM__mob_id__odd_even,
1197 /* 1179*/ CCD_ID_MM__mob_id__ident_dig,
1198 /* 1180*/ CCD_ID_MM__mob_id__spare_0,
1199 /* 1181*/ CCD_ID_MM__mob_id__tmsi,
1200 /* 1182*/ CCD_ID_MM__mob_id__dmy,
1201 /* 1183*/ CCD_ID_MM__pd_and_sapi__spare_0,
1202 /* 1184*/ CCD_ID_MM__pd_and_sapi__sapi,
1203 /* 1185*/ CCD_ID_MM__pd_and_sapi__pd,
1204 /* 1186*/ CCD_ID_MM__full_net_name__spare_0,
1205 /* 1187*/ CCD_ID_MM__full_net_name__cs,
1206 /* 1188*/ CCD_ID_MM__full_net_name__add_ci,
1207 /* 1189*/ CCD_ID_MM__full_net_name__num_spare,
1208 /* 1190*/ CCD_ID_MM__full_net_name__text,
1209 /* 1191*/ CCD_ID_MM__net_tz__tz,
1210 /* 1192*/ CCD_ID_MM__net_tz_and_time__year,
1211 /* 1193*/ CCD_ID_MM__net_tz_and_time__month,
1212 /* 1194*/ CCD_ID_MM__net_tz_and_time__day,
1213 /* 1195*/ CCD_ID_MM__net_tz_and_time__hour,
1214 /* 1196*/ CCD_ID_MM__net_tz_and_time__minute,
1215 /* 1197*/ CCD_ID_MM__net_tz_and_time__second,
1216 /* 1198*/ CCD_ID_MM__net_tz_and_time__tz,
1217 /* 1199*/ CCD_ID_MM__lsa_identifier__lsa_id,
1218 /* 1200*/ CCD_ID_MM__daylight_save_time__spare_0,
1219 /* 1201*/ CCD_ID_MM__daylight_save_time__save_time_value,
1220 /* 1202*/ CCD_ID_MM__eqv_plmn__mcc,
1221 /* 1203*/ CCD_ID_MM__eqv_plmn__mnc,
1222 /* 1204*/ CCD_ID_MM__eqv_plmn_list__eqv_plmn,
1223 /* 1205*/ CCD_ID_MM__D_ABORT__msg_type,
1224 /* 1206*/ CCD_ID_MM__D_ABORT__rej_cause,
1225 /* 1207*/ CCD_ID_MM__D_AUTH_REJ__msg_type,
1226 /* 1208*/ CCD_ID_MM__D_AUTH_REQ__msg_type,
1227 /* 1209*/ CCD_ID_MM__D_AUTH_REQ__ciph_key_num,
1228 /* 1210*/ CCD_ID_MM__D_AUTH_REQ__spare_0,
1229 /* 1211*/ CCD_ID_MM__D_AUTH_REQ__auth_rand,
1230 /* 1212*/ CCD_ID_MM__U_AUTH_RES__msg_type,
1231 /* 1213*/ CCD_ID_MM__U_AUTH_RES__auth_sres,
1232 /* 1214*/ CCD_ID_MM__U_CM_REESTAB_REQ__msg_type,
1233 /* 1215*/ CCD_ID_MM__U_CM_REESTAB_REQ__ciph_key_num,
1234 /* 1216*/ CCD_ID_MM__U_CM_REESTAB_REQ__spare_0,
1235 /* 1217*/ CCD_ID_MM__U_CM_REESTAB_REQ__mob_class_2,
1236 /* 1218*/ CCD_ID_MM__U_CM_REESTAB_REQ__mob_id,
1237 /* 1219*/ CCD_ID_MM__U_CM_REESTAB_REQ__loc_area_ident,
1238 /* 1220*/ CCD_ID_MM__U_CM_SERV_ABORT__msg_type,
1239 /* 1221*/ CCD_ID_MM__D_CM_SERV_ACCEPT__msg_type,
1240 /* 1222*/ CCD_ID_MM__D_CM_SERV_REJ__msg_type,
1241 /* 1223*/ CCD_ID_MM__D_CM_SERV_REJ__rej_cause,
1242 /* 1224*/ CCD_ID_MM__U_CM_SERV_REQ__msg_type,
1243 /* 1225*/ CCD_ID_MM__U_CM_SERV_REQ__cm_serv_type,
1244 /* 1226*/ CCD_ID_MM__U_CM_SERV_REQ__ciph_key_num,
1245 /* 1227*/ CCD_ID_MM__U_CM_SERV_REQ__mob_class_2,
1246 /* 1228*/ CCD_ID_MM__U_CM_SERV_REQ__mob_id,
1247 /* 1229*/ CCD_ID_MM__D_IDENT_REQ__msg_type,
1248 /* 1230*/ CCD_ID_MM__D_IDENT_REQ__ident,
1249 /* 1231*/ CCD_ID_MM__D_IDENT_REQ__spare_0,
1250 /* 1232*/ CCD_ID_MM__U_IDENT_RES__msg_type,
1251 /* 1233*/ CCD_ID_MM__U_IDENT_RES__mob_id,
1252 /* 1234*/ CCD_ID_MM__U_IMSI_DETACH_IND__msg_type,
1253 /* 1235*/ CCD_ID_MM__U_IMSI_DETACH_IND__mob_class_1,
1254 /* 1236*/ CCD_ID_MM__U_IMSI_DETACH_IND__mob_id,
1255 /* 1237*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__msg_type,
1256 /* 1238*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__loc_area_ident,
1257 /* 1239*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__mob_id,
1258 /* 1240*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__follow_proceed,
1259 /* 1241*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__cts_per,
1260 /* 1242*/ CCD_ID_MM__D_LOC_UPD_ACCEPT__eqv_plmn_list,
1261 /* 1243*/ CCD_ID_MM__D_LOC_UPD_REJ__msg_type,
1262 /* 1244*/ CCD_ID_MM__D_LOC_UPD_REJ__rej_cause,
1263 /* 1245*/ CCD_ID_MM__U_LOC_UPD_REQ__msg_type,
1264 /* 1246*/ CCD_ID_MM__U_LOC_UPD_REQ__loc_upd_type,
1265 /* 1247*/ CCD_ID_MM__U_LOC_UPD_REQ__ciph_key_num,
1266 /* 1248*/ CCD_ID_MM__U_LOC_UPD_REQ__loc_area_ident,
1267 /* 1249*/ CCD_ID_MM__U_LOC_UPD_REQ__mob_class_1,
1268 /* 1250*/ CCD_ID_MM__U_LOC_UPD_REQ__mob_id,
1269 /* 1251*/ CCD_ID_MM__B_MM_STATUS__msg_type,
1270 /* 1252*/ CCD_ID_MM__B_MM_STATUS__rej_cause,
1271 /* 1253*/ CCD_ID_MM__D_TMSI_REALLOC_CMD__msg_type,
1272 /* 1254*/ CCD_ID_MM__D_TMSI_REALLOC_CMD__loc_area_ident,
1273 /* 1255*/ CCD_ID_MM__D_TMSI_REALLOC_CMD__mob_id,
1274 /* 1256*/ CCD_ID_MM__U_TMSI_REALLOC_COMP__msg_type,
1275 /* 1257*/ CCD_ID_MM__D_CM_SERVICE_PROMPT__msg_type,
1276 /* 1258*/ CCD_ID_MM__D_CM_SERVICE_PROMPT__pd_and_sapi,
1277 /* 1259*/ CCD_ID_MM__D_MM_INFORMATION__msg_type,
1278 /* 1260*/ CCD_ID_MM__D_MM_INFORMATION__full_net_name,
1279 /* 1261*/ CCD_ID_MM__D_MM_INFORMATION__short_net_name,
1280 /* 1262*/ CCD_ID_MM__D_MM_INFORMATION__net_tz,
1281 /* 1263*/ CCD_ID_MM__D_MM_INFORMATION__net_tz_and_time,
1282 /* 1264*/ CCD_ID_MM__D_MM_INFORMATION__lsa_identifier,
1283 /* 1265*/ CCD_ID_MM__D_MM_INFORMATION__daylight_save_time,
1284 /* 1266*/ CCD_ID_CC__aux_states__spare_0,
1285 /* 1267*/ CCD_ID_CC__aux_states__hold,
1286 /* 1268*/ CCD_ID_CC__aux_states__mpty,
1287 /* 1269*/ CCD_ID_CC__bearer_cap__rad_chan_req,
1288 /* 1270*/ CCD_ID_CC__bearer_cap__code,
1289 /* 1271*/ CCD_ID_CC__bearer_cap__trans_mode,
1290 /* 1272*/ CCD_ID_CC__bearer_cap__trans_cap,
1291 /* 1273*/ CCD_ID_CC__bearer_cap__coding_bc3x1,
1292 /* 1274*/ CCD_ID_CC__bearer_cap__ctm,
1293 /* 1275*/ CCD_ID_CC__bearer_cap__spare_0,
1294 /* 1276*/ CCD_ID_CC__bearer_cap__speech_vers1,
1295 /* 1277*/ CCD_ID_CC__bearer_cap__coding_bc3x2,
1296 /* 1278*/ CCD_ID_CC__bearer_cap__spare_1,
1297 /* 1279*/ CCD_ID_CC__bearer_cap__speech_vers2,
1298 /* 1280*/ CCD_ID_CC__bearer_cap__coding_bc3x3,
1299 /* 1281*/ CCD_ID_CC__bearer_cap__spare_2,
1300 /* 1282*/ CCD_ID_CC__bearer_cap__speech_vers3,
1301 /* 1283*/ CCD_ID_CC__bearer_cap__coding_bc3x4,
1302 /* 1284*/ CCD_ID_CC__bearer_cap__spare_3,
1303 /* 1285*/ CCD_ID_CC__bearer_cap__speech_vers4,
1304 /* 1286*/ CCD_ID_CC__bearer_cap__coding_bc3x5,
1305 /* 1287*/ CCD_ID_CC__bearer_cap__spare_4,
1306 /* 1288*/ CCD_ID_CC__bearer_cap__speech_vers5,
1307 /* 1289*/ CCD_ID_CC__bearer_cap__compress,
1308 /* 1290*/ CCD_ID_CC__bearer_cap__structure,
1309 /* 1291*/ CCD_ID_CC__bearer_cap__duplex,
1310 /* 1292*/ CCD_ID_CC__bearer_cap__config,
1311 /* 1293*/ CCD_ID_CC__bearer_cap__nirr,
1312 /* 1294*/ CCD_ID_CC__bearer_cap__establish,
1313 /* 1295*/ CCD_ID_CC__bearer_cap__access_ident,
1314 /* 1296*/ CCD_ID_CC__bearer_cap__rate_adapt,
1315 /* 1297*/ CCD_ID_CC__bearer_cap__sig_access_prot,
1316 /* 1298*/ CCD_ID_CC__bearer_cap__other_itc,
1317 /* 1299*/ CCD_ID_CC__bearer_cap__other_ra,
1318 /* 1300*/ CCD_ID_CC__bearer_cap__spare_5,
1319 /* 1301*/ CCD_ID_CC__bearer_cap__ra_header,
1320 /* 1302*/ CCD_ID_CC__bearer_cap__multiple_frame,
1321 /* 1303*/ CCD_ID_CC__bearer_cap__mode_of_operation,
1322 /* 1304*/ CCD_ID_CC__bearer_cap__lli_negotiation,
1323 /* 1305*/ CCD_ID_CC__bearer_cap__assignor_assignee,
1324 /* 1306*/ CCD_ID_CC__bearer_cap__in_out_band_negotiation,
1325 /* 1307*/ CCD_ID_CC__bearer_cap__spare_6,
1326 /* 1308*/ CCD_ID_CC__bearer_cap__sig_access_prot,
1327 /* 1309*/ CCD_ID_CC__bearer_cap__l1_ident,
1328 /* 1310*/ CCD_ID_CC__bearer_cap__user_inf_l1_prot,
1329 /* 1311*/ CCD_ID_CC__bearer_cap__sync_async,
1330 /* 1312*/ CCD_ID_CC__bearer_cap__num_stop,
1331 /* 1313*/ CCD_ID_CC__bearer_cap__negotiate,
1332 /* 1314*/ CCD_ID_CC__bearer_cap__num_data,
1333 /* 1315*/ CCD_ID_CC__bearer_cap__user_rate,
1334 /* 1316*/ CCD_ID_CC__bearer_cap__intermed_rate,
1335 /* 1317*/ CCD_ID_CC__bearer_cap__nic_tx,
1336 /* 1318*/ CCD_ID_CC__bearer_cap__nic_rx,
1337 /* 1319*/ CCD_ID_CC__bearer_cap__parity,
1338 /* 1320*/ CCD_ID_CC__bearer_cap__conn_elem,
1339 /* 1321*/ CCD_ID_CC__bearer_cap__modem_type,
1340 /* 1322*/ CCD_ID_CC__bearer_cap__modem_type_2,
1341 /* 1323*/ CCD_ID_CC__bearer_cap__fnur,
1342 /* 1324*/ CCD_ID_CC__bearer_cap__acc,
1343 /* 1325*/ CCD_ID_CC__bearer_cap__mTch,
1344 /* 1326*/ CCD_ID_CC__bearer_cap__uimi,
1345 /* 1327*/ CCD_ID_CC__bearer_cap__waiur,
1346 /* 1328*/ CCD_ID_CC__bearer_cap__acc_ext_288,
1347 /* 1329*/ CCD_ID_CC__bearer_cap__acc_ext_320,
1348 /* 1330*/ CCD_ID_CC__bearer_cap__acc_ext_432,
1349 /* 1331*/ CCD_ID_CC__bearer_cap__ch_cod_asym,
1350 /* 1332*/ CCD_ID_CC__bearer_cap__spare_7,
1351 /* 1333*/ CCD_ID_CC__bearer_cap__waiur,
1352 /* 1334*/ CCD_ID_CC__bearer_cap__l2_ident,
1353 /* 1335*/ CCD_ID_CC__bearer_cap__user_inf_l2_prot,
1354 /* 1336*/ CCD_ID_CC__call_ctrl_cap__max_nof_supp_bearers,
1355 /* 1337*/ CCD_ID_CC__call_ctrl_cap__spare_0,
1356 /* 1338*/ CCD_ID_CC__call_ctrl_cap__pcp,
1357 /* 1339*/ CCD_ID_CC__call_ctrl_cap__dtmf,
1358 /* 1340*/ CCD_ID_CC__call_ctrl_cap__spare_2,
1359 /* 1341*/ CCD_ID_CC__call_ctrl_cap__max_nof_supp_speech_bearers,
1360 /* 1342*/ CCD_ID_CC__call_state__cs,
1361 /* 1343*/ CCD_ID_CC__call_state__state,
1362 /* 1344*/ CCD_ID_CC__dl_called_num__ton,
1363 /* 1345*/ CCD_ID_CC__dl_called_num__npi,
1364 /* 1346*/ CCD_ID_CC__dl_called_num__num,
1365 /* 1347*/ CCD_ID_CC__ul_called_num__ton,
1366 /* 1348*/ CCD_ID_CC__ul_called_num__npi,
1367 /* 1349*/ CCD_ID_CC__ul_called_num__num,
1368 /* 1350*/ CCD_ID_CC__called_subaddr__tos,
1369 /* 1351*/ CCD_ID_CC__called_subaddr__odd_even,
1370 /* 1352*/ CCD_ID_CC__called_subaddr__spare_0,
1371 /* 1353*/ CCD_ID_CC__called_subaddr__subaddr,
1372 /* 1354*/ CCD_ID_CC__calling_num__ton,
1373 /* 1355*/ CCD_ID_CC__calling_num__npi,
1374 /* 1356*/ CCD_ID_CC__calling_num__present,
1375 /* 1357*/ CCD_ID_CC__calling_num__spare_0,
1376 /* 1358*/ CCD_ID_CC__calling_num__screen,
1377 /* 1359*/ CCD_ID_CC__calling_num__num,
1378 /* 1360*/ CCD_ID_CC__calling_subaddr__tos,
1379 /* 1361*/ CCD_ID_CC__calling_subaddr__odd_even,
1380 /* 1362*/ CCD_ID_CC__calling_subaddr__spare_0,
1381 /* 1363*/ CCD_ID_CC__calling_subaddr__subaddr,
1382 /* 1364*/ CCD_ID_CC__cc_cause__cs,
1383 /* 1365*/ CCD_ID_CC__cc_cause__spare_0,
1384 /* 1366*/ CCD_ID_CC__cc_cause__loc,
1385 /* 1367*/ CCD_ID_CC__cc_cause__rec,
1386 /* 1368*/ CCD_ID_CC__cc_cause__cause,
1387 /* 1369*/ CCD_ID_CC__cc_cause__diag,
1388 /* 1370*/ CCD_ID_CC__connect_num__ton,
1389 /* 1371*/ CCD_ID_CC__connect_num__npi,
1390 /* 1372*/ CCD_ID_CC__connect_num__present,
1391 /* 1373*/ CCD_ID_CC__connect_num__spare_0,
1392 /* 1374*/ CCD_ID_CC__connect_num__screen,
1393 /* 1375*/ CCD_ID_CC__connect_num__num,
1394 /* 1376*/ CCD_ID_CC__connect_subaddr__tos,
1395 /* 1377*/ CCD_ID_CC__connect_subaddr__odd_even,
1396 /* 1378*/ CCD_ID_CC__connect_subaddr__spare_0,
1397 /* 1379*/ CCD_ID_CC__connect_subaddr__subaddr,
1398 /* 1380*/ CCD_ID_CC__facility__fac,
1399 /* 1381*/ CCD_ID_CC__high_layer_comp__cs,
1400 /* 1382*/ CCD_ID_CC__high_layer_comp__interpret,
1401 /* 1383*/ CCD_ID_CC__high_layer_comp__prot_prof,
1402 /* 1384*/ CCD_ID_CC__high_layer_comp__hlci,
1403 /* 1385*/ CCD_ID_CC__high_layer_comp__ext_hlci,
1404 /* 1386*/ CCD_ID_CC__key_facility__spare_0,
1405 /* 1387*/ CCD_ID_CC__key_facility__key,
1406 /* 1388*/ CCD_ID_CC__low_layer_comp__llc,
1407 /* 1389*/ CCD_ID_CC__notific__nd,
1408 /* 1390*/ CCD_ID_CC__progress__cs,
1409 /* 1391*/ CCD_ID_CC__progress__spare_0,
1410 /* 1392*/ CCD_ID_CC__progress__loc,
1411 /* 1393*/ CCD_ID_CC__progress__progress_desc,
1412 /* 1394*/ CCD_ID_CC__ss_version__ver,
1413 /* 1395*/ CCD_ID_CC__user_user__pd,
1414 /* 1396*/ CCD_ID_CC__user_user__info,
1415 /* 1397*/ CCD_ID_CC__allowed_actions__ccbs_act,
1416 /* 1398*/ CCD_ID_CC__allowed_actions__spare_0,
1417 /* 1399*/ CCD_ID_CC__recall_type__spare_0,
1418 /* 1400*/ CCD_ID_CC__recall_type__rcl_type,
1419 /* 1401*/ CCD_ID_CC__setup_cont__setup_msg,
1420 /* 1402*/ CCD_ID_CC__redirecting_num__ton,
1421 /* 1403*/ CCD_ID_CC__redirecting_num__npi,
1422 /* 1404*/ CCD_ID_CC__redirecting_num__present,
1423 /* 1405*/ CCD_ID_CC__redirecting_num__spare_0,
1424 /* 1406*/ CCD_ID_CC__redirecting_num__screen,
1425 /* 1407*/ CCD_ID_CC__redirecting_num__num,
1426 /* 1408*/ CCD_ID_CC__redirecting_subaddr__tos,
1427 /* 1409*/ CCD_ID_CC__redirecting_subaddr__odd_even,
1428 /* 1410*/ CCD_ID_CC__redirecting_subaddr__spare_0,
1429 /* 1411*/ CCD_ID_CC__redirecting_subaddr__subaddr,
1430 /* 1412*/ CCD_ID_CC__cause_of_no_cli__cause_no_cli,
1431 /* 1413*/ CCD_ID_CC__alerting_pattern__spare_0,
1432 /* 1414*/ CCD_ID_CC__alerting_pattern__alerting_pat,
1433 /* 1415*/ CCD_ID_CC__D_ALERT__msg_type,
1434 /* 1416*/ CCD_ID_CC__D_ALERT__facility,
1435 /* 1417*/ CCD_ID_CC__D_ALERT__progress,
1436 /* 1418*/ CCD_ID_CC__D_ALERT__user_user,
1437 /* 1419*/ CCD_ID_CC__U_ALERT__msg_type,
1438 /* 1420*/ CCD_ID_CC__U_ALERT__facility,
1439 /* 1421*/ CCD_ID_CC__U_ALERT__user_user,
1440 /* 1422*/ CCD_ID_CC__U_ALERT__ss_version,
1441 /* 1423*/ CCD_ID_CC__U_CALL_CONF__msg_type,
1442 /* 1424*/ CCD_ID_CC__U_CALL_CONF__repeat,
1443 /* 1425*/ CCD_ID_CC__U_CALL_CONF__bearer_cap,
1444 /* 1426*/ CCD_ID_CC__U_CALL_CONF__bearer_cap_2,
1445 /* 1427*/ CCD_ID_CC__U_CALL_CONF__cc_cause,
1446 /* 1428*/ CCD_ID_CC__U_CALL_CONF__call_ctrl_cap,
1447 /* 1429*/ CCD_ID_CC__D_CALL_PROCEED__msg_type,
1448 /* 1430*/ CCD_ID_CC__D_CALL_PROCEED__repeat,
1449 /* 1431*/ CCD_ID_CC__D_CALL_PROCEED__bearer_cap,
1450 /* 1432*/ CCD_ID_CC__D_CALL_PROCEED__bearer_cap_2,
1451 /* 1433*/ CCD_ID_CC__D_CALL_PROCEED__facility,
1452 /* 1434*/ CCD_ID_CC__D_CALL_PROCEED__progress,
1453 /* 1435*/ CCD_ID_CC__D_CALL_PROCEED__priority_grant,
1454 /* 1436*/ CCD_ID_CC__B_CONGEST_CTRL__msg_type,
1455 /* 1437*/ CCD_ID_CC__B_CONGEST_CTRL__congest_lev,
1456 /* 1438*/ CCD_ID_CC__B_CONGEST_CTRL__spare_0,
1457 /* 1439*/ CCD_ID_CC__B_CONGEST_CTRL__cc_cause,
1458 /* 1440*/ CCD_ID_CC__D_CONNECT__msg_type,
1459 /* 1441*/ CCD_ID_CC__D_CONNECT__facility,
1460 /* 1442*/ CCD_ID_CC__D_CONNECT__progress,
1461 /* 1443*/ CCD_ID_CC__D_CONNECT__connect_num,
1462 /* 1444*/ CCD_ID_CC__D_CONNECT__connect_subaddr,
1463 /* 1445*/ CCD_ID_CC__D_CONNECT__user_user,
1464 /* 1446*/ CCD_ID_CC__U_CONNECT__msg_type,
1465 /* 1447*/ CCD_ID_CC__U_CONNECT__facility,
1466 /* 1448*/ CCD_ID_CC__U_CONNECT__connect_subaddr,
1467 /* 1449*/ CCD_ID_CC__U_CONNECT__user_user,
1468 /* 1450*/ CCD_ID_CC__U_CONNECT__ss_version,
1469 /* 1451*/ CCD_ID_CC__B_CONNECT_ACK__msg_type,
1470 /* 1452*/ CCD_ID_CC__D_DISCONNECT__msg_type,
1471 /* 1453*/ CCD_ID_CC__D_DISCONNECT__cc_cause,
1472 /* 1454*/ CCD_ID_CC__D_DISCONNECT__facility,
1473 /* 1455*/ CCD_ID_CC__D_DISCONNECT__progress,
1474 /* 1456*/ CCD_ID_CC__D_DISCONNECT__user_user,
1475 /* 1457*/ CCD_ID_CC__D_DISCONNECT__allowed_actions,
1476 /* 1458*/ CCD_ID_CC__U_DISCONNECT__msg_type,
1477 /* 1459*/ CCD_ID_CC__U_DISCONNECT__cc_cause,
1478 /* 1460*/ CCD_ID_CC__U_DISCONNECT__facility,
1479 /* 1461*/ CCD_ID_CC__U_DISCONNECT__user_user,
1480 /* 1462*/ CCD_ID_CC__U_DISCONNECT__ss_version,
1481 /* 1463*/ CCD_ID_CC__U_EMERGE_SETUP__msg_type,
1482 /* 1464*/ CCD_ID_CC__U_EMERGE_SETUP__bearer_cap,
1483 /* 1465*/ CCD_ID_CC__D_FACILITY__msg_type,
1484 /* 1466*/ CCD_ID_CC__D_FACILITY__facility,
1485 /* 1467*/ CCD_ID_CC__U_FACILITY__msg_type,
1486 /* 1468*/ CCD_ID_CC__U_FACILITY__facility,
1487 /* 1469*/ CCD_ID_CC__U_FACILITY__ss_version,
1488 /* 1470*/ CCD_ID_CC__U_HOLD__msg_type,
1489 /* 1471*/ CCD_ID_CC__D_HOLD_ACK__msg_type,
1490 /* 1472*/ CCD_ID_CC__D_HOLD_REJ__msg_type,
1491 /* 1473*/ CCD_ID_CC__D_HOLD_REJ__cc_cause,
1492 /* 1474*/ CCD_ID_CC__B_MODIFY__msg_type,
1493 /* 1475*/ CCD_ID_CC__B_MODIFY__bearer_cap,
1494 /* 1476*/ CCD_ID_CC__B_MODIFY__low_layer_comp,
1495 /* 1477*/ CCD_ID_CC__B_MODIFY__high_layer_comp,
1496 /* 1478*/ CCD_ID_CC__B_MODIFY__reverse_call,
1497 /* 1479*/ CCD_ID_CC__B_MODIFY__immediate_mod,
1498 /* 1480*/ CCD_ID_CC__B_MODIFY_COMP__msg_type,
1499 /* 1481*/ CCD_ID_CC__B_MODIFY_COMP__bearer_cap,
1500 /* 1482*/ CCD_ID_CC__B_MODIFY_COMP__low_layer_comp,
1501 /* 1483*/ CCD_ID_CC__B_MODIFY_COMP__high_layer_comp,
1502 /* 1484*/ CCD_ID_CC__B_MODIFY_COMP__reverse_call,
1503 /* 1485*/ CCD_ID_CC__B_MODIFY_REJ__msg_type,
1504 /* 1486*/ CCD_ID_CC__B_MODIFY_REJ__bearer_cap,
1505 /* 1487*/ CCD_ID_CC__B_MODIFY_REJ__cc_cause,
1506 /* 1488*/ CCD_ID_CC__B_MODIFY_REJ__low_layer_comp,
1507 /* 1489*/ CCD_ID_CC__B_MODIFY_REJ__high_layer_comp,
1508 /* 1490*/ CCD_ID_CC__B_NOTIFY__msg_type,
1509 /* 1491*/ CCD_ID_CC__B_NOTIFY__notific,
1510 /* 1492*/ CCD_ID_CC__D_PROGRESS__msg_type,
1511 /* 1493*/ CCD_ID_CC__D_PROGRESS__progress,
1512 /* 1494*/ CCD_ID_CC__D_PROGRESS__user_user,
1513 /* 1495*/ CCD_ID_CC__D_RELEASE__msg_type,
1514 /* 1496*/ CCD_ID_CC__D_RELEASE__cc_cause,
1515 /* 1497*/ CCD_ID_CC__D_RELEASE__cc_cause_2,
1516 /* 1498*/ CCD_ID_CC__D_RELEASE__facility,
1517 /* 1499*/ CCD_ID_CC__D_RELEASE__user_user,
1518 /* 1500*/ CCD_ID_CC__U_RELEASE__msg_type,
1519 /* 1501*/ CCD_ID_CC__U_RELEASE__cc_cause,
1520 /* 1502*/ CCD_ID_CC__U_RELEASE__cc_cause_2,
1521 /* 1503*/ CCD_ID_CC__U_RELEASE__facility,
1522 /* 1504*/ CCD_ID_CC__U_RELEASE__user_user,
1523 /* 1505*/ CCD_ID_CC__U_RELEASE__ss_version,
1524 /* 1506*/ CCD_ID_CC__D_RELEASE_COMP__msg_type,
1525 /* 1507*/ CCD_ID_CC__D_RELEASE_COMP__cc_cause,
1526 /* 1508*/ CCD_ID_CC__D_RELEASE_COMP__facility,
1527 /* 1509*/ CCD_ID_CC__D_RELEASE_COMP__user_user,
1528 /* 1510*/ CCD_ID_CC__U_RELEASE_COMP__msg_type,
1529 /* 1511*/ CCD_ID_CC__U_RELEASE_COMP__cc_cause,
1530 /* 1512*/ CCD_ID_CC__U_RELEASE_COMP__facility,
1531 /* 1513*/ CCD_ID_CC__U_RELEASE_COMP__user_user,
1532 /* 1514*/ CCD_ID_CC__U_RELEASE_COMP__ss_version,
1533 /* 1515*/ CCD_ID_CC__U_RETRIEVE__msg_type,
1534 /* 1516*/ CCD_ID_CC__D_RETRIEVE_ACK__msg_type,
1535 /* 1517*/ CCD_ID_CC__D_RETRIEVE_REJ__msg_type,
1536 /* 1518*/ CCD_ID_CC__D_RETRIEVE_REJ__cc_cause,
1537 /* 1519*/ CCD_ID_CC__D_SETUP__msg_type,
1538 /* 1520*/ CCD_ID_CC__D_SETUP__repeat,
1539 /* 1521*/ CCD_ID_CC__D_SETUP__bearer_cap,
1540 /* 1522*/ CCD_ID_CC__D_SETUP__bearer_cap_2,
1541 /* 1523*/ CCD_ID_CC__D_SETUP__facility,
1542 /* 1524*/ CCD_ID_CC__D_SETUP__progress,
1543 /* 1525*/ CCD_ID_CC__D_SETUP__signal,
1544 /* 1526*/ CCD_ID_CC__D_SETUP__calling_num,
1545 /* 1527*/ CCD_ID_CC__D_SETUP__calling_subaddr,
1546 /* 1528*/ CCD_ID_CC__D_SETUP__dl_called_num,
1547 /* 1529*/ CCD_ID_CC__D_SETUP__called_subaddr,
1548 /* 1530*/ CCD_ID_CC__D_SETUP__redirecting_num,
1549 /* 1531*/ CCD_ID_CC__D_SETUP__redirecting_subaddr,
1550 /* 1532*/ CCD_ID_CC__D_SETUP__repeat_2,
1551 /* 1533*/ CCD_ID_CC__D_SETUP__low_layer_comp,
1552 /* 1534*/ CCD_ID_CC__D_SETUP__low_layer_comp_2,
1553 /* 1535*/ CCD_ID_CC__D_SETUP__repeat_3,
1554 /* 1536*/ CCD_ID_CC__D_SETUP__high_layer_comp,
1555 /* 1537*/ CCD_ID_CC__D_SETUP__high_layer_comp_2,
1556 /* 1538*/ CCD_ID_CC__D_SETUP__user_user,
1557 /* 1539*/ CCD_ID_CC__D_SETUP__priority_grant,
1558 /* 1540*/ CCD_ID_CC__D_SETUP__alerting_pattern,
1559 /* 1541*/ CCD_ID_CC__D_SETUP__cause_of_no_cli,
1560 /* 1542*/ CCD_ID_CC__U_SETUP__msg_type,
1561 /* 1543*/ CCD_ID_CC__U_SETUP__repeat,
1562 /* 1544*/ CCD_ID_CC__U_SETUP__bearer_cap,
1563 /* 1545*/ CCD_ID_CC__U_SETUP__bearer_cap_2,
1564 /* 1546*/ CCD_ID_CC__U_SETUP__facility,
1565 /* 1547*/ CCD_ID_CC__U_SETUP__calling_subaddr,
1566 /* 1548*/ CCD_ID_CC__U_SETUP__ul_called_num,
1567 /* 1549*/ CCD_ID_CC__U_SETUP__called_subaddr,
1568 /* 1550*/ CCD_ID_CC__U_SETUP__repeat_2,
1569 /* 1551*/ CCD_ID_CC__U_SETUP__low_layer_comp,
1570 /* 1552*/ CCD_ID_CC__U_SETUP__low_layer_comp_2,
1571 /* 1553*/ CCD_ID_CC__U_SETUP__repeat_3,
1572 /* 1554*/ CCD_ID_CC__U_SETUP__high_layer_comp,
1573 /* 1555*/ CCD_ID_CC__U_SETUP__high_layer_comp_2,
1574 /* 1556*/ CCD_ID_CC__U_SETUP__user_user,
1575 /* 1557*/ CCD_ID_CC__U_SETUP__ss_version,
1576 /* 1558*/ CCD_ID_CC__U_SETUP__clir_suppr,
1577 /* 1559*/ CCD_ID_CC__U_SETUP__clir_invoc,
1578 /* 1560*/ CCD_ID_CC__U_SETUP__call_ctrl_cap,
1579 /* 1561*/ CCD_ID_CC__U_SETUP__fac_adv,
1580 /* 1562*/ CCD_ID_CC__U_START_DTMF__msg_type,
1581 /* 1563*/ CCD_ID_CC__U_START_DTMF__key_facility,
1582 /* 1564*/ CCD_ID_CC__D_START_DTMF_ACK__msg_type,
1583 /* 1565*/ CCD_ID_CC__D_START_DTMF_ACK__key_facility,
1584 /* 1566*/ CCD_ID_CC__D_START_DTMF_REJ__msg_type,
1585 /* 1567*/ CCD_ID_CC__D_START_DTMF_REJ__cc_cause,
1586 /* 1568*/ CCD_ID_CC__B_STATUS__msg_type,
1587 /* 1569*/ CCD_ID_CC__B_STATUS__cc_cause,
1588 /* 1570*/ CCD_ID_CC__B_STATUS__call_state,
1589 /* 1571*/ CCD_ID_CC__B_STATUS__aux_states,
1590 /* 1572*/ CCD_ID_CC__B_STATUS_ENQ__msg_type,
1591 /* 1573*/ CCD_ID_CC__U_STOP_DTMF__msg_type,
1592 /* 1574*/ CCD_ID_CC__D_STOP_DTMF_ACK__msg_type,
1593 /* 1575*/ CCD_ID_CC__B_USER_INFO__msg_type,
1594 /* 1576*/ CCD_ID_CC__B_USER_INFO__user_user,
1595 /* 1577*/ CCD_ID_CC__B_USER_INFO__more_data,
1596 /* 1578*/ CCD_ID_CC__U_START_CC__msg_type,
1597 /* 1579*/ CCD_ID_CC__U_START_CC__call_ctrl_cap,
1598 /* 1580*/ CCD_ID_CC__D_RECALL__msg_type,
1599 /* 1581*/ CCD_ID_CC__D_RECALL__recall_type,
1600 /* 1582*/ CCD_ID_CC__D_RECALL__facility,
1601 /* 1583*/ CCD_ID_CC__U_CC_EST_CONF__msg_type,
1602 /* 1584*/ CCD_ID_CC__U_CC_EST_CONF__repeat,
1603 /* 1585*/ CCD_ID_CC__U_CC_EST_CONF__bearer_cap,
1604 /* 1586*/ CCD_ID_CC__U_CC_EST_CONF__bearer_cap_2,
1605 /* 1587*/ CCD_ID_CC__U_CC_EST_CONF__cc_cause,
1606 /* 1588*/ CCD_ID_CC__D_CC_ESTABLISHMENT__msg_type,
1607 /* 1589*/ CCD_ID_CC__D_CC_ESTABLISHMENT__setup_cont,
1608 /* 1590*/ CCD_ID_SS__ss_facility__fac_info,
1609 /* 1591*/ CCD_ID_SS__ss_version__ver,
1610 /* 1592*/ CCD_ID_SS__ss_cause__cs2,
1611 /* 1593*/ CCD_ID_SS__ss_cause__spare_0,
1612 /* 1594*/ CCD_ID_SS__ss_cause__loc,
1613 /* 1595*/ CCD_ID_SS__ss_cause__rec,
1614 /* 1596*/ CCD_ID_SS__ss_cause__cs,
1615 /* 1597*/ CCD_ID_SS__ss_cause__diag,
1616 /* 1598*/ CCD_ID_SS__D_SS_FACILITY__msg_type,
1617 /* 1599*/ CCD_ID_SS__D_SS_FACILITY__ss_facility,
1618 /* 1600*/ CCD_ID_SS__U_SS_FACILITY__msg_type,
1619 /* 1601*/ CCD_ID_SS__U_SS_FACILITY__ss_facility,
1620 /* 1602*/ CCD_ID_SS__D_SS_REGISTER__msg_type,
1621 /* 1603*/ CCD_ID_SS__D_SS_REGISTER__ss_facility,
1622 /* 1604*/ CCD_ID_SS__U_SS_REGISTER__msg_type,
1623 /* 1605*/ CCD_ID_SS__U_SS_REGISTER__ss_facility,
1624 /* 1606*/ CCD_ID_SS__U_SS_REGISTER__ss_version,
1625 /* 1607*/ CCD_ID_SS__B_SS_REL_COMP__msg_type,
1626 /* 1608*/ CCD_ID_SS__B_SS_REL_COMP__ss_cause,
1627 /* 1609*/ CCD_ID_SS__B_SS_REL_COMP__ss_facility,
1628 /* 1610*/ CCD_ID_SMS__rp_cause__rp_cause_value,
1629 /* 1611*/ CCD_ID_SMS__rp_cause__diag,
1630 /* 1612*/ CCD_ID_SMS__rp_addr__ton,
1631 /* 1613*/ CCD_ID_SMS__rp_addr__npi,
1632 /* 1614*/ CCD_ID_SMS__rp_addr__num,
1633 /* 1615*/ CCD_ID_SMS__rp_user_data__tp_mti,
1634 /* 1616*/ CCD_ID_SMS__rp_user_data__tpdu,
1635 /* 1617*/ CCD_ID_SMS__rp_ack__rp_user_data,
1636 /* 1618*/ CCD_ID_SMS__rp_error__rp_cause,
1637 /* 1619*/ CCD_ID_SMS__rp_error__rp_user_data,
1638 /* 1620*/ CCD_ID_SMS__rp_data_dl__rp_addr,
1639 /* 1621*/ CCD_ID_SMS__rp_data_dl__spare_0,
1640 /* 1622*/ CCD_ID_SMS__rp_data_dl__rp_user_data,
1641 /* 1623*/ CCD_ID_SMS__cp_user_data_dl__spare_0,
1642 /* 1624*/ CCD_ID_SMS__cp_user_data_dl__rp_mti,
1643 /* 1625*/ CCD_ID_SMS__cp_user_data_dl__reference,
1644 /* 1626*/ CCD_ID_SMS__cp_user_data_dl__rp_data_dl,
1645 /* 1627*/ CCD_ID_SMS__cp_user_data_dl__rp_error,
1646 /* 1628*/ CCD_ID_SMS__cp_user_data_dl__rp_ack,
1647 /* 1629*/ CCD_ID_SMS__rp_data_ul__spare_0,
1648 /* 1630*/ CCD_ID_SMS__rp_data_ul__rp_addr,
1649 /* 1631*/ CCD_ID_SMS__rp_data_ul__rp_user_data,
1650 /* 1632*/ CCD_ID_SMS__cp_user_data_ul__spare_0,
1651 /* 1633*/ CCD_ID_SMS__cp_user_data_ul__rp_mti,
1652 /* 1634*/ CCD_ID_SMS__cp_user_data_ul__reference,
1653 /* 1635*/ CCD_ID_SMS__cp_user_data_ul__rp_data_ul,
1654 /* 1636*/ CCD_ID_SMS__cp_user_data_ul__rp_error,
1655 /* 1637*/ CCD_ID_SMS__cp_user_data_ul__rp_ack,
1656 /* 1638*/ CCD_ID_SMS__tp_cd__data,
1657 /* 1639*/ CCD_ID_SMS__tp_da__digits,
1658 /* 1640*/ CCD_ID_SMS__tp_da__spare_0,
1659 /* 1641*/ CCD_ID_SMS__tp_da__ton,
1660 /* 1642*/ CCD_ID_SMS__tp_da__npi,
1661 /* 1643*/ CCD_ID_SMS__tp_da__num,
1662 /* 1644*/ CCD_ID_SMS__tp_vp_abs__year,
1663 /* 1645*/ CCD_ID_SMS__tp_vp_abs__month,
1664 /* 1646*/ CCD_ID_SMS__tp_vp_abs__day,
1665 /* 1647*/ CCD_ID_SMS__tp_vp_abs__hour,
1666 /* 1648*/ CCD_ID_SMS__tp_vp_abs__minute,
1667 /* 1649*/ CCD_ID_SMS__tp_vp_abs__second,
1668 /* 1650*/ CCD_ID_SMS__tp_vp_abs__tz_lsb,
1669 /* 1651*/ CCD_ID_SMS__tp_vp_abs__tz_sign,
1670 /* 1652*/ CCD_ID_SMS__tp_vp_abs__tz_msb,
1671 /* 1653*/ CCD_ID_SMS__tp_vp_enh__tp_ext,
1672 /* 1654*/ CCD_ID_SMS__tp_vp_enh__tp_ss,
1673 /* 1655*/ CCD_ID_SMS__tp_vp_enh__spare_0,
1674 /* 1656*/ CCD_ID_SMS__tp_vp_enh__tvpf,
1675 /* 1657*/ CCD_ID_SMS__tp_vp_enh__spare_1,
1676 /* 1658*/ CCD_ID_SMS__tp_vp_enh__tp_rsrvd,
1677 /* 1659*/ CCD_ID_SMS__tp_vp_enh__tp_vp_rel,
1678 /* 1660*/ CCD_ID_SMS__tp_vp_enh__tp_vp_sec,
1679 /* 1661*/ CCD_ID_SMS__tp_vp_enh__hour,
1680 /* 1662*/ CCD_ID_SMS__tp_vp_enh__minute,
1681 /* 1663*/ CCD_ID_SMS__tp_vp_enh__second,
1682 /* 1664*/ CCD_ID_SMS__tp_vp_enh__spare_2,
1683 /* 1665*/ CCD_ID_SMS__tp_vp_enh__spare_3,
1684 /* 1666*/ CCD_ID_SMS__tp_vp_enh__spare_4,
1685 /* 1667*/ CCD_ID_SMS__tp_vp_enh__spare_5,
1686 /* 1668*/ CCD_ID_SMS__tp_vp_enh__spare_6,
1687 /* 1669*/ CCD_ID_SMS__tp_ud__length,
1688 /* 1670*/ CCD_ID_SMS__tp_ud__data,
1689 /* 1671*/ CCD_ID_SMS__tp_udh_inc__length,
1690 /* 1672*/ CCD_ID_SMS__tp_udh_inc__tp_udh,
1691 /* 1673*/ CCD_ID_SMS__tp_udh_inc__data,
1692 /* 1674*/ CCD_ID_SMS__tp_cdh_inc__tp_udh,
1693 /* 1675*/ CCD_ID_SMS__tp_cdh_inc__data,
1694 /* 1676*/ CCD_ID_SMS__B_CP_ACK__msg_type,
1695 /* 1677*/ CCD_ID_SMS__D_CP_DATA__msg_type,
1696 /* 1678*/ CCD_ID_SMS__D_CP_DATA__cp_user_data_dl,
1697 /* 1679*/ CCD_ID_SMS__U_CP_DATA__msg_type,
1698 /* 1680*/ CCD_ID_SMS__U_CP_DATA__cp_user_data_ul,
1699 /* 1681*/ CCD_ID_SMS__B_CP_ERROR__msg_type,
1700 /* 1682*/ CCD_ID_SMS__B_CP_ERROR__cp_cause,
1701 /* 1683*/ CCD_ID_SMS__TP_DELIVER__tp_vt_mti,
1702 /* 1684*/ CCD_ID_SMS__TP_DELIVER__tp_rp,
1703 /* 1685*/ CCD_ID_SMS__TP_DELIVER__tp_udhi,
1704 /* 1686*/ CCD_ID_SMS__TP_DELIVER__tp_sri,
1705 /* 1687*/ CCD_ID_SMS__TP_DELIVER__spare_0,
1706 /* 1688*/ CCD_ID_SMS__TP_DELIVER__tp_mms,
1707 /* 1689*/ CCD_ID_SMS__TP_DELIVER__tp_mti,
1708 /* 1690*/ CCD_ID_SMS__TP_DELIVER__tp_oa,
1709 /* 1691*/ CCD_ID_SMS__TP_DELIVER__tp_pid,
1710 /* 1692*/ CCD_ID_SMS__TP_DELIVER__tp_dcs,
1711 /* 1693*/ CCD_ID_SMS__TP_DELIVER__tp_scts,
1712 /* 1694*/ CCD_ID_SMS__TP_DELIVER__tp_ud,
1713 /* 1695*/ CCD_ID_SMS__TP_DELIVER__tp_udh_inc,
1714 /* 1696*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_vt_mti,
1715 /* 1697*/ CCD_ID_SMS__TP_DLVR_REP_ERR__spare_0,
1716 /* 1698*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_udhi,
1717 /* 1699*/ CCD_ID_SMS__TP_DLVR_REP_ERR__spare_1,
1718 /* 1700*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_mti,
1719 /* 1701*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_fcs,
1720 /* 1702*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_ext,
1721 /* 1703*/ CCD_ID_SMS__TP_DLVR_REP_ERR__spare_2,
1722 /* 1704*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_udl_p,
1723 /* 1705*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_dcs_p,
1724 /* 1706*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_pid_p,
1725 /* 1707*/ CCD_ID_SMS__TP_DLVR_REP_ERR__spare_3,
1726 /* 1708*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_rsrvd,
1727 /* 1709*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_pid,
1728 /* 1710*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_dcs,
1729 /* 1711*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_ud,
1730 /* 1712*/ CCD_ID_SMS__TP_DLVR_REP_ERR__tp_udh_inc,
1731 /* 1713*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_vt_mti,
1732 /* 1714*/ CCD_ID_SMS__TP_DLVR_REP_ACK__spare_0,
1733 /* 1715*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_udhi,
1734 /* 1716*/ CCD_ID_SMS__TP_DLVR_REP_ACK__spare_1,
1735 /* 1717*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_mti,
1736 /* 1718*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_ext,
1737 /* 1719*/ CCD_ID_SMS__TP_DLVR_REP_ACK__spare_2,
1738 /* 1720*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_udl_p,
1739 /* 1721*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_dcs_p,
1740 /* 1722*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_pid_p,
1741 /* 1723*/ CCD_ID_SMS__TP_DLVR_REP_ACK__spare_3,
1742 /* 1724*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_rsrvd,
1743 /* 1725*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_pid,
1744 /* 1726*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_dcs,
1745 /* 1727*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_ud,
1746 /* 1728*/ CCD_ID_SMS__TP_DLVR_REP_ACK__tp_udh_inc,
1747 /* 1729*/ CCD_ID_SMS__TP_SUBMIT__tp_vt_mti,
1748 /* 1730*/ CCD_ID_SMS__TP_SUBMIT__tp_rp,
1749 /* 1731*/ CCD_ID_SMS__TP_SUBMIT__tp_udhi,
1750 /* 1732*/ CCD_ID_SMS__TP_SUBMIT__tp_srr,
1751 /* 1733*/ CCD_ID_SMS__TP_SUBMIT__tp_vpf,
1752 /* 1734*/ CCD_ID_SMS__TP_SUBMIT__tp_rd,
1753 /* 1735*/ CCD_ID_SMS__TP_SUBMIT__tp_mti,
1754 /* 1736*/ CCD_ID_SMS__TP_SUBMIT__tp_mr,
1755 /* 1737*/ CCD_ID_SMS__TP_SUBMIT__tp_da,
1756 /* 1738*/ CCD_ID_SMS__TP_SUBMIT__tp_pid,
1757 /* 1739*/ CCD_ID_SMS__TP_SUBMIT__tp_dcs,
1758 /* 1740*/ CCD_ID_SMS__TP_SUBMIT__tp_vp_enh,
1759 /* 1741*/ CCD_ID_SMS__TP_SUBMIT__tp_vp_rel,
1760 /* 1742*/ CCD_ID_SMS__TP_SUBMIT__tp_vp_abs,
1761 /* 1743*/ CCD_ID_SMS__TP_SUBMIT__tp_ud,
1762 /* 1744*/ CCD_ID_SMS__TP_SUBMIT__tp_udh_inc,
1763 /* 1745*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_vt_mti,
1764 /* 1746*/ CCD_ID_SMS__TP_SBMT_REP_ERR__spare_0,
1765 /* 1747*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_udhi,
1766 /* 1748*/ CCD_ID_SMS__TP_SBMT_REP_ERR__spare_1,
1767 /* 1749*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_mti,
1768 /* 1750*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_fcs,
1769 /* 1751*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_ext,
1770 /* 1752*/ CCD_ID_SMS__TP_SBMT_REP_ERR__spare_2,
1771 /* 1753*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_udl_p,
1772 /* 1754*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_dcs_p,
1773 /* 1755*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_pid_p,
1774 /* 1756*/ CCD_ID_SMS__TP_SBMT_REP_ERR__spare_3,
1775 /* 1757*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_rsrvd,
1776 /* 1758*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_scts,
1777 /* 1759*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_pid,
1778 /* 1760*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_dcs,
1779 /* 1761*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_ud,
1780 /* 1762*/ CCD_ID_SMS__TP_SBMT_REP_ERR__tp_udh_inc,
1781 /* 1763*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_vt_mti,
1782 /* 1764*/ CCD_ID_SMS__TP_SBMT_REP_ACK__spare_0,
1783 /* 1765*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_udhi,
1784 /* 1766*/ CCD_ID_SMS__TP_SBMT_REP_ACK__spare_1,
1785 /* 1767*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_mti,
1786 /* 1768*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_ext,
1787 /* 1769*/ CCD_ID_SMS__TP_SBMT_REP_ACK__spare_2,
1788 /* 1770*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_udl_p,
1789 /* 1771*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_dcs_p,
1790 /* 1772*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_pid_p,
1791 /* 1773*/ CCD_ID_SMS__TP_SBMT_REP_ACK__spare_3,
1792 /* 1774*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_rsrvd,
1793 /* 1775*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_scts,
1794 /* 1776*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_pid,
1795 /* 1777*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_dcs,
1796 /* 1778*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_ud,
1797 /* 1779*/ CCD_ID_SMS__TP_SBMT_REP_ACK__tp_udh_inc,
1798 /* 1780*/ CCD_ID_SMS__TP_STATUS__tp_vt_mti,
1799 /* 1781*/ CCD_ID_SMS__TP_STATUS__spare_0,
1800 /* 1782*/ CCD_ID_SMS__TP_STATUS__tp_udhi,
1801 /* 1783*/ CCD_ID_SMS__TP_STATUS__tp_srq,
1802 /* 1784*/ CCD_ID_SMS__TP_STATUS__spare_1,
1803 /* 1785*/ CCD_ID_SMS__TP_STATUS__tp_mms,
1804 /* 1786*/ CCD_ID_SMS__TP_STATUS__tp_mti,
1805 /* 1787*/ CCD_ID_SMS__TP_STATUS__tp_mr,
1806 /* 1788*/ CCD_ID_SMS__TP_STATUS__tp_ra,
1807 /* 1789*/ CCD_ID_SMS__TP_STATUS__tp_scts,
1808 /* 1790*/ CCD_ID_SMS__TP_STATUS__tp_dt,
1809 /* 1791*/ CCD_ID_SMS__TP_STATUS__tp_st,
1810 /* 1792*/ CCD_ID_SMS__TP_STATUS__spare_2,
1811 /* 1793*/ CCD_ID_SMS__TP_STATUS__tp_udl_p,
1812 /* 1794*/ CCD_ID_SMS__TP_STATUS__tp_dcs_p,
1813 /* 1795*/ CCD_ID_SMS__TP_STATUS__tp_pid_p,
1814 /* 1796*/ CCD_ID_SMS__TP_STATUS__tp_rsrvd,
1815 /* 1797*/ CCD_ID_SMS__TP_STATUS__tp_pid,
1816 /* 1798*/ CCD_ID_SMS__TP_STATUS__tp_dcs,
1817 /* 1799*/ CCD_ID_SMS__TP_STATUS__tp_ud,
1818 /* 1800*/ CCD_ID_SMS__TP_STATUS__tp_udh_inc,
1819 /* 1801*/ CCD_ID_SMS__TP_COMMAND__tp_vt_mti,
1820 /* 1802*/ CCD_ID_SMS__TP_COMMAND__spare_0,
1821 /* 1803*/ CCD_ID_SMS__TP_COMMAND__tp_udhi,
1822 /* 1804*/ CCD_ID_SMS__TP_COMMAND__tp_srr,
1823 /* 1805*/ CCD_ID_SMS__TP_COMMAND__spare_1,
1824 /* 1806*/ CCD_ID_SMS__TP_COMMAND__tp_mti,
1825 /* 1807*/ CCD_ID_SMS__TP_COMMAND__tp_mr,
1826 /* 1808*/ CCD_ID_SMS__TP_COMMAND__tp_pid,
1827 /* 1809*/ CCD_ID_SMS__TP_COMMAND__tp_ct,
1828 /* 1810*/ CCD_ID_SMS__TP_COMMAND__tp_mn,
1829 /* 1811*/ CCD_ID_SMS__TP_COMMAND__tp_da,
1830 /* 1812*/ CCD_ID_SMS__TP_COMMAND__tp_cd,
1831 /* 1813*/ CCD_ID_SMS__TP_COMMAND__tp_cdh_inc,
1832 /* 1814*/ CCD_ID_SMS__SIM_PDU__tp_vt_mti,
1833 /* 1815*/ CCD_ID_SMS__SIM_PDU__rp_addr,
1834 /* 1816*/ CCD_ID_SMS__SIM_PDU__tp_mti,
1835 /* 1817*/ CCD_ID_SMS__SIM_PDU__tpdu,
1836 /* 1818*/ CCD_ID_FAC__inv_comp__inv_id,
1837 /* 1819*/ CCD_ID_FAC__inv_comp__lnk_id,
1838 /* 1820*/ CCD_ID_FAC__inv_comp__op_code,
1839 /* 1821*/ CCD_ID_FAC__inv_comp__params,
1840 /* 1822*/ CCD_ID_FAC__err_comp__inv_id,
1841 /* 1823*/ CCD_ID_FAC__err_comp__err_code,
1842 /* 1824*/ CCD_ID_FAC__err_comp__params,
1843 /* 1825*/ CCD_ID_FAC__rej_comp__inv_id,
1844 /* 1826*/ CCD_ID_FAC__rej_comp__gen_problem,
1845 /* 1827*/ CCD_ID_FAC__rej_comp__inv_problem,
1846 /* 1828*/ CCD_ID_FAC__rej_comp__res_problem,
1847 /* 1829*/ CCD_ID_FAC__rej_comp__err_problem,
1848 /* 1830*/ CCD_ID_FAC__sequence__op_code,
1849 /* 1831*/ CCD_ID_FAC__sequence__params,
1850 /* 1832*/ CCD_ID_FAC__res_comp__inv_id,
1851 /* 1833*/ CCD_ID_FAC__res_comp__sequence,
1852 /* 1834*/ CCD_ID_FAC__forwardedToNumber__noa,
1853 /* 1835*/ CCD_ID_FAC__forwardedToNumber__npi,
1854 /* 1836*/ CCD_ID_FAC__forwardedToNumber__bcdDigit,
1855 /* 1837*/ CCD_ID_FAC__forwardedToSubaddress__tos,
1856 /* 1838*/ CCD_ID_FAC__forwardedToSubaddress__oei,
1857 /* 1839*/ CCD_ID_FAC__forwardedToSubaddress__spare_0,
1858 /* 1840*/ CCD_ID_FAC__forwardedToSubaddress__subadr_str,
1859 /* 1841*/ CCD_ID_FAC__basicService__bearerService,
1860 /* 1842*/ CCD_ID_FAC__basicService__teleservice,
1861 /* 1843*/ CCD_ID_FAC__ssForBS__ssCode,
1862 /* 1844*/ CCD_ID_FAC__ssForBS__basicService,
1863 /* 1845*/ CCD_ID_FAC__registerSSArg__ssCode,
1864 /* 1846*/ CCD_ID_FAC__registerSSArg__basicService,
1865 /* 1847*/ CCD_ID_FAC__registerSSArg__forwardedToNumber,
1866 /* 1848*/ CCD_ID_FAC__registerSSArg__forwardedToSubaddress,
1867 /* 1849*/ CCD_ID_FAC__registerSSArg__noReplyConditionTime,
1868 /* 1850*/ CCD_ID_FAC__registerSSArg__defaultPriority,
1869 /* 1851*/ CCD_ID_FAC__cbf__basicService,
1870 /* 1852*/ CCD_ID_FAC__cbf__ssStatus,
1871 /* 1853*/ CCD_ID_FAC__callBarringFeatureList__cbf,
1872 /* 1854*/ CCD_ID_FAC__callBarringInfo__ssCode,
1873 /* 1855*/ CCD_ID_FAC__callBarringInfo__callBarringFeatureList,
1874 /* 1856*/ CCD_ID_FAC__cugf__basicService,
1875 /* 1857*/ CCD_ID_FAC__cugf__preferentialCugIndicator,
1876 /* 1858*/ CCD_ID_FAC__cugf__interCugRestrictions,
1877 /* 1859*/ CCD_ID_FAC__cugFeatureList__cugf,
1878 /* 1860*/ CCD_ID_FAC__forwardingOptions__notify_fwd_pty,
1879 /* 1861*/ CCD_ID_FAC__forwardingOptions__notify_clg_pty,
1880 /* 1862*/ CCD_ID_FAC__forwardingOptions__fwd_reason,
1881 /* 1863*/ CCD_ID_FAC__forwardingOptions__spare_0,
1882 /* 1864*/ CCD_ID_FAC__ff__basicService,
1883 /* 1865*/ CCD_ID_FAC__ff__ssStatus,
1884 /* 1866*/ CCD_ID_FAC__ff__forwardedToNumber,
1885 /* 1867*/ CCD_ID_FAC__ff__forwardedToSubaddress,
1886 /* 1868*/ CCD_ID_FAC__ff__forwardingOptions,
1887 /* 1869*/ CCD_ID_FAC__ff__noReplyConditionTime,
1888 /* 1870*/ CCD_ID_FAC__forwardingFeatureList__ff,
1889 /* 1871*/ CCD_ID_FAC__forwardingInfo__ssCode,
1890 /* 1872*/ CCD_ID_FAC__forwardingInfo__forwardingFeatureList,
1891 /* 1873*/ CCD_ID_FAC__ssSubscriptionOption__cliRestrictionOption,
1892 /* 1874*/ CCD_ID_FAC__ssSubscriptionOption__overrideCategory,
1893 /* 1875*/ CCD_ID_FAC__ssNotification__spare_0,
1894 /* 1876*/ CCD_ID_FAC__ssNotification__clgSubscriber,
1895 /* 1877*/ CCD_ID_FAC__ssNotification__fwgSubscriber,
1896 /* 1878*/ CCD_ID_FAC__ssNotification__fwdSubscriber,
1897 /* 1879*/ CCD_ID_FAC__ssIncompatibilityCause__ssCode,
1898 /* 1880*/ CCD_ID_FAC__ssIncompatibilityCause__basicService,
1899 /* 1881*/ CCD_ID_FAC__ssIncompatibilityCause__ssStatus,
1900 /* 1882*/ CCD_ID_FAC__presentationAllowedAddress__partyNumber,
1901 /* 1883*/ CCD_ID_FAC__presentationAllowedAddress__partySubaddress,
1902 /* 1884*/ CCD_ID_FAC__rdn__presentationAllowedAddress,
1903 /* 1885*/ CCD_ID_FAC__rdn__presentationRestricted,
1904 /* 1886*/ CCD_ID_FAC__rdn__numberNotAvailableDueToInterworking,
1905 /* 1887*/ CCD_ID_FAC__rdn__presentationRestrictedAddress,
1906 /* 1888*/ CCD_ID_FAC__ectIndicator__ectCallState,
1907 /* 1889*/ CCD_ID_FAC__ectIndicator__rdn,
1908 /* 1890*/ CCD_ID_FAC__ussdRes__ussdDataCodingScheme,
1909 /* 1891*/ CCD_ID_FAC__ussdRes__ussdString,
1910 /* 1892*/ CCD_ID_FAC__forwardCUGInfoArg__cugIndex,
1911 /* 1893*/ CCD_ID_FAC__forwardCUGInfoArg__suppressPrefCUG,
1912 /* 1894*/ CCD_ID_FAC__forwardCUGInfoArg__suppressOA,
1913 /* 1895*/ CCD_ID_FAC__newPassword__digit,
1914 /* 1896*/ CCD_ID_FAC__e1__e_val,
1915 /* 1897*/ CCD_ID_FAC__chargingInformation__e1,
1916 /* 1898*/ CCD_ID_FAC__chargingInformation__e2,
1917 /* 1899*/ CCD_ID_FAC__chargingInformation__e3,
1918 /* 1900*/ CCD_ID_FAC__chargingInformation__e4,
1919 /* 1901*/ CCD_ID_FAC__chargingInformation__e5,
1920 /* 1902*/ CCD_ID_FAC__chargingInformation__e6,
1921 /* 1903*/ CCD_ID_FAC__chargingInformation__e7,
1922 /* 1904*/ CCD_ID_FAC__forwardChargeAdviceArg__ssCode,
1923 /* 1905*/ CCD_ID_FAC__forwardChargeAdviceArg__chargingInformation,
1924 /* 1906*/ CCD_ID_FAC__rej_comp_sat__inv_id,
1925 /* 1907*/ CCD_ID_FAC__rej_comp_sat__rej_params_sat,
1926 /* 1908*/ CCD_ID_FAC__err_desc_sat__err_params_sat,
1927 /* 1909*/ CCD_ID_FAC__err_comp_sat__inv_id,
1928 /* 1910*/ CCD_ID_FAC__err_comp_sat__err_desc_sat,
1929 /* 1911*/ CCD_ID_FAC__res_desc_sat__res_params_sat,
1930 /* 1912*/ CCD_ID_FAC__seq_sat__res_desc_sat,
1931 /* 1913*/ CCD_ID_FAC__res_comp_sat__inv_id,
1932 /* 1914*/ CCD_ID_FAC__res_comp_sat__seq_sat,
1933 /* 1915*/ CCD_ID_FAC__ccbsf__ccbsIndex,
1934 /* 1916*/ CCD_ID_FAC__ccbsf__b_subscriberNumber,
1935 /* 1917*/ CCD_ID_FAC__ccbsf__b_subscriberSubaddress,
1936 /* 1918*/ CCD_ID_FAC__ccbsf__basicServiceGroup,
1937 /* 1919*/ CCD_ID_FAC__ccbsFeatureList__ccbsf,
1938 /* 1920*/ CCD_ID_FAC__cliRestrictionInfo__ssStatus,
1939 /* 1921*/ CCD_ID_FAC__cliRestrictionInfo__cliRestrictionOption,
1940 /* 1922*/ CCD_ID_FAC__cliRestrictionInfo__maxEntitledPriority,
1941 /* 1923*/ CCD_ID_FAC__cliRestrictionInfo__defaultPriority,
1942 /* 1924*/ CCD_ID_FAC__cliRestrictionInfo__ccbsFeatureList,
1943 /* 1925*/ CCD_ID_FAC__namePresentationAllowed__dataCodingScheme,
1944 /* 1926*/ CCD_ID_FAC__namePresentationAllowed__lengthInCharacters,
1945 /* 1927*/ CCD_ID_FAC__namePresentationAllowed__nameString,
1946 /* 1928*/ CCD_ID_FAC__ussdArg__ussdDataCodingScheme,
1947 /* 1929*/ CCD_ID_FAC__ussdArg__ussdString,
1948 /* 1930*/ CCD_ID_FAC__ussdArg__alertingPattern,
1949 /* 1931*/ CCD_ID_FAC__ussdArg__msisdn,
1950 /* 1932*/ CCD_ID_FAC__eraseCCEntryArg__ssCode,
1951 /* 1933*/ CCD_ID_FAC__eraseCCEntryArg__ccbsIndex,
1952 /* 1934*/ CCD_ID_FAC__eraseCCEntryRes__ssCode,
1953 /* 1935*/ CCD_ID_FAC__eraseCCEntryRes__ssStatus,
1954 /* 1936*/ CCD_ID_FAC__accRegisterCCEntryRes__ccbsf,
1955 /* 1937*/ CCD_ID_FAC__callDeflectionArg__deflectedToNumber,
1956 /* 1938*/ CCD_ID_FAC__callDeflectionArg__deflectedToSubaddress,
1957 /* 1939*/ CCD_ID_FAC__userUserServiceArg__uusService,
1958 /* 1940*/ CCD_ID_FAC__userUserServiceArg__uusRequired,
1959 /* 1941*/ CCD_ID_FAC__privateExtensionList__extension,
1960 /* 1942*/ CCD_ID_FAC__extensionContainer__privateExtensionList,
1961 /* 1943*/ CCD_ID_FAC__extensionContainer__pcsExtension,
1962 /* 1944*/ CCD_ID_FAC__unknownSubscriberParam__extensionContainer,
1963 /* 1945*/ CCD_ID_FAC__unknownSubscriberParam__unknwnSubscrDiag,
1964 /* 1946*/ CCD_ID_FAC__illegalSubscriberParam__extensionContainer,
1965 /* 1947*/ CCD_ID_FAC__extCallBarredParam__callBarringCause,
1966 /* 1948*/ CCD_ID_FAC__extCallBarredParam__extensionContainer,
1967 /* 1949*/ CCD_ID_FAC__absentSubscriberParam__extensionContainer,
1968 /* 1950*/ CCD_ID_FAC__absentSubscriberParam__absentSubscriberReason,
1969 /* 1951*/ CCD_ID_FAC__extSystemFailureParam__networkResource,
1970 /* 1952*/ CCD_ID_FAC__extSystemFailureParam__extensionContainer,
1971 /* 1953*/ CCD_ID_FAC__callingName__namePresentationAllowed,
1972 /* 1954*/ CCD_ID_FAC__callingName__presentationRestricted,
1973 /* 1955*/ CCD_ID_FAC__callingName__nameUnavailable,
1974 /* 1956*/ CCD_ID_FAC__callingName__namePresentationRestricted,
1975 /* 1957*/ CCD_ID_FAC__nameIndicator__callingName,
1976 /* 1958*/ CCD_ID_FAC__notifySSArg__ssCode,
1977 /* 1959*/ CCD_ID_FAC__notifySSArg__ssStatus,
1978 /* 1960*/ CCD_ID_FAC__notifySSArg__ssNotification,
1979 /* 1961*/ CCD_ID_FAC__notifySSArg__callIsWaitingIndicator,
1980 /* 1962*/ CCD_ID_FAC__notifySSArg__callOnHoldIndicator,
1981 /* 1963*/ CCD_ID_FAC__notifySSArg__mptyIndicator,
1982 /* 1964*/ CCD_ID_FAC__notifySSArg__cugIndex,
1983 /* 1965*/ CCD_ID_FAC__notifySSArg__clirSuppressionRejected,
1984 /* 1966*/ CCD_ID_FAC__notifySSArg__ectIndicator,
1985 /* 1967*/ CCD_ID_FAC__notifySSArg__nameIndicator,
1986 /* 1968*/ CCD_ID_FAC__notifySSArg__ccbsf,
1987 /* 1969*/ CCD_ID_FAC__notifySSArg__alertingPattern,
1988 /* 1970*/ CCD_ID_FAC__basicServiceGroupList_value__bearerService,
1989 /* 1971*/ CCD_ID_FAC__basicServiceGroupList_value__teleservice,
1990 /* 1972*/ CCD_ID_FAC__basicServiceGroupList__basicServiceGroupList_value,
1991 /* 1973*/ CCD_ID_FAC__interrogateSSRes__ssStatus,
1992 /* 1974*/ CCD_ID_FAC__interrogateSSRes__forwardedToNumber,
1993 /* 1975*/ CCD_ID_FAC__interrogateSSRes__basicServiceGroupList,
1994 /* 1976*/ CCD_ID_FAC__interrogateSSRes__forwardingFeatureList,
1995 /* 1977*/ CCD_ID_FAC__interrogateSSRes__cliRestrictionInfo,
1996 /* 1978*/ CCD_ID_FAC__cugs__cugIndex,
1997 /* 1979*/ CCD_ID_FAC__cugs__cugInterlock,
1998 /* 1980*/ CCD_ID_FAC__cugs__intraCugOptions,
1999 /* 1981*/ CCD_ID_FAC__cugs__basicServiceGroupList,
2000 /* 1982*/ CCD_ID_FAC__cugSubscriptionList__cugs,
2001 /* 1983*/ CCD_ID_FAC__cugInfo__cugSubscriptionList,
2002 /* 1984*/ CCD_ID_FAC__cugInfo__cugFeatureList,
2003 /* 1985*/ CCD_ID_FAC__ssData__ssCode,
2004 /* 1986*/ CCD_ID_FAC__ssData__ssStatus,
2005 /* 1987*/ CCD_ID_FAC__ssData__ssSubscriptionOption,
2006 /* 1988*/ CCD_ID_FAC__ssData__basicServiceGroupList,
2007 /* 1989*/ CCD_ID_FAC__ssData__defaultPriority,
2008 /* 1990*/ CCD_ID_FAC__ssInfo__forwardingInfo,
2009 /* 1991*/ CCD_ID_FAC__ssInfo__callBarringInfo,
2010 /* 1992*/ CCD_ID_FAC__ssInfo__cugInfo,
2011 /* 1993*/ CCD_ID_FAC__ssInfo__ssData,
2012 /* 1994*/ CCD_ID_FAC__COMPONENT__msg_type,
2013 /* 1995*/ CCD_ID_FAC__COMPONENT__inv_comp,
2014 /* 1996*/ CCD_ID_FAC__COMPONENT__res_comp,
2015 /* 1997*/ CCD_ID_FAC__COMPONENT__err_comp,
2016 /* 1998*/ CCD_ID_FAC__COMPONENT__rej_comp,
2017 /* 1999*/ CCD_ID_FAC__REGISTER_SS_INV__msg_type,
2018 /* 2000*/ CCD_ID_FAC__REGISTER_SS_INV__registerSSArg,
2019 /* 2001*/ CCD_ID_FAC__REGISTER_SS_RES__msg_type,
2020 /* 2002*/ CCD_ID_FAC__REGISTER_SS_RES__ssInfo,
2021 /* 2003*/ CCD_ID_FAC__ERASE_SS_INV__msg_type,
2022 /* 2004*/ CCD_ID_FAC__ERASE_SS_INV__ssForBS,
2023 /* 2005*/ CCD_ID_FAC__ERASE_SS_RES__msg_type,
2024 /* 2006*/ CCD_ID_FAC__ERASE_SS_RES__ssInfo,
2025 /* 2007*/ CCD_ID_FAC__ACTIVATE_SS_INV__msg_type,
2026 /* 2008*/ CCD_ID_FAC__ACTIVATE_SS_INV__ssForBS,
2027 /* 2009*/ CCD_ID_FAC__ACTIVATE_SS_RES__msg_type,
2028 /* 2010*/ CCD_ID_FAC__ACTIVATE_SS_RES__ssInfo,
2029 /* 2011*/ CCD_ID_FAC__DEACTIVATE_SS_INV__msg_type,
2030 /* 2012*/ CCD_ID_FAC__DEACTIVATE_SS_INV__ssForBS,
2031 /* 2013*/ CCD_ID_FAC__DEACTIVATE_SS_RES__msg_type,
2032 /* 2014*/ CCD_ID_FAC__DEACTIVATE_SS_RES__ssInfo,
2033 /* 2015*/ CCD_ID_FAC__INTERROGATE_SS_INV__msg_type,
2034 /* 2016*/ CCD_ID_FAC__INTERROGATE_SS_INV__ssForBS,
2035 /* 2017*/ CCD_ID_FAC__INTERROGATE_SS_RES__msg_type,
2036 /* 2018*/ CCD_ID_FAC__INTERROGATE_SS_RES__interrogateSSRes,
2037 /* 2019*/ CCD_ID_FAC__NOTIFY_SS_INV__msg_type,
2038 /* 2020*/ CCD_ID_FAC__NOTIFY_SS_INV__notifySSArg,
2039 /* 2021*/ CCD_ID_FAC__REGISTER_PWD_INV__msg_type,
2040 /* 2022*/ CCD_ID_FAC__REGISTER_PWD_INV__ssCode,
2041 /* 2023*/ CCD_ID_FAC__REGISTER_PWD_RES__msg_type,
2042 /* 2024*/ CCD_ID_FAC__REGISTER_PWD_RES__newPassword,
2043 /* 2025*/ CCD_ID_FAC__GET_PWD_INV__msg_type,
2044 /* 2026*/ CCD_ID_FAC__GET_PWD_INV__guidanceInfo,
2045 /* 2027*/ CCD_ID_FAC__GET_PWD_RES__msg_type,
2046 /* 2028*/ CCD_ID_FAC__GET_PWD_RES__currPassword,
2047 /* 2029*/ CCD_ID_FAC__PROCESS_USSD_INV__msg_type,
2048 /* 2030*/ CCD_ID_FAC__PROCESS_USSD_INV__ssUserData,
2049 /* 2031*/ CCD_ID_FAC__PROCESS_USSD_RES__msg_type,
2050 /* 2032*/ CCD_ID_FAC__PROCESS_USSD_RES__ssUserData,
2051 /* 2033*/ CCD_ID_FAC__PROCESS_USSD_REQ_INV__msg_type,
2052 /* 2034*/ CCD_ID_FAC__PROCESS_USSD_REQ_INV__ussdArg,
2053 /* 2035*/ CCD_ID_FAC__PROCESS_USSD_REQ_RES__msg_type,
2054 /* 2036*/ CCD_ID_FAC__PROCESS_USSD_REQ_RES__ussdRes,
2055 /* 2037*/ CCD_ID_FAC__USSD_REQ_INV__msg_type,
2056 /* 2038*/ CCD_ID_FAC__USSD_REQ_INV__ussdArg,
2057 /* 2039*/ CCD_ID_FAC__USSD_REQ_RES__msg_type,
2058 /* 2040*/ CCD_ID_FAC__USSD_REQ_RES__ussdRes,
2059 /* 2041*/ CCD_ID_FAC__USSD_NOTIFY_INV__msg_type,
2060 /* 2042*/ CCD_ID_FAC__USSD_NOTIFY_INV__ussdArg,
2061 /* 2043*/ CCD_ID_FAC__FWD_CUG_INFO_INV__msg_type,
2062 /* 2044*/ CCD_ID_FAC__FWD_CUG_INFO_INV__forwardCUGInfoArg,
2063 /* 2045*/ CCD_ID_FAC__SPLIT_MPTY_RES__msg_type,
2064 /* 2046*/ CCD_ID_FAC__SPLIT_MPTY_RES__zzzzEmpty,
2065 /* 2047*/ CCD_ID_FAC__RETRIEVE_MPTY_RES__msg_type,
2066 /* 2048*/ CCD_ID_FAC__RETRIEVE_MPTY_RES__zzzzEmpty,
2067 /* 2049*/ CCD_ID_FAC__HOLD_MPTY_RES__msg_type,
2068 /* 2050*/ CCD_ID_FAC__HOLD_MPTY_RES__zzzzEmpty,
2069 /* 2051*/ CCD_ID_FAC__BUILD_MPTY_RES__msg_type,
2070 /* 2052*/ CCD_ID_FAC__BUILD_MPTY_RES__zzzzEmpty,
2071 /* 2053*/ CCD_ID_FAC__FWD_CHG_ADVICE_INV__msg_type,
2072 /* 2054*/ CCD_ID_FAC__FWD_CHG_ADVICE_INV__forwardChargeAdviceArg,
2073 /* 2055*/ CCD_ID_FAC__FWD_CHG_ADVICE_RES__msg_type,
2074 /* 2056*/ CCD_ID_FAC__FWD_CHG_ADVICE_RES__zzzzEmpty,
2075 /* 2057*/ CCD_ID_FAC__COMP_SAT__msg_type,
2076 /* 2058*/ CCD_ID_FAC__COMP_SAT__res_comp_sat,
2077 /* 2059*/ CCD_ID_FAC__COMP_SAT__err_comp_sat,
2078 /* 2060*/ CCD_ID_FAC__COMP_SAT__rej_comp_sat,
2079 /* 2061*/ CCD_ID_FAC__ERASE_CC_ENTRY_INV__msg_type,
2080 /* 2062*/ CCD_ID_FAC__ERASE_CC_ENTRY_INV__eraseCCEntryArg,
2081 /* 2063*/ CCD_ID_FAC__ERASE_CC_ENTRY_RES__msg_type,
2082 /* 2064*/ CCD_ID_FAC__ERASE_CC_ENTRY_RES__eraseCCEntryRes,
2083 /* 2065*/ CCD_ID_FAC__ACC_REGISTER_CC_ENTRY_INV__msg_type,
2084 /* 2066*/ CCD_ID_FAC__ACC_REGISTER_CC_ENTRY_INV__accRegisterCCEntryArg,
2085 /* 2067*/ CCD_ID_FAC__ACC_REGISTER_CC_ENTRY_RES__msg_type,
2086 /* 2068*/ CCD_ID_FAC__ACC_REGISTER_CC_ENTRY_RES__accRegisterCCEntryRes,
2087 /* 2069*/ CCD_ID_FAC__CALL_DEFLECTION_INV__msg_type,
2088 /* 2070*/ CCD_ID_FAC__CALL_DEFLECTION_INV__callDeflectionArg,
2089 /* 2071*/ CCD_ID_FAC__USER_USER_SRV_INV__msg_type,
2090 /* 2072*/ CCD_ID_FAC__USER_USER_SRV_INV__userUserServiceArg,
2091 /* 2073*/ CCD_ID_FAC__UNKNOWN_SUBSCRIBER_ERR__msg_type,
2092 /* 2074*/ CCD_ID_FAC__UNKNOWN_SUBSCRIBER_ERR__unknownSubscriberParam,
2093 /* 2075*/ CCD_ID_FAC__ILLEGAL_SUBSCRIBER_ERR__msg_type,
2094 /* 2076*/ CCD_ID_FAC__ILLEGAL_SUBSCRIBER_ERR__illegalSubscriberParam,
2095 /* 2077*/ CCD_ID_FAC__BEARER_SERV_NOT_PROV_ERR__msg_type,
2096 /* 2078*/ CCD_ID_FAC__BEARER_SERV_NOT_PROV_ERR__bearerServNotProvParam,
2097 /* 2079*/ CCD_ID_FAC__TELE_SERV_NOT_PROV_ERR__msg_type,
2098 /* 2080*/ CCD_ID_FAC__TELE_SERV_NOT_PROV_ERR__teleServNotProvParam,
2099 /* 2081*/ CCD_ID_FAC__ILLEGAL_EQUIPMENT_ERR__msg_type,
2100 /* 2082*/ CCD_ID_FAC__ILLEGAL_EQUIPMENT_ERR__teleServNotProvParam,
2101 /* 2083*/ CCD_ID_FAC__CALL_BARRED_ERR__msg_type,
2102 /* 2084*/ CCD_ID_FAC__CALL_BARRED_ERR__callBarringCause,
2103 /* 2085*/ CCD_ID_FAC__CALL_BARRED_ERR__extCallBarredParam,
2104 /* 2086*/ CCD_ID_FAC__SS_INCOMPATIBILITY_ERR__msg_type,
2105 /* 2087*/ CCD_ID_FAC__SS_INCOMPATIBILITY_ERR__ssIncompatibilityCause,
2106 /* 2088*/ CCD_ID_FAC__FACILITY_NOT_SUPPORTED_ERR__msg_type,
2107 /* 2089*/ CCD_ID_FAC__FACILITY_NOT_SUPPORTED_ERR__facilityNotSupParam,
2108 /* 2090*/ CCD_ID_FAC__ABSENT_SUBSCRIBER_ERR__msg_type,
2109 /* 2091*/ CCD_ID_FAC__ABSENT_SUBSCRIBER_ERR__absentSubscriberParam,
2110 /* 2092*/ CCD_ID_FAC__SYSTEM_FAILURE_ERR__msg_type,
2111 /* 2093*/ CCD_ID_FAC__SYSTEM_FAILURE_ERR__networkResource,
2112 /* 2094*/ CCD_ID_FAC__SYSTEM_FAILURE_ERR__extSystemFailureParam,
2113 /* 2095*/ CCD_ID_FAC__DATA_MISSING_ERR__msg_type,
2114 /* 2096*/ CCD_ID_FAC__DATA_MISSING_ERR__dataMissingParam,
2115 /* 2097*/ CCD_ID_FAC__UNEXPECTED_DATA_VALUE_ERR__msg_type,
2116 /* 2098*/ CCD_ID_FAC__UNEXPECTED_DATA_VALUE_ERR__unexpectedDataParam,
2117 /* 2099*/ CCD_ID_FAC__SS_ERROR_STATUS_ERR__msg_type,
2118 /* 2100*/ CCD_ID_FAC__SS_ERROR_STATUS_ERR__ssStatus,
2119 /* 2101*/ CCD_ID_FAC__PW_REGISTRATION_FAILURE_ERR__msg_type,
2120 /* 2102*/ CCD_ID_FAC__PW_REGISTRATION_FAILURE_ERR__pwRegistrationFailureCause,
2121 /* 2103*/ CCD_ID_SAT__cmd_details__cmd_nr,
2122 /* 2104*/ CCD_ID_SAT__cmd_details__cmd_typ,
2123 /* 2105*/ CCD_ID_SAT__cmd_details__cmd_qlf,
2124 /* 2106*/ CCD_ID_SAT__dev_ids__src_dev,
2125 /* 2107*/ CCD_ID_SAT__dev_ids__dest_dev,
2126 /* 2108*/ CCD_ID_SAT__pas_cmd__cmd_details,
2127 /* 2109*/ CCD_ID_SAT__pas_cmd__dev_ids,
2128 /* 2110*/ CCD_ID_SAT__pas_cmd__cmd_prms,
2129 /* 2111*/ CCD_ID_SAT__ss_string__noa,
2130 /* 2112*/ CCD_ID_SAT__ss_string__npi,
2131 /* 2113*/ CCD_ID_SAT__ss_string__ss_ctrl_string,
2132 /* 2114*/ CCD_ID_SAT__addr__noa,
2133 /* 2115*/ CCD_ID_SAT__addr__npi,
2134 /* 2116*/ CCD_ID_SAT__addr__bcdDigit,
2135 /* 2117*/ CCD_ID_SAT__subaddr__tos,
2136 /* 2118*/ CCD_ID_SAT__subaddr__oei,
2137 /* 2119*/ CCD_ID_SAT__subaddr__spare_0,
2138 /* 2120*/ CCD_ID_SAT__subaddr__subadr_str,
2139 /* 2121*/ CCD_ID_SAT__res__gen,
2140 /* 2122*/ CCD_ID_SAT__res__add,
2141 /* 2123*/ CCD_ID_SAT__text__dcs,
2142 /* 2124*/ CCD_ID_SAT__text__text_str,
2143 /* 2125*/ CCD_ID_SAT__item_id__item,
2144 /* 2126*/ CCD_ID_SAT__cc_smc_loc_info__mnc_mcc,
2145 /* 2127*/ CCD_ID_SAT__cc_smc_loc_info__lac,
2146 /* 2128*/ CCD_ID_SAT__cc_smc_loc_info__cid,
2147 /* 2129*/ CCD_ID_SAT__cbd_cmd__dev_ids,
2148 /* 2130*/ CCD_ID_SAT__cbd_cmd__cb_page,
2149 /* 2131*/ CCD_ID_SAT__dur__time_unit,
2150 /* 2132*/ CCD_ID_SAT__dur__time_ivl,
2151 /* 2133*/ CCD_ID_SAT__ussd_string__dcs,
2152 /* 2134*/ CCD_ID_SAT__ussd_string__ussd_str,
2153 /* 2135*/ CCD_ID_SAT__ccr_allw__addr,
2154 /* 2136*/ CCD_ID_SAT__ccr_allw__ss_string,
2155 /* 2137*/ CCD_ID_SAT__ccr_allw__ussd_string,
2156 /* 2138*/ CCD_ID_SAT__ccr_allw__cap_cnf_parms,
2157 /* 2139*/ CCD_ID_SAT__ccr_allw__subaddr,
2158 /* 2140*/ CCD_ID_SAT__ccr_allw__alpha_id,
2159 /* 2141*/ CCD_ID_SAT__ccr_allw__bc_rpi,
2160 /* 2142*/ CCD_ID_SAT__ccr_allw__cap_cnf_parms_2,
2161 /* 2143*/ CCD_ID_SAT__cc_cmd__dev_ids,
2162 /* 2144*/ CCD_ID_SAT__cc_cmd__addr,
2163 /* 2145*/ CCD_ID_SAT__cc_cmd__ss_string,
2164 /* 2146*/ CCD_ID_SAT__cc_cmd__ussd_string,
2165 /* 2147*/ CCD_ID_SAT__cc_cmd__cap_cnf_parms,
2166 /* 2148*/ CCD_ID_SAT__cc_cmd__subaddr,
2167 /* 2149*/ CCD_ID_SAT__cc_cmd__cc_smc_loc_info,
2168 /* 2150*/ CCD_ID_SAT__cc_cmd__cap_cnf_parms_2,
2169 /* 2151*/ CCD_ID_SAT__smpdu__tpdu_data,
2170 /* 2152*/ CCD_ID_SAT__icon__icon_qu,
2171 /* 2153*/ CCD_ID_SAT__icon__icon_id,
2172 /* 2154*/ CCD_ID_SAT__ev_list__event,
2173 /* 2155*/ CCD_ID_SAT__dtmf_string__bcdDigit,
2174 /* 2156*/ CCD_ID_SAT__ti_oct__ti,
2175 /* 2157*/ CCD_ID_SAT__ti_oct__spare_0,
2176 /* 2158*/ CCD_ID_SAT__ti_list__ti_oct,
2177 /* 2159*/ CCD_ID_SAT__cause__cs,
2178 /* 2160*/ CCD_ID_SAT__sm_addr__noa,
2179 /* 2161*/ CCD_ID_SAT__sm_addr__npi,
2180 /* 2162*/ CCD_ID_SAT__sm_addr__bcdDigit,
2181 /* 2163*/ CCD_ID_SAT__smc_cmd__dev_ids,
2182 /* 2164*/ CCD_ID_SAT__smc_cmd__sm_addr,
2183 /* 2165*/ CCD_ID_SAT__smc_cmd__sm_addr_2,
2184 /* 2166*/ CCD_ID_SAT__smc_cmd__cc_smc_loc_info,
2185 /* 2167*/ CCD_ID_SAT__smcr_allw__sm_addr,
2186 /* 2168*/ CCD_ID_SAT__smcr_allw__sm_addr_2,
2187 /* 2169*/ CCD_ID_SAT__smcr_allw__alpha_id,
2188 /* 2170*/ CCD_ID_SAT__at_resp__text_str,
2189 /* 2171*/ CCD_ID_SAT__chan_data__ch_dat_str,
2190 /* 2172*/ CCD_ID_SAT__other_addr__oth_addr_type,
2191 /* 2173*/ CCD_ID_SAT__other_addr__ipv4_addr,
2192 /* 2174*/ CCD_ID_SAT__other_addr__ipv6_addr,
2193 /* 2175*/ CCD_ID_SAT__if_transp_lev__trans_prot_type,
2194 /* 2176*/ CCD_ID_SAT__if_transp_lev__port_number,
2195 /* 2177*/ CCD_ID_SAT__browser_id__browser,
2196 /* 2178*/ CCD_ID_SAT__url__url_value,
2197 /* 2179*/ CCD_ID_SAT__prov_file_ref__prov_file_id,
2198 /* 2180*/ CCD_ID_SAT__brows_term_cause__brows_term_s,
2199 /* 2181*/ CCD_ID_SAT__chan_stat__chan_stat_link,
2200 /* 2182*/ CCD_ID_SAT__chan_stat__chan_stat_inf1,
2201 /* 2183*/ CCD_ID_SAT__chan_stat__chan_id,
2202 /* 2184*/ CCD_ID_SAT__chan_stat__chan_stat_inf2,
2203 /* 2185*/ CCD_ID_SAT__evd_cmd__ev_list,
2204 /* 2186*/ CCD_ID_SAT__evd_cmd__dev_ids,
2205 /* 2187*/ CCD_ID_SAT__evd_cmd__ti_list,
2206 /* 2188*/ CCD_ID_SAT__evd_cmd__addr,
2207 /* 2189*/ CCD_ID_SAT__evd_cmd__subaddr,
2208 /* 2190*/ CCD_ID_SAT__evd_cmd__cause,
2209 /* 2191*/ CCD_ID_SAT__evd_cmd__loc_state,
2210 /* 2192*/ CCD_ID_SAT__evd_cmd__cc_smc_loc_info,
2211 /* 2193*/ CCD_ID_SAT__evd_cmd__brows_term_cause,
2212 /* 2194*/ CCD_ID_SAT__evd_cmd__chan_stat,
2213 /* 2195*/ CCD_ID_SAT__evd_cmd__chan_dat_lth,
2214 /* 2196*/ CCD_ID_SAT__csd_bear_prm__csd_speed,
2215 /* 2197*/ CCD_ID_SAT__csd_bear_prm__csd_name,
2216 /* 2198*/ CCD_ID_SAT__csd_bear_prm__csd_ce,
2217 /* 2199*/ CCD_ID_SAT__gprs_bear_prm__gprs_prec,
2218 /* 2200*/ CCD_ID_SAT__gprs_bear_prm__gprs_delay,
2219 /* 2201*/ CCD_ID_SAT__gprs_bear_prm__gprs_rely,
2220 /* 2202*/ CCD_ID_SAT__gprs_bear_prm__gprs_peak,
2221 /* 2203*/ CCD_ID_SAT__gprs_bear_prm__gprs_mean,
2222 /* 2204*/ CCD_ID_SAT__gprs_bear_prm__gprs_pdp_type,
2223 /* 2205*/ CCD_ID_SAT__bear_desc__bear_type,
2224 /* 2206*/ CCD_ID_SAT__bear_desc__csd_bear_prm,
2225 /* 2207*/ CCD_ID_SAT__bear_desc__gprs_bear_prm,
2226 /* 2208*/ CCD_ID_SAT__nan_buf__n_acc_name,
2227 /* 2209*/ CCD_ID_SAT__dtt__text_str,
2228 /* 2210*/ CCD_ID_SAT__lang__lang_buf,
2229 /* 2211*/ CCD_ID_SAT__STK_CMD__msg_type,
2230 /* 2212*/ CCD_ID_SAT__STK_CMD__pas_cmd,
2231 /* 2213*/ CCD_ID_SAT__SEND_SS__msg_type,
2232 /* 2214*/ CCD_ID_SAT__SEND_SS__alpha_id,
2233 /* 2215*/ CCD_ID_SAT__SEND_SS__ss_string,
2234 /* 2216*/ CCD_ID_SAT__SEND_SS__icon,
2235 /* 2217*/ CCD_ID_SAT__SETUP_CALL__msg_type,
2236 /* 2218*/ CCD_ID_SAT__SETUP_CALL__alpha_id,
2237 /* 2219*/ CCD_ID_SAT__SETUP_CALL__addr,
2238 /* 2220*/ CCD_ID_SAT__SETUP_CALL__cap_cnf_parms,
2239 /* 2221*/ CCD_ID_SAT__SETUP_CALL__subaddr,
2240 /* 2222*/ CCD_ID_SAT__SETUP_CALL__dur,
2241 /* 2223*/ CCD_ID_SAT__SETUP_CALL__icon,
2242 /* 2224*/ CCD_ID_SAT__SETUP_CALL__alpha_id_2,
2243 /* 2225*/ CCD_ID_SAT__SETUP_CALL__icon_2,
2244 /* 2226*/ CCD_ID_SAT__SEND_SM__msg_type,
2245 /* 2227*/ CCD_ID_SAT__SEND_SM__alpha_id,
2246 /* 2228*/ CCD_ID_SAT__SEND_SM__addr,
2247 /* 2229*/ CCD_ID_SAT__SEND_SM__smpdu,
2248 /* 2230*/ CCD_ID_SAT__SEND_SM__icon,
2249 /* 2231*/ CCD_ID_SAT__SEND_USSD__msg_type,
2250 /* 2232*/ CCD_ID_SAT__SEND_USSD__alpha_id,
2251 /* 2233*/ CCD_ID_SAT__SEND_USSD__ussd_string,
2252 /* 2234*/ CCD_ID_SAT__SEND_USSD__icon,
2253 /* 2235*/ CCD_ID_SAT__SEND_DTMF__msg_type,
2254 /* 2236*/ CCD_ID_SAT__SEND_DTMF__alpha_id,
2255 /* 2237*/ CCD_ID_SAT__SEND_DTMF__dtmf_string,
2256 /* 2238*/ CCD_ID_SAT__SEND_DTMF__icon,
2257 /* 2239*/ CCD_ID_SAT__SETUP_EVENT__msg_type,
2258 /* 2240*/ CCD_ID_SAT__SETUP_EVENT__ev_list,
2259 /* 2241*/ CCD_ID_SAT__TERM_RESP__msg_type,
2260 /* 2242*/ CCD_ID_SAT__TERM_RESP__cmd_details,
2261 /* 2243*/ CCD_ID_SAT__TERM_RESP__dev_ids,
2262 /* 2244*/ CCD_ID_SAT__TERM_RESP__res,
2263 /* 2245*/ CCD_ID_SAT__TERM_RESP__dur,
2264 /* 2246*/ CCD_ID_SAT__TERM_RESP__text,
2265 /* 2247*/ CCD_ID_SAT__TERM_RESP__item_id,
2266 /* 2248*/ CCD_ID_SAT__TERM_RESP__cc_smc_loc_info,
2267 /* 2249*/ CCD_ID_SAT__TERM_RESP__imei,
2268 /* 2250*/ CCD_ID_SAT__TERM_RESP__ntw_msr_res,
2269 /* 2251*/ CCD_ID_SAT__TERM_RESP__bcch_list,
2270 /* 2252*/ CCD_ID_SAT__TERM_RESP__dtt,
2271 /* 2253*/ CCD_ID_SAT__TERM_RESP__cc_req_act,
2272 /* 2254*/ CCD_ID_SAT__TERM_RESP__res_2,
2273 /* 2255*/ CCD_ID_SAT__TERM_RESP__at_resp,
2274 /* 2256*/ CCD_ID_SAT__TERM_RESP__chan_data,
2275 /* 2257*/ CCD_ID_SAT__TERM_RESP__chan_stat,
2276 /* 2258*/ CCD_ID_SAT__TERM_RESP__chan_dat_lth,
2277 /* 2259*/ CCD_ID_SAT__TERM_RESP__bear_desc,
2278 /* 2260*/ CCD_ID_SAT__TERM_RESP__buffer_size,
2279 /* 2261*/ CCD_ID_SAT__TERM_RESP__lang,
2280 /* 2262*/ CCD_ID_SAT__ENV_CMD__msg_type,
2281 /* 2263*/ CCD_ID_SAT__ENV_CMD__cbd_cmd,
2282 /* 2264*/ CCD_ID_SAT__ENV_CMD__cc_cmd,
2283 /* 2265*/ CCD_ID_SAT__ENV_CMD__smc_cmd,
2284 /* 2266*/ CCD_ID_SAT__ENV_CMD__evd_cmd,
2285 /* 2267*/ CCD_ID_SAT__ENV_RES__msg_type,
2286 /* 2268*/ CCD_ID_SAT__ENV_RES__ccr_allw,
2287 /* 2269*/ CCD_ID_SAT__ENV_RES__ccr_not_allw,
2288 /* 2270*/ CCD_ID_SAT__ENV_RES__ccr_allw_mdfy,
2289 /* 2271*/ CCD_ID_SAT__ENV_RES_SMC__msg_type,
2290 /* 2272*/ CCD_ID_SAT__ENV_RES_SMC__smcr_allw,
2291 /* 2273*/ CCD_ID_SAT__ENV_RES_SMC__smcr_not_allw,
2292 /* 2274*/ CCD_ID_SAT__ENV_RES_SMC__smcr_allw_mdfy,
2293 /* 2275*/ CCD_ID_SAT__RUN_AT__msg_type,
2294 /* 2276*/ CCD_ID_SAT__RUN_AT__alpha_id,
2295 /* 2277*/ CCD_ID_SAT__RUN_AT__at_string,
2296 /* 2278*/ CCD_ID_SAT__RUN_AT__icon,
2297 /* 2279*/ CCD_ID_SAT__OPEN_CHANNEL__msg_type,
2298 /* 2280*/ CCD_ID_SAT__OPEN_CHANNEL__alpha_id,
2299 /* 2281*/ CCD_ID_SAT__OPEN_CHANNEL__icon,
2300 /* 2282*/ CCD_ID_SAT__OPEN_CHANNEL__addr,
2301 /* 2283*/ CCD_ID_SAT__OPEN_CHANNEL__subaddr,
2302 /* 2284*/ CCD_ID_SAT__OPEN_CHANNEL__dur,
2303 /* 2285*/ CCD_ID_SAT__OPEN_CHANNEL__dur2,
2304 /* 2286*/ CCD_ID_SAT__OPEN_CHANNEL__bear_desc,
2305 /* 2287*/ CCD_ID_SAT__OPEN_CHANNEL__buffer_size,
2306 /* 2288*/ CCD_ID_SAT__OPEN_CHANNEL__nan_buf,
2307 /* 2289*/ CCD_ID_SAT__OPEN_CHANNEL__other_addr,
2308 /* 2290*/ CCD_ID_SAT__OPEN_CHANNEL__text,
2309 /* 2291*/ CCD_ID_SAT__OPEN_CHANNEL__text2,
2310 /* 2292*/ CCD_ID_SAT__OPEN_CHANNEL__if_transp_lev,
2311 /* 2293*/ CCD_ID_SAT__OPEN_CHANNEL__data_dest_addr,
2312 /* 2294*/ CCD_ID_SAT__CLOSE_CHANNEL__msg_type,
2313 /* 2295*/ CCD_ID_SAT__CLOSE_CHANNEL__alpha_id,
2314 /* 2296*/ CCD_ID_SAT__CLOSE_CHANNEL__icon,
2315 /* 2297*/ CCD_ID_SAT__RECEIVE_DATA__msg_type,
2316 /* 2298*/ CCD_ID_SAT__RECEIVE_DATA__alpha_id,
2317 /* 2299*/ CCD_ID_SAT__RECEIVE_DATA__icon,
2318 /* 2300*/ CCD_ID_SAT__RECEIVE_DATA__chan_dat_lth,
2319 /* 2301*/ CCD_ID_SAT__SEND_DATA__msg_type,
2320 /* 2302*/ CCD_ID_SAT__SEND_DATA__alpha_id,
2321 /* 2303*/ CCD_ID_SAT__SEND_DATA__icon,
2322 /* 2304*/ CCD_ID_SAT__SEND_DATA__chan_data,
2323 /* 2305*/ CCD_ID_SAT__GET_CHA_STAT__msg_type,
2324 /* 2306*/ CCD_ID_SAT__LAUNCH_BROWSER__msg_type,
2325 /* 2307*/ CCD_ID_SAT__LAUNCH_BROWSER__browser_id,
2326 /* 2308*/ CCD_ID_SAT__LAUNCH_BROWSER__url,
2327 /* 2309*/ CCD_ID_SAT__LAUNCH_BROWSER__bearer,
2328 /* 2310*/ CCD_ID_SAT__LAUNCH_BROWSER__prov_file_ref,
2329 /* 2311*/ CCD_ID_SAT__LAUNCH_BROWSER__text,
2330 /* 2312*/ CCD_ID_SAT__LAUNCH_BROWSER__alpha_id,
2331 /* 2313*/ CCD_ID_SAT__LAUNCH_BROWSER__icon,
2332 /* 2314*/ CCD_ID_T30__cap0_rcv__spare_0,
2333 /* 2315*/ CCD_ID_T30__cap0_rcv__v8,
2334 /* 2316*/ CCD_ID_T30__cap0_rcv__n_byte,
2335 /* 2317*/ CCD_ID_T30__cap0_rcv__spare_1,
2336 /* 2318*/ CCD_ID_T30__cap0_rcv__ready_tx_fax,
2337 /* 2319*/ CCD_ID_T30__cap0_rcv__rec_fax_op,
2338 /* 2320*/ CCD_ID_T30__cap0_rcv__data_sig_rate,
2339 /* 2321*/ CCD_ID_T30__cap0_rcv__R8_lines_pels,
2340 /* 2322*/ CCD_ID_T30__cap0_rcv__two_dim_coding,
2341 /* 2323*/ CCD_ID_T30__cap0_rcv__rec_width,
2342 /* 2324*/ CCD_ID_T30__cap0_rcv__max_rec_len,
2343 /* 2325*/ CCD_ID_T30__cap0_rcv__min_scan_time,
2344 /* 2326*/ CCD_ID_T30__cap1_rcv__spare_0,
2345 /* 2327*/ CCD_ID_T30__cap1_rcv__uncomp_mode,
2346 /* 2328*/ CCD_ID_T30__cap1_rcv__err_corr_mode,
2347 /* 2329*/ CCD_ID_T30__cap1_rcv__spare_1,
2348 /* 2330*/ CCD_ID_T30__cap1_rcv__t6_coding,
2349 /* 2331*/ CCD_ID_T30__cap2_rcv__spare_0,
2350 /* 2332*/ CCD_ID_T30__cap3_rcv__R8_lines,
2351 /* 2333*/ CCD_ID_T30__cap3_rcv__r_300_pels,
2352 /* 2334*/ CCD_ID_T30__cap3_rcv__R16_lines_pels,
2353 /* 2335*/ CCD_ID_T30__cap3_rcv__i_res_pref,
2354 /* 2336*/ CCD_ID_T30__cap3_rcv__m_res_pref,
2355 /* 2337*/ CCD_ID_T30__cap3_rcv__min_scan_time_hr,
2356 /* 2338*/ CCD_ID_T30__cap3_rcv__sel_polling,
2357 /* 2339*/ CCD_ID_T30__cap4_rcv__subaddr,
2358 /* 2340*/ CCD_ID_T30__cap4_rcv__password,
2359 /* 2341*/ CCD_ID_T30__cap4_rcv__ready_tx_doc,
2360 /* 2342*/ CCD_ID_T30__cap4_rcv__spare_0,
2361 /* 2343*/ CCD_ID_T30__cap4_rcv__bft,
2362 /* 2344*/ CCD_ID_T30__cap4_rcv__dtm,
2363 /* 2345*/ CCD_ID_T30__cap4_rcv__edi,
2364 /* 2346*/ CCD_ID_T30__cap5_rcv__btm,
2365 /* 2347*/ CCD_ID_T30__cap5_rcv__spare_0,
2366 /* 2348*/ CCD_ID_T30__cap5_rcv__ready_tx_mixed,
2367 /* 2349*/ CCD_ID_T30__cap5_rcv__char_mode,
2368 /* 2350*/ CCD_ID_T30__cap5_rcv__spare_1,
2369 /* 2351*/ CCD_ID_T30__cap5_rcv__mixed_mode,
2370 /* 2352*/ CCD_ID_T30__cap5_rcv__spare_2,
2371 /* 2353*/ CCD_ID_T30__cap6_rcv__proc_mode_26,
2372 /* 2354*/ CCD_ID_T30__cap6_rcv__dig_network_cap,
2373 /* 2355*/ CCD_ID_T30__cap6_rcv__duplex,
2374 /* 2356*/ CCD_ID_T30__cap6_rcv__jpeg,
2375 /* 2357*/ CCD_ID_T30__cap6_rcv__full_colour,
2376 /* 2358*/ CCD_ID_T30__cap6_rcv__spare_0,
2377 /* 2359*/ CCD_ID_T30__cap6_rcv__r_12_bits_pel_comp,
2378 /* 2360*/ CCD_ID_T30__cap7_rcv__no_subsamp,
2379 /* 2361*/ CCD_ID_T30__cap7_rcv__cust_illum,
2380 /* 2362*/ CCD_ID_T30__cap7_rcv__cust_gamut,
2381 /* 2363*/ CCD_ID_T30__cap7_rcv__na_letter,
2382 /* 2364*/ CCD_ID_T30__cap7_rcv__na_legal,
2383 /* 2365*/ CCD_ID_T30__cap7_rcv__sing_prog_seq_coding_basic,
2384 /* 2366*/ CCD_ID_T30__cap7_rcv__sing_prog_seq_coding_L0,
2385 /* 2367*/ CCD_ID_T30__cap0_snd__spare_0,
2386 /* 2368*/ CCD_ID_T30__cap0_snd__rec_fax_op,
2387 /* 2369*/ CCD_ID_T30__cap0_snd__data_sig_rate,
2388 /* 2370*/ CCD_ID_T30__cap0_snd__R8_lines_pels,
2389 /* 2371*/ CCD_ID_T30__cap0_snd__two_dim_coding,
2390 /* 2372*/ CCD_ID_T30__cap0_snd__rec_width,
2391 /* 2373*/ CCD_ID_T30__cap0_snd__max_rec_len,
2392 /* 2374*/ CCD_ID_T30__cap0_snd__min_scan_time,
2393 /* 2375*/ CCD_ID_T30__cap1_snd__spare_0,
2394 /* 2376*/ CCD_ID_T30__cap1_snd__uncomp_mode,
2395 /* 2377*/ CCD_ID_T30__cap1_snd__err_corr_mode,
2396 /* 2378*/ CCD_ID_T30__cap1_snd__frame_size,
2397 /* 2379*/ CCD_ID_T30__cap1_snd__spare_1,
2398 /* 2380*/ CCD_ID_T30__cap1_snd__t6_coding,
2399 /* 2381*/ CCD_ID_T30__cap2_snd__spare_0,
2400 /* 2382*/ CCD_ID_T30__cap3_snd__R8_lines,
2401 /* 2383*/ CCD_ID_T30__cap3_snd__r_300_pels,
2402 /* 2384*/ CCD_ID_T30__cap3_snd__R16_lines_pels,
2403 /* 2385*/ CCD_ID_T30__cap3_snd__resolution_type,
2404 /* 2386*/ CCD_ID_T30__cap3_snd__spare_0,
2405 /* 2387*/ CCD_ID_T30__cap4_snd__subaddr,
2406 /* 2388*/ CCD_ID_T30__cap4_snd__password,
2407 /* 2389*/ CCD_ID_T30__cap4_snd__spare_0,
2408 /* 2390*/ CCD_ID_T30__cap4_snd__bft,
2409 /* 2391*/ CCD_ID_T30__cap4_snd__dtm,
2410 /* 2392*/ CCD_ID_T30__cap4_snd__edi,
2411 /* 2393*/ CCD_ID_T30__cap5_snd__btm,
2412 /* 2394*/ CCD_ID_T30__cap5_snd__spare_0,
2413 /* 2395*/ CCD_ID_T30__cap5_snd__char_mode,
2414 /* 2396*/ CCD_ID_T30__cap5_snd__spare_1,
2415 /* 2397*/ CCD_ID_T30__cap5_snd__mixed_mode,
2416 /* 2398*/ CCD_ID_T30__cap5_snd__spare_2,
2417 /* 2399*/ CCD_ID_T30__cap6_snd__proc_mode_26,
2418 /* 2400*/ CCD_ID_T30__cap6_snd__dig_network_cap,
2419 /* 2401*/ CCD_ID_T30__cap6_snd__duplex,
2420 /* 2402*/ CCD_ID_T30__cap6_snd__jpeg,
2421 /* 2403*/ CCD_ID_T30__cap6_snd__full_colour,
2422 /* 2404*/ CCD_ID_T30__cap6_snd__huffman_tables,
2423 /* 2405*/ CCD_ID_T30__cap6_snd__r_12_bits_pel_comp,
2424 /* 2406*/ CCD_ID_T30__cap7_snd__no_subsamp,
2425 /* 2407*/ CCD_ID_T30__cap7_snd__cust_illum,
2426 /* 2408*/ CCD_ID_T30__cap7_snd__cust_gamut,
2427 /* 2409*/ CCD_ID_T30__cap7_snd__na_letter,
2428 /* 2410*/ CCD_ID_T30__cap7_snd__na_legal,
2429 /* 2411*/ CCD_ID_T30__cap7_snd__sing_prog_seq_coding_basic,
2430 /* 2412*/ CCD_ID_T30__cap7_snd__sing_prog_seq_coding_L0,
2431 /* 2413*/ CCD_ID_T30__BCS_DIS__fcf,
2432 /* 2414*/ CCD_ID_T30__BCS_DIS__cap0_rcv,
2433 /* 2415*/ CCD_ID_T30__BCS_DIS__cap1_rcv,
2434 /* 2416*/ CCD_ID_T30__BCS_DIS__cap2_rcv,
2435 /* 2417*/ CCD_ID_T30__BCS_DIS__cap3_rcv,
2436 /* 2418*/ CCD_ID_T30__BCS_DIS__cap4_rcv,
2437 /* 2419*/ CCD_ID_T30__BCS_DIS__cap5_rcv,
2438 /* 2420*/ CCD_ID_T30__BCS_DIS__cap6_rcv,
2439 /* 2421*/ CCD_ID_T30__BCS_DIS__cap7_rcv,
2440 /* 2422*/ CCD_ID_T30__BCS_CSI__fcf,
2441 /* 2423*/ CCD_ID_T30__BCS_CSI__cld_sub_nr,
2442 /* 2424*/ CCD_ID_T30__BCS_NSF__fcf,
2443 /* 2425*/ CCD_ID_T30__BCS_NSF__non_std_fac,
2444 /* 2426*/ CCD_ID_T30__BCS_DTC__fcf,
2445 /* 2427*/ CCD_ID_T30__BCS_DTC__cap0_rcv,
2446 /* 2428*/ CCD_ID_T30__BCS_DTC__cap1_rcv,
2447 /* 2429*/ CCD_ID_T30__BCS_DTC__cap2_rcv,
2448 /* 2430*/ CCD_ID_T30__BCS_DTC__cap3_rcv,
2449 /* 2431*/ CCD_ID_T30__BCS_DTC__cap4_rcv,
2450 /* 2432*/ CCD_ID_T30__BCS_DTC__cap5_rcv,
2451 /* 2433*/ CCD_ID_T30__BCS_DTC__cap6_rcv,
2452 /* 2434*/ CCD_ID_T30__BCS_DTC__cap7_rcv,
2453 /* 2435*/ CCD_ID_T30__BCS_CIG__fcf,
2454 /* 2436*/ CCD_ID_T30__BCS_CIG__clg_sub_nr,
2455 /* 2437*/ CCD_ID_T30__BCS_NSC__fcf,
2456 /* 2438*/ CCD_ID_T30__BCS_NSC__non_std_fac,
2457 /* 2439*/ CCD_ID_T30__BCS_PWD_POLL__fcf,
2458 /* 2440*/ CCD_ID_T30__BCS_PWD_POLL__pm_pword,
2459 /* 2441*/ CCD_ID_T30__BCS_SEP__fcf,
2460 /* 2442*/ CCD_ID_T30__BCS_SEP__pm_sub_addr,
2461 /* 2443*/ CCD_ID_T30__BCS_DCS__fcf,
2462 /* 2444*/ CCD_ID_T30__BCS_DCS__cap0_snd,
2463 /* 2445*/ CCD_ID_T30__BCS_DCS__cap1_snd,
2464 /* 2446*/ CCD_ID_T30__BCS_DCS__cap2_snd,
2465 /* 2447*/ CCD_ID_T30__BCS_DCS__cap3_snd,
2466 /* 2448*/ CCD_ID_T30__BCS_DCS__cap4_snd,
2467 /* 2449*/ CCD_ID_T30__BCS_DCS__cap5_snd,
2468 /* 2450*/ CCD_ID_T30__BCS_DCS__cap6_snd,
2469 /* 2451*/ CCD_ID_T30__BCS_DCS__cap7_snd,
2470 /* 2452*/ CCD_ID_T30__BCS_TSI__fcf,
2471 /* 2453*/ CCD_ID_T30__BCS_TSI__tra_sub_nr,
2472 /* 2454*/ CCD_ID_T30__BCS_NSS__fcf,
2473 /* 2455*/ CCD_ID_T30__BCS_NSS__non_std_fac,
2474 /* 2456*/ CCD_ID_T30__BCS_SUB__fcf,
2475 /* 2457*/ CCD_ID_T30__BCS_SUB__sub_addr,
2476 /* 2458*/ CCD_ID_T30__BCS_PWD_SND__fcf,
2477 /* 2459*/ CCD_ID_T30__BCS_PWD_SND__sm_pword,
2478 /* 2460*/ CCD_ID_T30__BCS_CFR__fcf,
2479 /* 2461*/ CCD_ID_T30__BCS_FTT__fcf,
2480 /* 2462*/ CCD_ID_T30__BCS_EOM__fcf,
2481 /* 2463*/ CCD_ID_T30__BCS_MPS__fcf,
2482 /* 2464*/ CCD_ID_T30__BCS_EOP__fcf,
2483 /* 2465*/ CCD_ID_T30__BCS_PRI_EOM__fcf,
2484 /* 2466*/ CCD_ID_T30__BCS_PRI_MPS__fcf,
2485 /* 2467*/ CCD_ID_T30__BCS_PRI_EOP__fcf,
2486 /* 2468*/ CCD_ID_T30__BCS_MCF__fcf,
2487 /* 2469*/ CCD_ID_T30__BCS_RTP__fcf,
2488 /* 2470*/ CCD_ID_T30__BCS_RTN__fcf,
2489 /* 2471*/ CCD_ID_T30__BCS_PIP__fcf,
2490 /* 2472*/ CCD_ID_T30__BCS_PIN__fcf,
2491 /* 2473*/ CCD_ID_T30__BCS_DCN__fcf,
2492 /* 2474*/ CCD_ID_T30__BCS_CRP__fcf,
2493 /* 2475*/ CCD_ID_GMM__authentication_parameter_rand__rand_value,
2494 /* 2476*/ CCD_ID_GMM__ciphering_key_sequence_number__spare_0,
2495 /* 2477*/ CCD_ID_GMM__ciphering_key_sequence_number__key_sequence,
2496 /* 2478*/ CCD_ID_GMM__a_c_reference_number__a_c_reference_number_value,
2497 /* 2479*/ CCD_ID_GMM__imeisv_request__spare_0,
2498 /* 2480*/ CCD_ID_GMM__imeisv_request__imeisv_request_value,
2499 /* 2481*/ CCD_ID_GMM__ciphering_algorithm__spare_0,
2500 /* 2482*/ CCD_ID_GMM__ciphering_algorithm__type_of_algorithm,
2501 /* 2483*/ CCD_ID_GMM__authentication_parameter_sres__sres_value,
2502 /* 2484*/ CCD_ID_GMM__identity_type_2__spare_0,
2503 /* 2485*/ CCD_ID_GMM__identity_type_2__type_of_identity_2,
2504 /* 2486*/ CCD_ID_GMM__routing_area_identification__mcc,
2505 /* 2487*/ CCD_ID_GMM__routing_area_identification__mnc,
2506 /* 2488*/ CCD_ID_GMM__routing_area_identification__lac,
2507 /* 2489*/ CCD_ID_GMM__routing_area_identification__rac,
2508 /* 2490*/ CCD_ID_GMM__update_type__spare_0,
2509 /* 2491*/ CCD_ID_GMM__update_type__update_type_value,
2510 /* 2492*/ CCD_ID_GMM__result_gmm__spare_0,
2511 /* 2493*/ CCD_ID_GMM__result_gmm__result_value,
2512 /* 2494*/ CCD_ID_GMM__mobile_identity__type_of_identity,
2513 /* 2495*/ CCD_ID_GMM__mobile_identity__odd_even,
2514 /* 2496*/ CCD_ID_GMM__mobile_identity__identity_digit,
2515 /* 2497*/ CCD_ID_GMM__mobile_identity__spare_0,
2516 /* 2498*/ CCD_ID_GMM__mobile_identity__tmsi,
2517 /* 2499*/ CCD_ID_GMM__mobile_identity__dmy,
2518 /* 2500*/ CCD_ID_GMM__attach_type__spare_0,
2519 /* 2501*/ CCD_ID_GMM__attach_type__type_of_attach,
2520 /* 2502*/ CCD_ID_GMM__d_detach_type__spare_0,
2521 /* 2503*/ CCD_ID_GMM__d_detach_type__d_type_of_detach,
2522 /* 2504*/ CCD_ID_GMM__u_detach_type__power_off,
2523 /* 2505*/ CCD_ID_GMM__u_detach_type__u_type_of_detach,
2524 /* 2506*/ CCD_ID_GMM__drx_parameter__split_pg_cycle_code,
2525 /* 2507*/ CCD_ID_GMM__drx_parameter__spare_0,
2526 /* 2508*/ CCD_ID_GMM__drx_parameter__split_on_ccch,
2527 /* 2509*/ CCD_ID_GMM__drx_parameter__non_drx_timer,
2528 /* 2510*/ CCD_ID_GMM__ready_timer__timer_unit,
2529 /* 2511*/ CCD_ID_GMM__ready_timer__timer_value,
2530 /* 2512*/ CCD_ID_GMM__t3302__timer_unit,
2531 /* 2513*/ CCD_ID_GMM__t3302__timer_value,
2532 /* 2514*/ CCD_ID_GMM__p_tmsi_signature__p_tmsi_signature_value,
2533 /* 2515*/ CCD_ID_GMM__force_to_standby__spare_0,
2534 /* 2516*/ CCD_ID_GMM__force_to_standby__force_to_standby_value,
2535 /* 2517*/ CCD_ID_GMM__radio_priority__spare_0,
2536 /* 2518*/ CCD_ID_GMM__radio_priority__radio_priority_level_value,
2537 /* 2519*/ CCD_ID_GMM__gmm_cause__cause_value,
2538 /* 2520*/ CCD_ID_GMM__receive_n_pdu_number_list_val__nsapi,
2539 /* 2521*/ CCD_ID_GMM__receive_n_pdu_number_list_val__receive_n_pdu_number_val,
2540 /* 2522*/ CCD_ID_GMM__receive_n_pdu_number_list__receive_n_pdu_number_list_val,
2541 /* 2523*/ CCD_ID_GMM__receive_n_pdu_number_list__spare_0,
2542 /* 2524*/ CCD_ID_GMM__full_network_name__spare_0,
2543 /* 2525*/ CCD_ID_GMM__full_network_name__code,
2544 /* 2526*/ CCD_ID_GMM__full_network_name__add_ci,
2545 /* 2527*/ CCD_ID_GMM__full_network_name__nr_sparebits,
2546 /* 2528*/ CCD_ID_GMM__full_network_name__text_string,
2547 /* 2529*/ CCD_ID_GMM__time_zone__time_zone_value,
2548 /* 2530*/ CCD_ID_GMM__time_zone_and_time__year,
2549 /* 2531*/ CCD_ID_GMM__time_zone_and_time__month,
2550 /* 2532*/ CCD_ID_GMM__time_zone_and_time__day,
2551 /* 2533*/ CCD_ID_GMM__time_zone_and_time__hour,
2552 /* 2534*/ CCD_ID_GMM__time_zone_and_time__minute,
2553 /* 2535*/ CCD_ID_GMM__time_zone_and_time__second,
2554 /* 2536*/ CCD_ID_GMM__time_zone_and_time__time_zone_value,
2555 /* 2537*/ CCD_ID_GMM__tmsi_status__spare_0,
2556 /* 2538*/ CCD_ID_GMM__tmsi_status__tmsi_flag,
2557 /* 2539*/ CCD_ID_GMM__ext_gea_bits__gea_2,
2558 /* 2540*/ CCD_ID_GMM__ext_gea_bits__gea_3,
2559 /* 2541*/ CCD_ID_GMM__ext_gea_bits__gea_4,
2560 /* 2542*/ CCD_ID_GMM__ext_gea_bits__gea_5,
2561 /* 2543*/ CCD_ID_GMM__ext_gea_bits__gea_6,
2562 /* 2544*/ CCD_ID_GMM__ext_gea_bits__gea_7,
2563 /* 2545*/ CCD_ID_GMM__ms_network_capability__gea_1,
2564 /* 2546*/ CCD_ID_GMM__ms_network_capability__sm_capabilities_gsm,
2565 /* 2547*/ CCD_ID_GMM__ms_network_capability__sm_capabilities_gprs,
2566 /* 2548*/ CCD_ID_GMM__ms_network_capability__ucs2_support,
2567 /* 2549*/ CCD_ID_GMM__ms_network_capability__ss_screening_indicator,
2568 /* 2550*/ CCD_ID_GMM__ms_network_capability__solsa_capability,
2569 /* 2551*/ CCD_ID_GMM__ms_network_capability__rev_level_ind,
2570 /* 2552*/ CCD_ID_GMM__ms_network_capability__pfc_feature_mode,
2571 /* 2553*/ CCD_ID_GMM__ms_network_capability__ext_gea_bits,
2572 /* 2554*/ CCD_ID_GMM__ms_network_capability__spare_0,
2573 /* 2555*/ CCD_ID_GMM__eqv_plmn__mcc,
2574 /* 2556*/ CCD_ID_GMM__eqv_plmn__mnc,
2575 /* 2557*/ CCD_ID_GMM__eqv_plmn_list__eqv_plmn,
2576 /* 2558*/ CCD_ID_GMM__p_tmsi_signature_2__p_tmsi_signature_value,
2577 /* 2559*/ CCD_ID_GMM__pdp_context_status__nsapi_set,
2578 /* 2560*/ CCD_ID_GMM__lsa_identifier__lsa_id,
2579 /* 2561*/ CCD_ID_GMM__daylight_save_time__spare_0,
2580 /* 2562*/ CCD_ID_GMM__daylight_save_time__save_time_value,
2581 /* 2563*/ CCD_ID_GMM__ATTACH_REQUEST__msg_type,
2582 /* 2564*/ CCD_ID_GMM__ATTACH_REQUEST__ms_network_capability,
2583 /* 2565*/ CCD_ID_GMM__ATTACH_REQUEST__attach_type,
2584 /* 2566*/ CCD_ID_GMM__ATTACH_REQUEST__ciphering_key_sequence_number,
2585 /* 2567*/ CCD_ID_GMM__ATTACH_REQUEST__drx_parameter,
2586 /* 2568*/ CCD_ID_GMM__ATTACH_REQUEST__gmobile_identity,
2587 /* 2569*/ CCD_ID_GMM__ATTACH_REQUEST__routing_area_identification,
2588 /* 2570*/ CCD_ID_GMM__ATTACH_REQUEST__ra_cap,
2589 /* 2571*/ CCD_ID_GMM__ATTACH_REQUEST__p_tmsi_signature,
2590 /* 2572*/ CCD_ID_GMM__ATTACH_REQUEST__ready_timer,
2591 /* 2573*/ CCD_ID_GMM__ATTACH_REQUEST__tmsi_status,
2592 /* 2574*/ CCD_ID_GMM__ATTACH_ACCEPT__msg_type,
2593 /* 2575*/ CCD_ID_GMM__ATTACH_ACCEPT__result_gmm,
2594 /* 2576*/ CCD_ID_GMM__ATTACH_ACCEPT__force_to_standby,
2595 /* 2577*/ CCD_ID_GMM__ATTACH_ACCEPT__rau_timer,
2596 /* 2578*/ CCD_ID_GMM__ATTACH_ACCEPT__radio_priority,
2597 /* 2579*/ CCD_ID_GMM__ATTACH_ACCEPT__spare_0,
2598 /* 2580*/ CCD_ID_GMM__ATTACH_ACCEPT__routing_area_identification,
2599 /* 2581*/ CCD_ID_GMM__ATTACH_ACCEPT__p_tmsi_signature,
2600 /* 2582*/ CCD_ID_GMM__ATTACH_ACCEPT__ready_timer,
2601 /* 2583*/ CCD_ID_GMM__ATTACH_ACCEPT__gmobile_identity,
2602 /* 2584*/ CCD_ID_GMM__ATTACH_ACCEPT__mobile_identity,
2603 /* 2585*/ CCD_ID_GMM__ATTACH_ACCEPT__gmm_cause,
2604 /* 2586*/ CCD_ID_GMM__ATTACH_ACCEPT__t3302,
2605 /* 2587*/ CCD_ID_GMM__ATTACH_ACCEPT__cell_notification,
2606 /* 2588*/ CCD_ID_GMM__ATTACH_ACCEPT__eqv_plmn_list,
2607 /* 2589*/ CCD_ID_GMM__ATTACH_COMPLETE__msg_type,
2608 /* 2590*/ CCD_ID_GMM__ATTACH_REJECT__msg_type,
2609 /* 2591*/ CCD_ID_GMM__ATTACH_REJECT__gmm_cause,
2610 /* 2592*/ CCD_ID_GMM__ATTACH_REJECT__t3302,
2611 /* 2593*/ CCD_ID_GMM__D_DETACH_REQUEST__msg_type,
2612 /* 2594*/ CCD_ID_GMM__D_DETACH_REQUEST__d_detach_type,
2613 /* 2595*/ CCD_ID_GMM__D_DETACH_REQUEST__force_to_standby,
2614 /* 2596*/ CCD_ID_GMM__D_DETACH_REQUEST__gmm_cause,
2615 /* 2597*/ CCD_ID_GMM__U_DETACH_REQUEST__msg_type,
2616 /* 2598*/ CCD_ID_GMM__U_DETACH_REQUEST__u_detach_type,
2617 /* 2599*/ CCD_ID_GMM__U_DETACH_REQUEST__spare_0,
2618 /* 2600*/ CCD_ID_GMM__U_DETACH_REQUEST__gmobile_identity,
2619 /* 2601*/ CCD_ID_GMM__U_DETACH_REQUEST__p_tmsi_signature_2,
2620 /* 2602*/ CCD_ID_GMM__U_DETACH_ACCEPT__msg_type,
2621 /* 2603*/ CCD_ID_GMM__D_DETACH_ACCEPT__msg_type,
2622 /* 2604*/ CCD_ID_GMM__D_DETACH_ACCEPT__force_to_standby,
2623 /* 2605*/ CCD_ID_GMM__D_DETACH_ACCEPT__spare_0,
2624 /* 2606*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__msg_type,
2625 /* 2607*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__update_type,
2626 /* 2608*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__ciphering_key_sequence_number,
2627 /* 2609*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__routing_area_identification,
2628 /* 2610*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__ra_cap,
2629 /* 2611*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__p_tmsi_signature,
2630 /* 2612*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__ready_timer,
2631 /* 2613*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__drx_parameter,
2632 /* 2614*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__tmsi_status,
2633 /* 2615*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__gmobile_identity,
2634 /* 2616*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__ms_network_capability,
2635 /* 2617*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REQUEST__pdp_context_status,
2636 /* 2618*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__msg_type,
2637 /* 2619*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__force_to_standby,
2638 /* 2620*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__result_gmm,
2639 /* 2621*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__rau_timer,
2640 /* 2622*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__routing_area_identification,
2641 /* 2623*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__p_tmsi_signature,
2642 /* 2624*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__gmobile_identity,
2643 /* 2625*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__mobile_identity,
2644 /* 2626*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__receive_n_pdu_number_list,
2645 /* 2627*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__ready_timer,
2646 /* 2628*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__gmm_cause,
2647 /* 2629*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__t3302,
2648 /* 2630*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__cell_notification,
2649 /* 2631*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_ACCEPT__eqv_plmn_list,
2650 /* 2632*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_COMPLETE__msg_type,
2651 /* 2633*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_COMPLETE__receive_n_pdu_number_list,
2652 /* 2634*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REJECT__msg_type,
2653 /* 2635*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REJECT__gmm_cause,
2654 /* 2636*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REJECT__force_to_standby,
2655 /* 2637*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REJECT__spare_0,
2656 /* 2638*/ CCD_ID_GMM__ROUTING_AREA_UPDATE_REJECT__t3302,
2657 /* 2639*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__msg_type,
2658 /* 2640*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__gmobile_identity,
2659 /* 2641*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__routing_area_identification,
2660 /* 2642*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__force_to_standby,
2661 /* 2643*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__spare_0,
2662 /* 2644*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMMAND__p_tmsi_signature,
2663 /* 2645*/ CCD_ID_GMM__P_TMSI_REALLOCATION_COMPLETE__msg_type,
2664 /* 2646*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__msg_type,
2665 /* 2647*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__ciphering_algorithm,
2666 /* 2648*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__imeisv_request,
2667 /* 2649*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__force_to_standby,
2668 /* 2650*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__a_c_reference_number,
2669 /* 2651*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__authentication_parameter_rand,
2670 /* 2652*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REQUEST__ciphering_key_sequence_number,
2671 /* 2653*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_RESPONSE__msg_type,
2672 /* 2654*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_RESPONSE__a_c_reference_number,
2673 /* 2655*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_RESPONSE__spare_0,
2674 /* 2656*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_RESPONSE__authentication_parameter_sres,
2675 /* 2657*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_RESPONSE__gmobile_identity,
2676 /* 2658*/ CCD_ID_GMM__AUTHENTICATION_AND_CIPHERING_REJECT__msg_type,
2677 /* 2659*/ CCD_ID_GMM__IDENTITY_REQUEST__msg_type,
2678 /* 2660*/ CCD_ID_GMM__IDENTITY_REQUEST__identity_type_2,
2679 /* 2661*/ CCD_ID_GMM__IDENTITY_REQUEST__force_to_standby,
2680 /* 2662*/ CCD_ID_GMM__IDENTITY_RESPONSE__msg_type,
2681 /* 2663*/ CCD_ID_GMM__IDENTITY_RESPONSE__gmobile_identity,
2682 /* 2664*/ CCD_ID_GMM__GMM_STATUS__msg_type,
2683 /* 2665*/ CCD_ID_GMM__GMM_STATUS__gmm_cause,
2684 /* 2666*/ CCD_ID_GMM__GMM_INFORMATION__msg_type,
2685 /* 2667*/ CCD_ID_GMM__GMM_INFORMATION__full_network_name,
2686 /* 2668*/ CCD_ID_GMM__GMM_INFORMATION__short_network_name,
2687 /* 2669*/ CCD_ID_GMM__GMM_INFORMATION__time_zone,
2688 /* 2670*/ CCD_ID_GMM__GMM_INFORMATION__time_zone_and_time,
2689 /* 2671*/ CCD_ID_GMM__GMM_INFORMATION__lsa_identifier,
2690 /* 2672*/ CCD_ID_GMM__GMM_INFORMATION__daylight_save_time,
2691 /* 2673*/ CCD_ID_TST__pdu_description__spare_0,
2692 /* 2674*/ CCD_ID_TST__pdu_description__no_of_pdus,
2693 /* 2675*/ CCD_ID_TST__pdu_description_ie__pdu_description,
2694 /* 2676*/ CCD_ID_TST__mode_flag__spare_0,
2695 /* 2677*/ CCD_ID_TST__mode_flag__dl_timeslot_offset,
2696 /* 2678*/ CCD_ID_TST__mode_flag__mode_flag_val,
2697 /* 2679*/ CCD_ID_TST__GPRS_TEST_MODE_CMD__msg_type,
2698 /* 2680*/ CCD_ID_TST__GPRS_TEST_MODE_CMD__pdu_description_ie,
2699 /* 2681*/ CCD_ID_TST__GPRS_TEST_MODE_CMD__mode_flag,
2700 /* 2682*/ CCD_ID_GRLC__glob_tfi__flag,
2701 /* 2683*/ CCD_ID_GRLC__glob_tfi__ul_tfi,
2702 /* 2684*/ CCD_ID_GRLC__glob_tfi__dl_tfi,
2703 /* 2685*/ CCD_ID_GRLC__chan_req_des__peak_thr_class,
2704 /* 2686*/ CCD_ID_GRLC__chan_req_des__radio_prio,
2705 /* 2687*/ CCD_ID_GRLC__chan_req_des__rlc_mode,
2706 /* 2688*/ CCD_ID_GRLC__chan_req_des__llc_pdu_type,
2707 /* 2689*/ CCD_ID_GRLC__chan_req_des__rlc_octet_cnt,
2708 /* 2690*/ CCD_ID_GRLC__block_struct__bl_o_bl_per,
2709 /* 2691*/ CCD_ID_GRLC__block_struct__a_map_len,
2710 /* 2692*/ CCD_ID_GRLC__block_struct__alloc_map,
2711 /* 2693*/ CCD_ID_GRLC__ext_bits__ext_len,
2712 /* 2694*/ CCD_ID_GRLC__ext_bits__spare_ext,
2713 /* 2695*/ CCD_ID_GRLC__ilev__ilev0,
2714 /* 2696*/ CCD_ID_GRLC__ilev__ilev1,
2715 /* 2697*/ CCD_ID_GRLC__ilev__ilev2,
2716 /* 2698*/ CCD_ID_GRLC__ilev__ilev3,
2717 /* 2699*/ CCD_ID_GRLC__ilev__ilev4,
2718 /* 2700*/ CCD_ID_GRLC__ilev__ilev5,
2719 /* 2701*/ CCD_ID_GRLC__ilev__ilev6,
2720 /* 2702*/ CCD_ID_GRLC__ilev__ilev7,
2721 /* 2703*/ CCD_ID_GRLC__chan_qual_rep__c_value,
2722 /* 2704*/ CCD_ID_GRLC__chan_qual_rep__rxqual,
2723 /* 2705*/ CCD_ID_GRLC__chan_qual_rep__signvar,
2724 /* 2706*/ CCD_ID_GRLC__chan_qual_rep__ilev,
2725 /* 2707*/ CCD_ID_GRLC__ack_nack_des__f_ack_ind,
2726 /* 2708*/ CCD_ID_GRLC__ack_nack_des__ssn,
2727 /* 2709*/ CCD_ID_GRLC__ack_nack_des__rbb,
2728 /* 2710*/ CCD_ID_GRLC__abs__t1,
2729 /* 2711*/ CCD_ID_GRLC__abs__t3,
2730 /* 2712*/ CCD_ID_GRLC__abs__t2,
2731 /* 2713*/ CCD_ID_GRLC__tbf_s_time__flag,
2732 /* 2714*/ CCD_ID_GRLC__tbf_s_time__rel,
2733 /* 2715*/ CCD_ID_GRLC__tbf_s_time__abs,
2734 /* 2716*/ CCD_ID_GRLC__fa_s2__tbf_s_time,
2735 /* 2717*/ CCD_ID_GRLC__fa_s2__ts_alloc,
2736 /* 2718*/ CCD_ID_GRLC__fa_s2__spare_0,
2737 /* 2719*/ CCD_ID_GRLC__fa_s2__flag,
2738 /* 2720*/ CCD_ID_GRLC__fa_s2__block_struct,
2739 /* 2721*/ CCD_ID_GRLC__fa_s2__alloc_map,
2740 /* 2722*/ CCD_ID_GRLC__f_alloc_ack__final_alloc,
2741 /* 2723*/ CCD_ID_GRLC__f_alloc_ack__flag,
2742 /* 2724*/ CCD_ID_GRLC__f_alloc_ack__ts_overr,
2743 /* 2725*/ CCD_ID_GRLC__f_alloc_ack__fa_s2,
2744 /* 2726*/ CCD_ID_GRLC__gamma_tn__gamma,
2745 /* 2727*/ CCD_ID_GRLC__pwr_par__alpha,
2746 /* 2728*/ CCD_ID_GRLC__pwr_par__gamma_tn,
2747 /* 2729*/ CCD_ID_GRLC__release_99_str_d_ul_ack__p_ext_ta,
2748 /* 2730*/ CCD_ID_GRLC__release_99_str_d_ul_ack__tbf_est,
2749 /* 2731*/ CCD_ID_GRLC__ta_index_tn__ta_index,
2750 /* 2732*/ CCD_ID_GRLC__ta_index_tn__ta_tn,
2751 /* 2733*/ CCD_ID_GRLC__pta__ta_value,
2752 /* 2734*/ CCD_ID_GRLC__pta__ta_index_tn,
2753 /* 2735*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__chan_coding_cmd,
2754 /* 2736*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__ack_nack_des,
2755 /* 2737*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__cr_tlli,
2756 /* 2738*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__pta,
2757 /* 2739*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__pwr_par,
2758 /* 2740*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__ext_bits,
2759 /* 2741*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__f_alloc_ack,
2760 /* 2742*/ CCD_ID_GRLC__gprs_ul_ack_nack_info__release_99_str_d_ul_ack,
2761 /* 2743*/ CCD_ID_GRLC__release_99_str_grlc_prr__flag,
2762 /* 2744*/ CCD_ID_GRLC__release_99_str_grlc_prr__flag2,
2763 /* 2745*/ CCD_ID_GRLC__release_99_str_grlc_prr__pfi,
2764 /* 2746*/ CCD_ID_GRLC__release_99_str_grlc_prr__add_ms_rac,
2765 /* 2747*/ CCD_ID_GRLC__release_99_str_grlc_prr__retrans_of_prr,
2766 /* 2748*/ CCD_ID_GRLC__release_99_str_u_grlc_dl_ack__pfi,
2767 /* 2749*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__msg_type,
2768 /* 2750*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__access_type,
2769 /* 2751*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__flag,
2770 /* 2752*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__glob_tfi,
2771 /* 2753*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__tlli_value,
2772 /* 2754*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__ra_cap,
2773 /* 2755*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__chan_req_des,
2774 /* 2756*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__ma_ch_mark,
2775 /* 2757*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__c_value,
2776 /* 2758*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__signvar,
2777 /* 2759*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__ilev,
2778 /* 2760*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__release_99_str_grlc_prr,
2779 /* 2761*/ CCD_ID_GRLC__U_GRLC_RESOURCE_REQ__spare_0,
2780 /* 2762*/ CCD_ID_GRLC__U_GRLC_DL_ACK__msg_type,
2781 /* 2763*/ CCD_ID_GRLC__U_GRLC_DL_ACK__dl_tfi,
2782 /* 2764*/ CCD_ID_GRLC__U_GRLC_DL_ACK__ack_nack_des,
2783 /* 2765*/ CCD_ID_GRLC__U_GRLC_DL_ACK__chan_req_des,
2784 /* 2766*/ CCD_ID_GRLC__U_GRLC_DL_ACK__chan_qual_rep,
2785 /* 2767*/ CCD_ID_GRLC__U_GRLC_DL_ACK__release_99_str_u_grlc_dl_ack,
2786 /* 2768*/ CCD_ID_GRLC__U_GRLC_DL_ACK__spare_0,
2787 /* 2769*/ CCD_ID_GRLC__D_GRLC_UL_ACK__msg_type,
2788 /* 2770*/ CCD_ID_GRLC__D_GRLC_UL_ACK__page_mode,
2789 /* 2771*/ CCD_ID_GRLC__D_GRLC_UL_ACK__spare_0,
2790 /* 2772*/ CCD_ID_GRLC__D_GRLC_UL_ACK__ul_tfi,
2791 /* 2773*/ CCD_ID_GRLC__D_GRLC_UL_ACK__egprs_flag,
2792 /* 2774*/ CCD_ID_GRLC__D_GRLC_UL_ACK__gprs_ul_ack_nack_info,
2793 /* 2775*/ CCD_ID_GRLC__D_GRLC_UL_ACK__spare_1,
2794 /* 2776*/ CCD_ID_GRLC__U_GRLC_CTRL_ACK__msg_type,
2795 /* 2777*/ CCD_ID_GRLC__U_GRLC_CTRL_ACK__tlli_value,
2796 /* 2778*/ CCD_ID_GRLC__U_GRLC_CTRL_ACK__pctrl_ack,
2797 /* 2779*/ CCD_ID_GRLC__U_GRLC_CTRL_ACK__spare_0,
2798 /* 2780*/ CCD_ID_GRLC__U_GRLC_UL_DUMMY__msg_type,
2799 /* 2781*/ CCD_ID_GRLC__U_GRLC_UL_DUMMY__tlli_value,
2800 /* 2782*/ CCD_ID_GRLC__U_GRLC_UL_DUMMY__spare_0,
2801 /* 2783*/ CCD_ID_GRR__wait__wait_ind,
2802 /* 2784*/ CCD_ID_GRR__wait__waitsize,
2803 /* 2785*/ CCD_ID_GRR__bts_pwr_ctrl__p0,
2804 /* 2786*/ CCD_ID_GRR__bts_pwr_ctrl__mode,
2805 /* 2787*/ CCD_ID_GRR__bts_pwr_ctrl__pr_mode,
2806 /* 2788*/ CCD_ID_GRR__psi_des__msg_type,
2807 /* 2789*/ CCD_ID_GRR__psi_des__psix_cm,
2808 /* 2790*/ CCD_ID_GRR__psi_des__flag,
2809 /* 2791*/ CCD_ID_GRR__psi_des__psix_cnt,
2810 /* 2792*/ CCD_ID_GRR__psi_des__inst_bitmap,
2811 /* 2793*/ CCD_ID_GRR__received_psi__psi_des,
2812 /* 2794*/ CCD_ID_GRR__received_psi__add_msg_type,
2813 /* 2795*/ CCD_ID_GRR__unknown_psi__msg_type,
2814 /* 2796*/ CCD_ID_GRR__unknown_psi__add_msg_type,
2815 /* 2797*/ CCD_ID_GRR__glob_tfi__flag,
2816 /* 2798*/ CCD_ID_GRR__glob_tfi__ul_tfi,
2817 /* 2799*/ CCD_ID_GRR__glob_tfi__dl_tfi,
2818 /* 2800*/ CCD_ID_GRR__add2__flag,
2819 /* 2801*/ CCD_ID_GRR__add2__glob_tfi,
2820 /* 2802*/ CCD_ID_GRR__add2__flag2,
2821 /* 2803*/ CCD_ID_GRR__add2__tlli_value,
2822 /* 2804*/ CCD_ID_GRR__add2__flag3,
2823 /* 2805*/ CCD_ID_GRR__add2__tqi,
2824 /* 2806*/ CCD_ID_GRR__add1__flag,
2825 /* 2807*/ CCD_ID_GRR__add1__glob_tfi,
2826 /* 2808*/ CCD_ID_GRR__add1__flag2,
2827 /* 2809*/ CCD_ID_GRR__add1__tlli_value,
2828 /* 2810*/ CCD_ID_GRR__chan_req_des__peak_thr_class,
2829 /* 2811*/ CCD_ID_GRR__chan_req_des__radio_prio,
2830 /* 2812*/ CCD_ID_GRR__chan_req_des__rlc_mode,
2831 /* 2813*/ CCD_ID_GRR__chan_req_des__llc_pdu_type,
2832 /* 2814*/ CCD_ID_GRR__chan_req_des__rlc_octet_cnt,
2833 /* 2815*/ CCD_ID_GRR__gpta__ta_value,
2834 /* 2816*/ CCD_ID_GRR__gpta__flag,
2835 /* 2817*/ CCD_ID_GRR__gpta__ul_ta_index,
2836 /* 2818*/ CCD_ID_GRR__gpta__ul_ta_tn,
2837 /* 2819*/ CCD_ID_GRR__gpta__flag2,
2838 /* 2820*/ CCD_ID_GRR__gpta__dl_ta_index,
2839 /* 2821*/ CCD_ID_GRR__gpta__dl_ta_tn,
2840 /* 2822*/ CCD_ID_GRR__chamge_ma_sub__cm1,
2841 /* 2823*/ CCD_ID_GRR__chamge_ma_sub__cm2,
2842 /* 2824*/ CCD_ID_GRR__indi_encod__maio,
2843 /* 2825*/ CCD_ID_GRR__indi_encod__ma_num,
2844 /* 2826*/ CCD_ID_GRR__indi_encod__chamge_ma_sub,
2845 /* 2827*/ CCD_ID_GRR__di_encod2__maio,
2846 /* 2828*/ CCD_ID_GRR__di_encod2__hsn,
2847 /* 2829*/ CCD_ID_GRR__di_encod2__len_ma_list,
2848 /* 2830*/ CCD_ID_GRR__di_encod2__ma_list,
2849 /* 2831*/ CCD_ID_GRR__block_struct__bl_o_bl_per,
2850 /* 2832*/ CCD_ID_GRR__block_struct__a_map_len,
2851 /* 2833*/ CCD_ID_GRR__block_struct__alloc_map,
2852 /* 2834*/ CCD_ID_GRR__g_pwr_par__alpha,
2853 /* 2835*/ CCD_ID_GRR__g_pwr_par__t_avg_w,
2854 /* 2836*/ CCD_ID_GRR__g_pwr_par__t_avg_t,
2855 /* 2837*/ CCD_ID_GRR__g_pwr_par__pb,
2856 /* 2838*/ CCD_ID_GRR__g_pwr_par__pc_meas_chan,
2857 /* 2839*/ CCD_ID_GRR__g_pwr_par__imeas_chan_list,
2858 /* 2840*/ CCD_ID_GRR__g_pwr_par__n_avg_i,
2859 /* 2841*/ CCD_ID_GRR__ext_bits__ext_len,
2860 /* 2842*/ CCD_ID_GRR__ext_bits__spare_ext,
2861 /* 2843*/ CCD_ID_GRR__pccch_org_par__bs_pcc_rel,
2862 /* 2844*/ CCD_ID_GRR__pccch_org_par__bs_pbcch_blks,
2863 /* 2845*/ CCD_ID_GRR__pccch_org_par__bs_pag_blks,
2864 /* 2846*/ CCD_ID_GRR__pccch_org_par__bs_prach_blks,
2865 /* 2847*/ CCD_ID_GRR__loc_area_ident__mcc,
2866 /* 2848*/ CCD_ID_GRR__loc_area_ident__mnc,
2867 /* 2849*/ CCD_ID_GRR__loc_area_ident__lac,
2868 /* 2850*/ CCD_ID_GRR__cell_id__loc_area_ident,
2869 /* 2851*/ CCD_ID_GRR__cell_id__rac,
2870 /* 2852*/ CCD_ID_GRR__cell_id__cell_id_ie,
2871 /* 2853*/ CCD_ID_GRR__rfl_num_list__rfl_num,
2872 /* 2854*/ CCD_ID_GRR__rfl_cont__flist,
2873 /* 2855*/ CCD_ID_GRR__rfl__rfl_num,
2874 /* 2856*/ CCD_ID_GRR__rfl__rfl_cont_len,
2875 /* 2857*/ CCD_ID_GRR__rfl__rfl_cont,
2876 /* 2858*/ CCD_ID_GRR__cell_alloc__rfl_num,
2877 /* 2859*/ CCD_ID_GRR__ma_struct__ma_len,
2878 /* 2860*/ CCD_ID_GRR__ma_struct__ma_map,
2879 /* 2861*/ CCD_ID_GRR__arfcn_index_list__arfcn_index,
2880 /* 2862*/ CCD_ID_GRR__gprs_ms_alloc_ie__hsn,
2881 /* 2863*/ CCD_ID_GRR__gprs_ms_alloc_ie__rfl_num_list,
2882 /* 2864*/ CCD_ID_GRR__gprs_ms_alloc_ie__flag,
2883 /* 2865*/ CCD_ID_GRR__gprs_ms_alloc_ie__ma_struct,
2884 /* 2866*/ CCD_ID_GRR__gprs_ms_alloc_ie__arfcn_index_list,
2885 /* 2867*/ CCD_ID_GRR__gprs_ms_alloc__ma_num,
2886 /* 2868*/ CCD_ID_GRR__gprs_ms_alloc__gprs_ms_alloc_ie,
2887 /* 2869*/ CCD_ID_GRR__di_encod1__maio,
2888 /* 2870*/ CCD_ID_GRR__di_encod1__gprs_ms_alloc_ie,
2889 /* 2871*/ CCD_ID_GRR__freq_par__tsc,
2890 /* 2872*/ CCD_ID_GRR__freq_par__flag,
2891 /* 2873*/ CCD_ID_GRR__freq_par__flag2,
2892 /* 2874*/ CCD_ID_GRR__freq_par__arfcn,
2893 /* 2875*/ CCD_ID_GRR__freq_par__indi_encod,
2894 /* 2876*/ CCD_ID_GRR__freq_par__di_encod1,
2895 /* 2877*/ CCD_ID_GRR__freq_par__di_encod2,
2896 /* 2878*/ CCD_ID_GRR__pbcch_des__pb,
2897 /* 2879*/ CCD_ID_GRR__pbcch_des__tsc,
2898 /* 2880*/ CCD_ID_GRR__pbcch_des__tn,
2899 /* 2881*/ CCD_ID_GRR__pbcch_des__flag,
2900 /* 2882*/ CCD_ID_GRR__pbcch_des__flag2,
2901 /* 2883*/ CCD_ID_GRR__pbcch_des__arfcn,
2902 /* 2884*/ CCD_ID_GRR__pbcch_des__maio,
2903 /* 2885*/ CCD_ID_GRR__h_pccch_c__maio,
2904 /* 2886*/ CCD_ID_GRR__h_pccch_c__ts_alloc,
2905 /* 2887*/ CCD_ID_GRR__nh_pccch_c__arfcn,
2906 /* 2888*/ CCD_ID_GRR__nh_pccch_c__ts_alloc,
2907 /* 2889*/ CCD_ID_GRR__ma_h_s1__ma_num,
2908 /* 2890*/ CCD_ID_GRR__ma_h_s1__h_pccch_c,
2909 /* 2891*/ CCD_ID_GRR__pccch_des__tsc,
2910 /* 2892*/ CCD_ID_GRR__pccch_des__flag,
2911 /* 2893*/ CCD_ID_GRR__pccch_des__nh_pccch_c,
2912 /* 2894*/ CCD_ID_GRR__pccch_des__ma_h_s1,
2913 /* 2895*/ CCD_ID_GRR__gen_cell_par__gprs_c_hyst,
2914 /* 2896*/ CCD_ID_GRR__gen_cell_par__c31_hyst,
2915 /* 2897*/ CCD_ID_GRR__gen_cell_par__c32_qual,
2916 /* 2898*/ CCD_ID_GRR__gen_cell_par__rab_acc_re,
2917 /* 2899*/ CCD_ID_GRR__gen_cell_par__t_resel,
2918 /* 2900*/ CCD_ID_GRR__gen_cell_par__ra_re_hyst,
2919 /* 2901*/ CCD_ID_GRR__hcs_par__gprs_prio_class,
2920 /* 2902*/ CCD_ID_GRR__hcs_par__gprs_hcs_thr,
2921 /* 2903*/ CCD_ID_GRR__scell_par__cell_ba,
2922 /* 2904*/ CCD_ID_GRR__scell_par__exc_acc,
2923 /* 2905*/ CCD_ID_GRR__scell_par__gprs_rxlev_access_min,
2924 /* 2906*/ CCD_ID_GRR__scell_par__txpwr_max_cch,
2925 /* 2907*/ CCD_ID_GRR__scell_par__hcs_par,
2926 /* 2908*/ CCD_ID_GRR__scell_par__multi_band_rep,
2927 /* 2909*/ CCD_ID_GRR__si13_pbcch_s1__pbcch_loc,
2928 /* 2910*/ CCD_ID_GRR__si13_pbcch_s1__psi1_rep_per,
2929 /* 2911*/ CCD_ID_GRR__si13_pbcch__flag,
2930 /* 2912*/ CCD_ID_GRR__si13_pbcch__si13_loc,
2931 /* 2913*/ CCD_ID_GRR__si13_pbcch__si13_pbcch_s1,
2932 /* 2914*/ CCD_ID_GRR__cs_par_s1__gprs_rxlev_access_min,
2933 /* 2915*/ CCD_ID_GRR__cs_par_s1__txpwr_max_cch,
2934 /* 2916*/ CCD_ID_GRR__cs_par_s2__gprs_temp_offset,
2935 /* 2917*/ CCD_ID_GRR__cs_par_s2__gprs_penalty_time,
2936 /* 2918*/ CCD_ID_GRR__cs_par__cell_ba,
2937 /* 2919*/ CCD_ID_GRR__cs_par__exc_acc,
2938 /* 2920*/ CCD_ID_GRR__cs_par__same_ra_scell,
2939 /* 2921*/ CCD_ID_GRR__cs_par__cs_par_s1,
2940 /* 2922*/ CCD_ID_GRR__cs_par__cs_par_s2,
2941 /* 2923*/ CCD_ID_GRR__cs_par__gprs_resel_off,
2942 /* 2924*/ CCD_ID_GRR__cs_par__hcs_par,
2943 /* 2925*/ CCD_ID_GRR__cs_par__si13_pbcch,
2944 /* 2926*/ CCD_ID_GRR__ncell_par2_set__ncc,
2945 /* 2927*/ CCD_ID_GRR__ncell_par2_set__exc_acc,
2946 /* 2928*/ CCD_ID_GRR__ncell_par2_set__gprs_rxlev_access_min,
2947 /* 2929*/ CCD_ID_GRR__ncell_par2_set__txpwr_max_cch,
2948 /* 2930*/ CCD_ID_GRR__ncell_par2_set__gprs_prio_class,
2949 /* 2931*/ CCD_ID_GRR__ncell_par2_set__gprs_hcs_thr,
2950 /* 2932*/ CCD_ID_GRR__ncell_par2_set__si13_pbcch,
2951 /* 2933*/ CCD_ID_GRR__ncell_par2_set__gprs_temp_offset,
2952 /* 2934*/ CCD_ID_GRR__ncell_par2_set__gprs_penalty_time,
2953 /* 2935*/ CCD_ID_GRR__ncell_par2_set__gprs_resel_off,
2954 /* 2936*/ CCD_ID_GRR__ma_num_maio__ma_num,
2955 /* 2937*/ CCD_ID_GRR__ma_num_maio__maio,
2956 /* 2938*/ CCD_ID_GRR__chan_group__flag,
2957 /* 2939*/ CCD_ID_GRR__chan_group__arfcn,
2958 /* 2940*/ CCD_ID_GRR__chan_group__ma_num_maio,
2959 /* 2941*/ CCD_ID_GRR__chan_group__ts_alloc,
2960 /* 2942*/ CCD_ID_GRR__chan_list2__chan_group,
2961 /* 2943*/ CCD_ID_GRR__chan_list_imeas__chan_group,
2962 /* 2944*/ CCD_ID_GRR__chan_list_imeas__chan_list2,
2963 /* 2945*/ CCD_ID_GRR__list_rf__num_rfreq,
2964 /* 2946*/ CCD_ID_GRR__list_rf__rfreq_index,
2965 /* 2947*/ CCD_ID_GRR__si13_cm_gprs_alloc__si13_cm,
2966 /* 2948*/ CCD_ID_GRR__si13_cm_gprs_alloc__gprs_ms_alloc_ie,
2967 /* 2949*/ CCD_ID_GRR__psi13_pwr_par__alpha,
2968 /* 2950*/ CCD_ID_GRR__psi13_pwr_par__t_avg_w,
2969 /* 2951*/ CCD_ID_GRR__psi13_pwr_par__t_avg_t,
2970 /* 2952*/ CCD_ID_GRR__psi13_pwr_par__pc_meas_chan,
2971 /* 2953*/ CCD_ID_GRR__psi13_pwr_par__n_avg_i,
2972 /* 2954*/ CCD_ID_GRR__pbcch_n_pres__rac,
2973 /* 2955*/ CCD_ID_GRR__pbcch_n_pres__spgc_ccch_sup,
2974 /* 2956*/ CCD_ID_GRR__pbcch_n_pres__prio_acc_thr,
2975 /* 2957*/ CCD_ID_GRR__pbcch_n_pres__ctrl_order,
2976 /* 2958*/ CCD_ID_GRR__pbcch_n_pres__gprs_cell_opt,
2977 /* 2959*/ CCD_ID_GRR__pbcch_n_pres__psi13_pwr_par,
2978 /* 2960*/ CCD_ID_GRR__nc_meas_s1__freq_n,
2979 /* 2961*/ CCD_ID_GRR__nc_meas_s1__bsic,
2980 /* 2962*/ CCD_ID_GRR__nc_meas_s1__rxlev_n,
2981 /* 2963*/ CCD_ID_GRR__nc_meas_rep__nc_mode,
2982 /* 2964*/ CCD_ID_GRR__nc_meas_rep__rxlev_scell,
2983 /* 2965*/ CCD_ID_GRR__nc_meas_rep__i_scell,
2984 /* 2966*/ CCD_ID_GRR__nc_meas_rep__num_nc_meas,
2985 /* 2967*/ CCD_ID_GRR__nc_meas_rep__nc_meas_s1,
2986 /* 2968*/ CCD_ID_GRR__ilev__ilev0,
2987 /* 2969*/ CCD_ID_GRR__ilev__ilev1,
2988 /* 2970*/ CCD_ID_GRR__ilev__ilev2,
2989 /* 2971*/ CCD_ID_GRR__ilev__ilev3,
2990 /* 2972*/ CCD_ID_GRR__ilev__ilev4,
2991 /* 2973*/ CCD_ID_GRR__ilev__ilev5,
2992 /* 2974*/ CCD_ID_GRR__ilev__ilev6,
2993 /* 2975*/ CCD_ID_GRR__ilev__ilev7,
2994 /* 2976*/ CCD_ID_GRR__chan_qual_rep__c_value,
2995 /* 2977*/ CCD_ID_GRR__chan_qual_rep__rxqual,
2996 /* 2978*/ CCD_ID_GRR__chan_qual_rep__signvar,
2997 /* 2979*/ CCD_ID_GRR__chan_qual_rep__ilev,
2998 /* 2980*/ CCD_ID_GRR__ilev_abs__ilevabs0,
2999 /* 2981*/ CCD_ID_GRR__ilev_abs__ilevabs1,
3000 /* 2982*/ CCD_ID_GRR__ilev_abs__ilevabs2,
3001 /* 2983*/ CCD_ID_GRR__ilev_abs__ilevabs3,
3002 /* 2984*/ CCD_ID_GRR__ilev_abs__ilevabs4,
3003 /* 2985*/ CCD_ID_GRR__ilev_abs__ilevabs5,
3004 /* 2986*/ CCD_ID_GRR__ilev_abs__ilevabs6,
3005 /* 2987*/ CCD_ID_GRR__ilev_abs__ilevabs7,
3006 /* 2988*/ CCD_ID_GRR__ext_mp_s1__freq_n,
3007 /* 2989*/ CCD_ID_GRR__ext_mp_s1__bsic,
3008 /* 2990*/ CCD_ID_GRR__ext_mp_s1__rxlev_n,
3009 /* 2991*/ CCD_ID_GRR__xmeas_rep__xrep_type,
3010 /* 2992*/ CCD_ID_GRR__xmeas_rep__ilev_abs,
3011 /* 2993*/ CCD_ID_GRR__xmeas_rep__num_meas,
3012 /* 2994*/ CCD_ID_GRR__xmeas_rep__ext_mp_s1,
3013 /* 2995*/ CCD_ID_GRR__tn_alloc__usf,
3014 /* 2996*/ CCD_ID_GRR__usf_g__usf,
3015 /* 2997*/ CCD_ID_GRR__usf_g__gamma,
3016 /* 2998*/ CCD_ID_GRR__pers_lev__plev,
3017 /* 2999*/ CCD_ID_GRR__prach_ctrl_par__ac_class,
3018 /* 3000*/ CCD_ID_GRR__prach_ctrl_par__max_retrans,
3019 /* 3001*/ CCD_ID_GRR__prach_ctrl_par__s_prach,
3020 /* 3002*/ CCD_ID_GRR__prach_ctrl_par__tx_int,
3021 /* 3003*/ CCD_ID_GRR__prach_ctrl_par__pers_lev,
3022 /* 3004*/ CCD_ID_GRR__ack_nack_des__f_ack_ind,
3023 /* 3005*/ CCD_ID_GRR__ack_nack_des__ssn,
3024 /* 3006*/ CCD_ID_GRR__ack_nack_des__rbb,
3025 /* 3007*/ CCD_ID_GRR__ms_id__ms_id_len,
3026 /* 3008*/ CCD_ID_GRR__ms_id__ident_digit,
3027 /* 3009*/ CCD_ID_GRR__rep_page_s2__flag,
3028 /* 3010*/ CCD_ID_GRR__rep_page_s2__tmsi_field,
3029 /* 3011*/ CCD_ID_GRR__rep_page_s2__ms_id,
3030 /* 3012*/ CCD_ID_GRR__rep_page_s2__chan_need,
3031 /* 3013*/ CCD_ID_GRR__rep_page_s2__emlpp_prio,
3032 /* 3014*/ CCD_ID_GRR__rep_page_s1__flag,
3033 /* 3015*/ CCD_ID_GRR__rep_page_s1__ptmsi,
3034 /* 3016*/ CCD_ID_GRR__rep_page_s1__ms_id,
3035 /* 3017*/ CCD_ID_GRR__rep_page_info__flag,
3036 /* 3018*/ CCD_ID_GRR__rep_page_info__rep_page_s1,
3037 /* 3019*/ CCD_ID_GRR__rep_page_info__rep_page_s2,
3038 /* 3020*/ CCD_ID_GRR__abs__t1,
3039 /* 3021*/ CCD_ID_GRR__abs__t3,
3040 /* 3022*/ CCD_ID_GRR__abs__t2,
3041 /* 3023*/ CCD_ID_GRR__tbf_s_time__flag,
3042 /* 3024*/ CCD_ID_GRR__tbf_s_time__rel,
3043 /* 3025*/ CCD_ID_GRR__tbf_s_time__abs,
3044 /* 3026*/ CCD_ID_GRR__meas_map__meas_start_grr,
3045 /* 3027*/ CCD_ID_GRR__meas_map__meas_inter,
3046 /* 3028*/ CCD_ID_GRR__meas_map__meas_bitmap,
3047 /* 3029*/ CCD_ID_GRR__fa_s2__tbf_s_time,
3048 /* 3030*/ CCD_ID_GRR__fa_s2__ts_alloc,
3049 /* 3031*/ CCD_ID_GRR__fa_s2__spare_0,
3050 /* 3032*/ CCD_ID_GRR__fa_s2__flag,
3051 /* 3033*/ CCD_ID_GRR__fa_s2__block_struct,
3052 /* 3034*/ CCD_ID_GRR__fa_s2__alloc_map,
3053 /* 3035*/ CCD_ID_GRR__f_alloc_ack__final_alloc,
3054 /* 3036*/ CCD_ID_GRR__f_alloc_ack__flag,
3055 /* 3037*/ CCD_ID_GRR__f_alloc_ack__ts_overr,
3056 /* 3038*/ CCD_ID_GRR__f_alloc_ack__fa_s2,
3057 /* 3039*/ CCD_ID_GRR__req_ref_p__access_info,
3058 /* 3040*/ CCD_ID_GRR__req_ref_p__fn_mod,
3059 /* 3041*/ CCD_ID_GRR__add3__flag,
3060 /* 3042*/ CCD_ID_GRR__add3__glob_tfi,
3061 /* 3043*/ CCD_ID_GRR__add3__flag2,
3062 /* 3044*/ CCD_ID_GRR__add3__tlli_value,
3063 /* 3045*/ CCD_ID_GRR__add3__flag3,
3064 /* 3046*/ CCD_ID_GRR__add3__tqi,
3065 /* 3047*/ CCD_ID_GRR__add3__req_ref_p,
3066 /* 3048*/ CCD_ID_GRR__req_ref_tfi__flag,
3067 /* 3049*/ CCD_ID_GRR__req_ref_tfi__req_ref_p,
3068 /* 3050*/ CCD_ID_GRR__req_ref_tfi__glob_tfi,
3069 /* 3051*/ CCD_ID_GRR__reject__flag,
3070 /* 3052*/ CCD_ID_GRR__reject__tlli_value,
3071 /* 3053*/ CCD_ID_GRR__reject__req_ref_tfi,
3072 /* 3054*/ CCD_ID_GRR__reject__wait,
3073 /* 3055*/ CCD_ID_GRR__gamma_tn__gamma,
3074 /* 3056*/ CCD_ID_GRR__pwr_par__alpha,
3075 /* 3057*/ CCD_ID_GRR__pwr_par__gamma_tn,
3076 /* 3058*/ CCD_ID_GRR__f_alloc_ul__ul_tfi_assign,
3077 /* 3059*/ CCD_ID_GRR__f_alloc_ul__final_alloc,
3078 /* 3060*/ CCD_ID_GRR__f_alloc_ul__dl_ctrl_ts,
3079 /* 3061*/ CCD_ID_GRR__f_alloc_ul__bts_pwr_ctrl,
3080 /* 3062*/ CCD_ID_GRR__f_alloc_ul__flag,
3081 /* 3063*/ CCD_ID_GRR__f_alloc_ul__ts_alloc,
3082 /* 3064*/ CCD_ID_GRR__f_alloc_ul__pwr_par,
3083 /* 3065*/ CCD_ID_GRR__f_alloc_ul__half_dupelx,
3084 /* 3066*/ CCD_ID_GRR__f_alloc_ul__tbf_s_time,
3085 /* 3067*/ CCD_ID_GRR__f_alloc_ul__spare_0,
3086 /* 3068*/ CCD_ID_GRR__f_alloc_ul__flag2,
3087 /* 3069*/ CCD_ID_GRR__f_alloc_ul__block_struct,
3088 /* 3070*/ CCD_ID_GRR__f_alloc_ul__alloc_map,
3089 /* 3071*/ CCD_ID_GRR__f_alloc_re__flag,
3090 /* 3072*/ CCD_ID_GRR__f_alloc_re__ul_ts_alloc,
3091 /* 3073*/ CCD_ID_GRR__f_alloc_re__pwr_par,
3092 /* 3074*/ CCD_ID_GRR__f_alloc_re__final_alloc,
3093 /* 3075*/ CCD_ID_GRR__f_alloc_re__dl_ctrl_ts,
3094 /* 3076*/ CCD_ID_GRR__f_alloc_re__bts_pwr_ctrl,
3095 /* 3077*/ CCD_ID_GRR__f_alloc_re__meas_map,
3096 /* 3078*/ CCD_ID_GRR__f_alloc_re__tbf_s_time,
3097 /* 3079*/ CCD_ID_GRR__f_alloc_re__spare_0,
3098 /* 3080*/ CCD_ID_GRR__f_alloc_re__flag2,
3099 /* 3081*/ CCD_ID_GRR__f_alloc_re__block_struct,
3100 /* 3082*/ CCD_ID_GRR__f_alloc_re__alloc_map,
3101 /* 3083*/ CCD_ID_GRR__usf_array__usf_g,
3102 /* 3084*/ CCD_ID_GRR__tn_alloc_pwr__alpha,
3103 /* 3085*/ CCD_ID_GRR__tn_alloc_pwr__usf_array,
3104 /* 3086*/ CCD_ID_GRR__dyn_alloc_p__xdyn_alloc,
3105 /* 3087*/ CCD_ID_GRR__dyn_alloc_p__flag2,
3106 /* 3088*/ CCD_ID_GRR__dyn_alloc_p__p0,
3107 /* 3089*/ CCD_ID_GRR__dyn_alloc_p__pr_mode,
3108 /* 3090*/ CCD_ID_GRR__dyn_alloc_p__usf_grant,
3109 /* 3091*/ CCD_ID_GRR__dyn_alloc_p__ul_tfi_assign,
3110 /* 3092*/ CCD_ID_GRR__dyn_alloc_p__rlc_db_granted,
3111 /* 3093*/ CCD_ID_GRR__dyn_alloc_p__tbf_s_time,
3112 /* 3094*/ CCD_ID_GRR__dyn_alloc_p__flag,
3113 /* 3095*/ CCD_ID_GRR__dyn_alloc_p__tn_alloc,
3114 /* 3096*/ CCD_ID_GRR__dyn_alloc_p__tn_alloc_pwr,
3115 /* 3097*/ CCD_ID_GRR__alf_gam__alpha,
3116 /* 3098*/ CCD_ID_GRR__alf_gam__gamma,
3117 /* 3099*/ CCD_ID_GRR__sin_alloc__tn,
3118 /* 3100*/ CCD_ID_GRR__sin_alloc__alf_gam,
3119 /* 3101*/ CCD_ID_GRR__sin_alloc__bts_pwr_ctrl,
3120 /* 3102*/ CCD_ID_GRR__sin_alloc__tbf_s_time,
3121 /* 3103*/ CCD_ID_GRR__freq_diff_struct__freq_diff,
3122 /* 3104*/ CCD_ID_GRR__xfreq_list__start_freq,
3123 /* 3105*/ CCD_ID_GRR__xfreq_list__nr_freq,
3124 /* 3106*/ CCD_ID_GRR__xfreq_list__freq_diff_len,
3125 /* 3107*/ CCD_ID_GRR__xfreq_list__freq_diff_struct,
3126 /* 3108*/ CCD_ID_GRR__em1__flag,
3127 /* 3109*/ CCD_ID_GRR__em1__xrep_type,
3128 /* 3110*/ CCD_ID_GRR__em1__ncc_permitted,
3129 /* 3111*/ CCD_ID_GRR__em1__int_freq,
3130 /* 3112*/ CCD_ID_GRR__em1__xrep_per,
3131 /* 3113*/ CCD_ID_GRR__em1__xfreq_list,
3132 /* 3114*/ CCD_ID_GRR__em1__xfreq_list2,
3133 /* 3115*/ CCD_ID_GRR__xmeas_par__xmeas_order,
3134 /* 3116*/ CCD_ID_GRR__xmeas_par__em1,
3135 /* 3117*/ CCD_ID_GRR__ncell_par_rest__freq_diff_struct,
3136 /* 3118*/ CCD_ID_GRR__ncell_par_rest__bsic,
3137 /* 3119*/ CCD_ID_GRR__ncell_par_rest__cs_par,
3138 /* 3120*/ CCD_ID_GRR__ncell_par__start_freq,
3139 /* 3121*/ CCD_ID_GRR__ncell_par__bsic,
3140 /* 3122*/ CCD_ID_GRR__ncell_par__cs_par,
3141 /* 3123*/ CCD_ID_GRR__ncell_par__n_rest,
3142 /* 3124*/ CCD_ID_GRR__ncell_par__freq_diff_len,
3143 /* 3125*/ CCD_ID_GRR__ncell_par__ncell_par_rest,
3144 /* 3126*/ CCD_ID_GRR__afreq_s__freq_diff_struct,
3145 /* 3127*/ CCD_ID_GRR__afreq_s__bsic,
3146 /* 3128*/ CCD_ID_GRR__afreq_s__cs_par,
3147 /* 3129*/ CCD_ID_GRR__list_af__start_freq,
3148 /* 3130*/ CCD_ID_GRR__list_af__bsic,
3149 /* 3131*/ CCD_ID_GRR__list_af__cs_par,
3150 /* 3132*/ CCD_ID_GRR__list_af__nr_freq,
3151 /* 3133*/ CCD_ID_GRR__list_af__freq_diff_len,
3152 /* 3134*/ CCD_ID_GRR__list_af__afreq_s,
3153 /* 3135*/ CCD_ID_GRR__nc_freq_list__list_rf,
3154 /* 3136*/ CCD_ID_GRR__nc_freq_list__list_af,
3155 /* 3137*/ CCD_ID_GRR__dyn_alloc_ts__xdyn_alloc,
3156 /* 3138*/ CCD_ID_GRR__dyn_alloc_ts__flag2,
3157 /* 3139*/ CCD_ID_GRR__dyn_alloc_ts__p0,
3158 /* 3140*/ CCD_ID_GRR__dyn_alloc_ts__pr_mode,
3159 /* 3141*/ CCD_ID_GRR__dyn_alloc_ts__usf_grant,
3160 /* 3142*/ CCD_ID_GRR__dyn_alloc_ts__rlc_db_granted,
3161 /* 3143*/ CCD_ID_GRR__dyn_alloc_ts__tbf_s_time,
3162 /* 3144*/ CCD_ID_GRR__dyn_alloc_ts__flag,
3163 /* 3145*/ CCD_ID_GRR__dyn_alloc_ts__tn_alloc,
3164 /* 3146*/ CCD_ID_GRR__dyn_alloc_ts__tn_alloc_pwr,
3165 /* 3147*/ CCD_ID_GRR__add_psi__non_gsm_info,
3166 /* 3148*/ CCD_ID_GRR__add_psi__Psi8_broadcast,
3167 /* 3149*/ CCD_ID_GRR__add_psi__psi3ter_broadcast,
3168 /* 3150*/ CCD_ID_GRR__add_psi__psi3quater_broadcast,
3169 /* 3151*/ CCD_ID_GRR__report_900_grr__rep_offset_900,
3170 /* 3152*/ CCD_ID_GRR__report_900_grr__rep_thres_900,
3171 /* 3153*/ CCD_ID_GRR__report_1800_grr__rep_offset_1800,
3172 /* 3154*/ CCD_ID_GRR__report_1800_grr__rep_thres_1800,
3173 /* 3155*/ CCD_ID_GRR__report_400_grr__rep_offset_400,
3174 /* 3156*/ CCD_ID_GRR__report_400_grr__rep_thres_400,
3175 /* 3157*/ CCD_ID_GRR__report_1900_grr__rep_offset_1900,
3176 /* 3158*/ CCD_ID_GRR__report_1900_grr__rep_thres_1900,
3177 /* 3159*/ CCD_ID_GRR__report_850_grr__rep_offset_850,
3178 /* 3160*/ CCD_ID_GRR__report_850_grr__rep_thres_850,
3179 /* 3161*/ CCD_ID_GRR__fdd_multi_report__fdd_rep_quant,
3180 /* 3162*/ CCD_ID_GRR__fdd_multi_report__fdd_multi_rep,
3181 /* 3163*/ CCD_ID_GRR__gprs_meas_par_report__multi_band_rep,
3182 /* 3164*/ CCD_ID_GRR__gprs_meas_par_report__serv_cell_rep,
3183 /* 3165*/ CCD_ID_GRR__gprs_meas_par_report__scale_ord,
3184 /* 3166*/ CCD_ID_GRR__gprs_meas_par_report__report_900_grr,
3185 /* 3167*/ CCD_ID_GRR__gprs_meas_par_report__report_1800_grr,
3186 /* 3168*/ CCD_ID_GRR__gprs_meas_par_report__report_400_grr,
3187 /* 3169*/ CCD_ID_GRR__gprs_meas_par_report__report_1900_grr,
3188 /* 3170*/ CCD_ID_GRR__gprs_meas_par_report__report_850_grr,
3189 /* 3171*/ CCD_ID_GRR__gprs_meas_par_desc_meas__multi_band_rep,
3190 /* 3172*/ CCD_ID_GRR__gprs_meas_par_desc_meas__serv_cell_rep,
3191 /* 3173*/ CCD_ID_GRR__gprs_meas_par_desc_meas__scale_ord,
3192 /* 3174*/ CCD_ID_GRR__gprs_meas_par_desc_meas__report_900_grr,
3193 /* 3175*/ CCD_ID_GRR__gprs_meas_par_desc_meas__report_1800_grr,
3194 /* 3176*/ CCD_ID_GRR__gprs_meas_par_desc_meas__report_400_grr,
3195 /* 3177*/ CCD_ID_GRR__gprs_meas_par_desc_meas__report_1900_grr,
3196 /* 3178*/ CCD_ID_GRR__gprs_meas_par_desc_meas__report_850_grr,
3197 /* 3179*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__fdd_multi_report,
3198 /* 3180*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__fdd_report,
3199 /* 3181*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__tdd_multirat_rep,
3200 /* 3182*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__tdd_rep,
3201 /* 3183*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__cdma2000_multirat_rep,
3202 /* 3184*/ CCD_ID_GRR__gprs_3g_meas_par_desc_pmo__cdma2000_rep,
3203 /* 3185*/ CCD_ID_GRR__gprs_3g_meas_par_desc__fdd_multi_report,
3204 /* 3186*/ CCD_ID_GRR__gprs_3g_meas_par_desc__fdd_report,
3205 /* 3187*/ CCD_ID_GRR__gprs_3g_meas_par_desc__tdd_multirat_rep,
3206 /* 3188*/ CCD_ID_GRR__gprs_3g_meas_par_desc__tdd_rep,
3207 /* 3189*/ CCD_ID_GRR__enh_rep_param_struct__reporting_type,
3208 /* 3190*/ CCD_ID_GRR__enh_rep_param_struct__reporting_rate,
3209 /* 3191*/ CCD_ID_GRR__enh_rep_param_struct__invalid_bsic_rep,
3210 /* 3192*/ CCD_ID_GRR__enh_rep_param_struct__ncc_permitted,
3211 /* 3193*/ CCD_ID_GRR__enh_rep_param_struct__gprs_meas_par_report,
3212 /* 3194*/ CCD_ID_GRR__enh_rep_param_struct__gprs_3g_meas_par_desc,
3213 /* 3195*/ CCD_ID_GRR__utran_fdd_grr__fdd_arfcn,
3214 /* 3196*/ CCD_ID_GRR__utran_fdd_grr__diversity,
3215 /* 3197*/ CCD_ID_GRR__utran_fdd_grr__bandwidth_fdd,
3216 /* 3198*/ CCD_ID_GRR__utran_fdd_grr__scrambl_codes,
3217 /* 3199*/ CCD_ID_GRR__utran_tdd_grr__tdd_arfcn,
3218 /* 3200*/ CCD_ID_GRR__utran_tdd_grr__diversity,
3219 /* 3201*/ CCD_ID_GRR__utran_tdd_grr__bandwidth_tdd,
3220 /* 3202*/ CCD_ID_GRR__utran_tdd_grr__cell_par,
3221 /* 3203*/ CCD_ID_GRR__utran_tdd_grr__sync_case,
3222 /* 3204*/ CCD_ID_GRR__target_cell_3g__utran_fdd_grr,
3223 /* 3205*/ CCD_ID_GRR__target_cell_3g__utran_tdd_grr,
3224 /* 3206*/ CCD_ID_GRR__n2_struct__rem_cell_index_3g,
3225 /* 3207*/ CCD_ID_GRR__n2_struct__cell_diff_len_3g,
3226 /* 3208*/ CCD_ID_GRR__n2_struct__cell_diff_3g,
3227 /* 3209*/ CCD_ID_GRR__n1_struct__n2,
3228 /* 3210*/ CCD_ID_GRR__n1_struct__n2_struct,
3229 /* 3211*/ CCD_ID_GRR__rem_3g_cell_desc__n1,
3230 /* 3212*/ CCD_ID_GRR__rem_3g_cell_desc__n1_struct,
3231 /* 3213*/ CCD_ID_GRR__gprs_rep_prio_cell_desc__number_cells,
3232 /* 3214*/ CCD_ID_GRR__gprs_rep_prio_cell_desc__rep_prio,
3233 /* 3215*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pmo__qsearch_p,
3234 /* 3216*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pmo__search_prio_3g,
3235 /* 3217*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pmo__gprs_3g_meas_par_desc_pmo,
3236 /* 3218*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pcco__qsearch_p,
3237 /* 3219*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pcco__search_prio_3g,
3238 /* 3220*/ CCD_ID_GRR__gprs_3g_meas_par_desc_ext_pcco__gprs_3g_meas_par_desc,
3239 /* 3221*/ CCD_ID_GRR__fdd_info_ded__fdd_qoffset,
3240 /* 3222*/ CCD_ID_GRR__fdd_info_ded__fdd_rep_quant,
3241 /* 3223*/ CCD_ID_GRR__fdd_info_ded__fdd_multi_rep,
3242 /* 3224*/ CCD_ID_GRR__tdd_info_ded__tdd_qoffset,
3243 /* 3225*/ CCD_ID_GRR__tdd_info_ded__tdd_multirat_rep,
3244 /* 3226*/ CCD_ID_GRR__init_ded_mod_rep_desc_3g__ba_ind_used_3g,
3245 /* 3227*/ CCD_ID_GRR__init_ded_mod_rep_desc_3g__qsearch_i,
3246 /* 3228*/ CCD_ID_GRR__init_ded_mod_rep_desc_3g__qsearch_C_init,
3247 /* 3229*/ CCD_ID_GRR__init_ded_mod_rep_desc_3g__fdd_info_ded,
3248 /* 3230*/ CCD_ID_GRR__init_ded_mod_rep_desc_3g__tdd_info_ded,
3249 /* 3231*/ CCD_ID_GRR__ba_psi3_str__flag,
3250 /* 3232*/ CCD_ID_GRR__ba_psi3_str__psi3_cm,
3251 /* 3233*/ CCD_ID_GRR__ba_psi3_str__ba_ind_used,
3252 /* 3234*/ CCD_ID_GRR__ba_psi3_str__ba_ind_used_3g,
3253 /* 3235*/ CCD_ID_GRR__ba_psi3_str__pmo_ind_used,
3254 /* 3236*/ CCD_ID_GRR__cell_list_3g__cell_list_3g_index,
3255 /* 3237*/ CCD_ID_GRR__cell_list_3g__reporting_quantity,
3256 /* 3238*/ CCD_ID_GRR__meas_rep_3g_str__n_3g,
3257 /* 3239*/ CCD_ID_GRR__meas_rep_3g_str__cell_list_3g,
3258 /* 3240*/ CCD_ID_GRR__fdd_info_grr__fdd_gprs_qoffset,
3259 /* 3241*/ CCD_ID_GRR__fdd_info_grr__fdd_qmin,
3260 /* 3242*/ CCD_ID_GRR__gprs_3g_meas_par_desc_qua__qsearch_p,
3261 /* 3243*/ CCD_ID_GRR__gprs_3g_meas_par_desc_qua__search_prio_3g,
3262 /* 3244*/ CCD_ID_GRR__gprs_3g_meas_par_desc_qua__fdd_info_grr,
3263 /* 3245*/ CCD_ID_GRR__gprs_3g_meas_par_desc_qua__tdd_gprs_qoffset,
3264 /* 3246*/ CCD_ID_GRR__cbch_chan_desc__chan_typ_tdma_offset,
3265 /* 3247*/ CCD_ID_GRR__cbch_chan_desc__tn,
3266 /* 3248*/ CCD_ID_GRR__cbch_chan_desc__freq_par,
3267 /* 3249*/ CCD_ID_GRR__serv_cell_data__rxlev_scell,
3268 /* 3250*/ CCD_ID_GRR__serv_cell_data__i_scell,
3269 /* 3251*/ CCD_ID_GRR__rep_invalid_bsic_info__bcch_freq_ncell,
3270 /* 3252*/ CCD_ID_GRR__rep_invalid_bsic_info__bsic,
3271 /* 3253*/ CCD_ID_GRR__rep_invalid_bsic_info__rxlev_ncell,
3272 /* 3254*/ CCD_ID_GRR__non_gprs_ext_info__ecsc,
3273 /* 3255*/ CCD_ID_GRR__non_gprs_ext_info__ecsr_3g,
3274 /* 3256*/ CCD_ID_GRR__lsa_id_struct__flag,
3275 /* 3257*/ CCD_ID_GRR__lsa_id_struct__lsa_id,
3276 /* 3258*/ CCD_ID_GRR__lsa_id_struct__short_lsa_id,
3277 /* 3259*/ CCD_ID_GRR__serv_cell_lsa_id_info__lsa_id_struct,
3278 /* 3260*/ CCD_ID_GRR__lsa_param2__nr_of_freq_or_cells,
3279 /* 3261*/ CCD_ID_GRR__lsa_param2__serv_cell_lsa_id_info,
3280 /* 3262*/ CCD_ID_GRR__egprs_link_adpt_para__egprs_ws,
3281 /* 3263*/ CCD_ID_GRR__egprs_link_adpt_para__lqm_mode,
3282 /* 3264*/ CCD_ID_GRR__egprs_link_adpt_para__bep_period2,
3283 /* 3265*/ CCD_ID_GRR__compact_red_ma__length_reduced_bitmap,
3284 /* 3266*/ CCD_ID_GRR__compact_red_ma__reduced_ma_bitmap,
3285 /* 3267*/ CCD_ID_GRR__compact_red_ma__maio_2,
3286 /* 3268*/ CCD_ID_GRR__num_idle_blks_str__nib_ccch_0,
3287 /* 3269*/ CCD_ID_GRR__num_idle_blks_str__nib_ccch_1,
3288 /* 3270*/ CCD_ID_GRR__num_idle_blks_str__nib_ccch_2,
3289 /* 3271*/ CCD_ID_GRR__num_idle_blks_str__nib_ccch_3,
3290 /* 3272*/ CCD_ID_GRR__compact_ctrl_info__large_cell_operation,
3291 /* 3273*/ CCD_ID_GRR__compact_ctrl_info__num_idle_blks_str,
3292 /* 3274*/ CCD_ID_GRR__compact_ctrl_info__n_ccch_nh,
3293 /* 3275*/ CCD_ID_GRR__compact_cell_sel_str__bsic,
3294 /* 3276*/ CCD_ID_GRR__compact_cell_sel_str__cell_ba,
3295 /* 3277*/ CCD_ID_GRR__compact_cell_sel_str__exc_acc,
3296 /* 3278*/ CCD_ID_GRR__compact_cell_sel_str__same_ra_scell,
3297 /* 3279*/ CCD_ID_GRR__compact_cell_sel_str__cs_par_s1,
3298 /* 3280*/ CCD_ID_GRR__compact_cell_sel_str__cs_par_s2,
3299 /* 3281*/ CCD_ID_GRR__compact_cell_sel_str__gprs_resel_off,
3300 /* 3282*/ CCD_ID_GRR__compact_cell_sel_str__hcs_par,
3301 /* 3283*/ CCD_ID_GRR__compact_cell_sel_str__time_grp,
3302 /* 3284*/ CCD_ID_GRR__compact_cell_sel_str__guar_const_pwr_grp,
3303 /* 3285*/ CCD_ID_GRR__freq_diff_and_com_param__freq_diff_struct_2,
3304 /* 3286*/ CCD_ID_GRR__freq_diff_and_com_param__compact_cell_sel_str,
3305 /* 3287*/ CCD_ID_GRR__compact_neighbour_cell_str__start_freq,
3306 /* 3288*/ CCD_ID_GRR__compact_neighbour_cell_str__compact_cell_sel_str,
3307 /* 3289*/ CCD_ID_GRR__compact_neighbour_cell_str__n_rest,
3308 /* 3290*/ CCD_ID_GRR__compact_neighbour_cell_str__freq_diff_len,
3309 /* 3291*/ CCD_ID_GRR__compact_neighbour_cell_str__freq_diff_and_com_param,
3310 /* 3292*/ CCD_ID_GRR__compact_info_str__cell_id,
3311 /* 3293*/ CCD_ID_GRR__compact_info_str__compact_neighbour_cell_str,
3312 /* 3294*/ CCD_ID_GRR__compact_neighbour_param_set_str__ncc,
3313 /* 3295*/ CCD_ID_GRR__compact_neighbour_param_set_str__exc_acc,
3314 /* 3296*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_rxlev_access_min,
3315 /* 3297*/ CCD_ID_GRR__compact_neighbour_param_set_str__txpwr_max_cch,
3316 /* 3298*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_prio_class,
3317 /* 3299*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_hcs_thr,
3318 /* 3300*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_temp_offset,
3319 /* 3301*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_penalty_time,
3320 /* 3302*/ CCD_ID_GRR__compact_neighbour_param_set_str__gprs_resel_off,
3321 /* 3303*/ CCD_ID_GRR__compact_neighbour_param_set_str__guar_const_pwr_grp,
3322 /* 3304*/ CCD_ID_GRR__compact_ncp2_prop_struct__freq_diff_struct,
3323 /* 3305*/ CCD_ID_GRR__compact_ncp2_prop_struct__same_ra_scell,
3324 /* 3306*/ CCD_ID_GRR__compact_ncp2_prop_struct__cell_ba,
3325 /* 3307*/ CCD_ID_GRR__compact_ncp2_prop_struct__bcc,
3326 /* 3308*/ CCD_ID_GRR__compact_ncp2_prop_struct__time_grp,
3327 /* 3309*/ CCD_ID_GRR__comp_ncp2_rep_struct__start_freq,
3328 /* 3310*/ CCD_ID_GRR__comp_ncp2_rep_struct__same_ra_scell,
3329 /* 3311*/ CCD_ID_GRR__comp_ncp2_rep_struct__cell_ba,
3330 /* 3312*/ CCD_ID_GRR__comp_ncp2_rep_struct__bcc,
3331 /* 3313*/ CCD_ID_GRR__comp_ncp2_rep_struct__time_grp,
3332 /* 3314*/ CCD_ID_GRR__comp_ncp2_rep_struct__n_r_cells,
3333 /* 3315*/ CCD_ID_GRR__comp_ncp2_rep_struct__freq_diff_len,
3334 /* 3316*/ CCD_ID_GRR__comp_ncp2_rep_struct__compact_ncp2_prop_struct,
3335 /* 3317*/ CCD_ID_GRR__compact_ncp2_str__comp_ncp2_rep_struct,
3336 /* 3318*/ CCD_ID_GRR__compact_ncp2_str__para_ptr,
3337 /* 3319*/ CCD_ID_GRR__compact_neighbour_cell_param__flag,
3338 /* 3320*/ CCD_ID_GRR__compact_neighbour_cell_param__flag2,
3339 /* 3321*/ CCD_ID_GRR__compact_neighbour_cell_param__compact_ncp2_str,
3340 /* 3322*/ CCD_ID_GRR__compact_neighbour_cell_param__compact_neighbour_param_set_str,
3341 /* 3323*/ CCD_ID_GRR__nc_meas_per__non_drx_per,
3342 /* 3324*/ CCD_ID_GRR__nc_meas_per__rep_per_i,
3343 /* 3325*/ CCD_ID_GRR__nc_meas_per__rep_per_t,
3344 /* 3326*/ CCD_ID_GRR__nc_meas_par__ctrl_order,
3345 /* 3327*/ CCD_ID_GRR__nc_meas_par__nc_meas_per,
3346 /* 3328*/ CCD_ID_GRR__nc_meas_par_list__nc_meas_par,
3347 /* 3329*/ CCD_ID_GRR__nc_meas_par_list__nc_freq_list,
3348 /* 3330*/ CCD_ID_GRR__non_gprs_ext_bits__ext_len,
3349 /* 3331*/ CCD_ID_GRR__non_gprs_ext_bits__non_gprs_ext_info,
3350 /* 3332*/ CCD_ID_GRR__non_gprs_opt__att,
3351 /* 3333*/ CCD_ID_GRR__non_gprs_opt__t3212,
3352 /* 3334*/ CCD_ID_GRR__non_gprs_opt__neci,
3353 /* 3335*/ CCD_ID_GRR__non_gprs_opt__pwcr,
3354 /* 3336*/ CCD_ID_GRR__non_gprs_opt__dtx,
3355 /* 3337*/ CCD_ID_GRR__non_gprs_opt__rl_timeout,
3356 /* 3338*/ CCD_ID_GRR__non_gprs_opt__bs_ag_blks_res,
3357 /* 3339*/ CCD_ID_GRR__non_gprs_opt__ccch_conf,
3358 /* 3340*/ CCD_ID_GRR__non_gprs_opt__bs_pa_mfrms,
3359 /* 3341*/ CCD_ID_GRR__non_gprs_opt__max_retrans,
3360 /* 3342*/ CCD_ID_GRR__non_gprs_opt__tx_integer,
3361 /* 3343*/ CCD_ID_GRR__non_gprs_opt__ec,
3362 /* 3344*/ CCD_ID_GRR__non_gprs_opt__txpwr_max_cch,
3363 /* 3345*/ CCD_ID_GRR__non_gprs_opt__ext_bits,
3364 /* 3346*/ CCD_ID_GRR__non_gprs_opt__non_gprs_ext_bits,
3365 /* 3347*/ CCD_ID_GRR__ncell_par2_s2__freq_diff_struct,
3366 /* 3348*/ CCD_ID_GRR__ncell_par2_s2__same_ra_scell,
3367 /* 3349*/ CCD_ID_GRR__ncell_par2_s2__cell_ba,
3368 /* 3350*/ CCD_ID_GRR__ncell_par2_s2__bcc,
3369 /* 3351*/ CCD_ID_GRR__ncell_par2_s1__start_freq,
3370 /* 3352*/ CCD_ID_GRR__ncell_par2_s1__same_ra_scell,
3371 /* 3353*/ CCD_ID_GRR__ncell_par2_s1__cell_ba,
3372 /* 3354*/ CCD_ID_GRR__ncell_par2_s1__bcc,
3373 /* 3355*/ CCD_ID_GRR__ncell_par2_s1__n_r_cells,
3374 /* 3356*/ CCD_ID_GRR__ncell_par2_s1__freq_diff_len,
3375 /* 3357*/ CCD_ID_GRR__ncell_par2_s1__ncell_par2_s2,
3376 /* 3358*/ CCD_ID_GRR__ncell_par2_des__ncell_par2_s1,
3377 /* 3359*/ CCD_ID_GRR__ncell_par2_des__para_ptr,
3378 /* 3360*/ CCD_ID_GRR__ncell_par2__generation,
3379 /* 3361*/ CCD_ID_GRR__ncell_par2__ncell_par2_des,
3380 /* 3362*/ CCD_ID_GRR__ncell_par2__ncell_par2_set,
3381 /* 3363*/ CCD_ID_GRR__neighbour_cell_desc_3g_pmo__threeg_cells,
3382 /* 3364*/ CCD_ID_GRR__neighbour_cell_desc_3g_pmo__cdma2000_cell_desc,
3383 /* 3365*/ CCD_ID_GRR__neighbour_cell_desc_3g_pmo__rem_3g_cell_desc,
3384 /* 3366*/ CCD_ID_GRR__enh_meas_param_pmo__ba_psi3_str,
3385 /* 3367*/ CCD_ID_GRR__enh_meas_param_pmo__reporting_type,
3386 /* 3368*/ CCD_ID_GRR__enh_meas_param_pmo__reporting_rate,
3387 /* 3369*/ CCD_ID_GRR__enh_meas_param_pmo__invalid_bsic_rep,
3388 /* 3370*/ CCD_ID_GRR__enh_meas_param_pmo__neighbour_cell_desc_3g_pmo,
3389 /* 3371*/ CCD_ID_GRR__enh_meas_param_pmo__gprs_rep_prio_cell_desc,
3390 /* 3372*/ CCD_ID_GRR__enh_meas_param_pmo__gprs_meas_par_desc_meas,
3391 /* 3373*/ CCD_ID_GRR__enh_meas_param_pmo__gprs_3g_meas_par_desc_ext_pmo,
3392 /* 3374*/ CCD_ID_GRR__neighbour_cell_desc_3g_pcco__threeg_cells,
3393 /* 3375*/ CCD_ID_GRR__neighbour_cell_desc_3g_pcco__rem_3g_cell_desc,
3394 /* 3376*/ CCD_ID_GRR__enh_meas_param_pcco__ba_psi3_str,
3395 /* 3377*/ CCD_ID_GRR__enh_meas_param_pcco__reporting_type,
3396 /* 3378*/ CCD_ID_GRR__enh_meas_param_pcco__reporting_rate,
3397 /* 3379*/ CCD_ID_GRR__enh_meas_param_pcco__invalid_bsic_rep,
3398 /* 3380*/ CCD_ID_GRR__enh_meas_param_pcco__neighbour_cell_desc_3g_pcco,
3399 /* 3381*/ CCD_ID_GRR__enh_meas_param_pcco__gprs_rep_prio_cell_desc,
3400 /* 3382*/ CCD_ID_GRR__enh_meas_param_pcco__gprs_meas_par_desc_meas,
3401 /* 3383*/ CCD_ID_GRR__enh_meas_param_pcco__gprs_3g_meas_par_desc_ext_pcco,
3402 /* 3384*/ CCD_ID_GRR__reporting_quantity_bmp__reporting_quantity,
3403 /* 3385*/ CCD_ID_GRR__nc_rep_quan__reporting_quantity_bmp,
3404 /* 3386*/ CCD_ID_GRR__nc_meas_rep_enh__nc_mode,
3405 /* 3387*/ CCD_ID_GRR__nc_meas_rep_enh__ba_psi3_str,
3406 /* 3388*/ CCD_ID_GRR__nc_meas_rep_enh__bsic_seen,
3407 /* 3389*/ CCD_ID_GRR__nc_meas_rep_enh__scale,
3408 /* 3390*/ CCD_ID_GRR__nc_meas_rep_enh__serv_cell_data,
3409 /* 3391*/ CCD_ID_GRR__nc_meas_rep_enh__rep_invalid_bsic_info,
3410 /* 3392*/ CCD_ID_GRR__nc_meas_rep_enh__nc_rep_quan,
3411 /* 3393*/ CCD_ID_GRR__rtd6_struct__rtd_6bit,
3412 /* 3394*/ CCD_ID_GRR__rtd6_struct_opt_array__rtd_6bit,
3413 /* 3395*/ CCD_ID_GRR__rtd_struct_6bit__cell_index_start_rtd,
3414 /* 3396*/ CCD_ID_GRR__rtd_struct_6bit__rtd6_struct,
3415 /* 3397*/ CCD_ID_GRR__rtd_struct_6bit__rtd6_struct_opt_array,
3416 /* 3398*/ CCD_ID_GRR__rtd12_struct__rtd_12bit,
3417 /* 3399*/ CCD_ID_GRR__rtd12_struct_opt_array__rtd_12bit,
3418 /* 3400*/ CCD_ID_GRR__rtd_struct_12bit__cell_index_start_rtd,
3419 /* 3401*/ CCD_ID_GRR__rtd_struct_12bit__rtd12_struct,
3420 /* 3402*/ CCD_ID_GRR__rtd_struct_12bit__rtd12_struct_opt_array,
3421 /* 3403*/ CCD_ID_GRR__real_time_diff__rtd_struct_6bit,
3422 /* 3404*/ CCD_ID_GRR__real_time_diff__rtd_struct_12bit,
3423 /* 3405*/ CCD_ID_GRR__release_99_str__compact_neighbour_cell_param,
3424 /* 3406*/ CCD_ID_GRR__release_99_str__spare_0,
3425 /* 3407*/ CCD_ID_GRR__release_98_str__lsa_param2,
3426 /* 3408*/ CCD_ID_GRR__release_98_str__release_99_str,
3427 /* 3409*/ CCD_ID_GRR__ncell_par_trnc_grp__ncell_par,
3428 /* 3410*/ CCD_ID_GRR__ncell_par_trnc_grp__ncell_par2,
3429 /* 3411*/ CCD_ID_GRR__ncell_par_trnc_grp__release_98_str,
3430 /* 3412*/ CCD_ID_GRR__rtd_rep_prio_trnc_grp__real_time_diff,
3431 /* 3413*/ CCD_ID_GRR__rtd_rep_prio_trnc_grp__gprs_rep_prio_cell_desc,
3432 /* 3414*/ CCD_ID_GRR__psi_3_qua_trnc_grp__gprs_rep_prio_cell_desc,
3433 /* 3415*/ CCD_ID_GRR__psi_3_qua_trnc_grp__threeg_cells,
3434 /* 3416*/ CCD_ID_GRR__psi_3_qua_trnc_grp__gprs_3g_meas_par_desc_qua,
3435 /* 3417*/ CCD_ID_GRR__psi_3_qua_trnc_grp__init_ded_mod_rep_desc_3g,
3436 /* 3418*/ CCD_ID_GRR__release_99_str_psi_2__compact_ctrl_info,
3437 /* 3419*/ CCD_ID_GRR__release_99_str_psi_2__add_psi,
3438 /* 3420*/ CCD_ID_GRR__psi_2_trnc_grp__cell_id,
3439 /* 3421*/ CCD_ID_GRR__psi_2_trnc_grp__non_gprs_opt,
3440 /* 3422*/ CCD_ID_GRR__psi_2_trnc_grp__rfl,
3441 /* 3423*/ CCD_ID_GRR__psi_2_trnc_grp__cell_alloc,
3442 /* 3424*/ CCD_ID_GRR__psi_2_trnc_grp__gprs_ms_alloc,
3443 /* 3425*/ CCD_ID_GRR__psi_2_trnc_grp__pccch_des,
3444 /* 3426*/ CCD_ID_GRR__psi_2_trnc_grp__release_99_str_psi_2,
3445 /* 3427*/ CCD_ID_GRR__add_reject_trnc_grp__add_reject,
3446 /* 3428*/ CCD_ID_GRR__release_99_str_pda__egprs_link_adpt_para,
3447 /* 3429*/ CCD_ID_GRR__release_99_str_pda__p_ext_ta,
3448 /* 3430*/ CCD_ID_GRR__release_99_str_pda__compact_red_ma,
3449 /* 3431*/ CCD_ID_GRR__pda_trnc_grp__freq_par,
3450 /* 3432*/ CCD_ID_GRR__pda_trnc_grp__dl_tfi_assign,
3451 /* 3433*/ CCD_ID_GRR__pda_trnc_grp__pwr_par,
3452 /* 3434*/ CCD_ID_GRR__pda_trnc_grp__tbf_s_time,
3453 /* 3435*/ CCD_ID_GRR__pda_trnc_grp__meas_map,
3454 /* 3436*/ CCD_ID_GRR__pda_trnc_grp__release_99_str_pda,
3455 /* 3437*/ CCD_ID_GRR__rep_page_info_trnc_grp__rep_page_info,
3456 /* 3438*/ CCD_ID_GRR__release_99_str_d_ul_ack__p_ext_ta,
3457 /* 3439*/ CCD_ID_GRR__release_99_str_d_ul_ack__tbf_est,
3458 /* 3440*/ CCD_ID_GRR__ta_index_tn__ta_index,
3459 /* 3441*/ CCD_ID_GRR__ta_index_tn__ta_tn,
3460 /* 3442*/ CCD_ID_GRR__pta__ta_value,
3461 /* 3443*/ CCD_ID_GRR__pta__ta_index_tn,
3462 /* 3444*/ CCD_ID_GRR__gprs_ul_ack_nack_info__chan_coding_cmd,
3463 /* 3445*/ CCD_ID_GRR__gprs_ul_ack_nack_info__ack_nack_des,
3464 /* 3446*/ CCD_ID_GRR__gprs_ul_ack_nack_info__cr_tlli,
3465 /* 3447*/ CCD_ID_GRR__gprs_ul_ack_nack_info__pta,
3466 /* 3448*/ CCD_ID_GRR__gprs_ul_ack_nack_info__pwr_par,
3467 /* 3449*/ CCD_ID_GRR__gprs_ul_ack_nack_info__ext_bits,
3468 /* 3450*/ CCD_ID_GRR__gprs_ul_ack_nack_info__f_alloc_ack,
3469 /* 3451*/ CCD_ID_GRR__gprs_ul_ack_nack_info__release_99_str_d_ul_ack,
3470 /* 3452*/ CCD_ID_GRR__release_99_str_psi_3__spare_0,
3471 /* 3453*/ CCD_ID_GRR__release_99_str_psi_3__compact_info_str,
3472 /* 3454*/ CCD_ID_GRR__release_99_str_psi_3__spare_1,
3473 /* 3455*/ CCD_ID_GRR__release_98_str_psi_3__serv_cell_lsa_id_info,
3474 /* 3456*/ CCD_ID_GRR__release_98_str_psi_3__lsa_param2,
3475 /* 3457*/ CCD_ID_GRR__release_98_str_psi_3__release_99_str_psi_3,
3476 /* 3458*/ CCD_ID_GRR__release_99_str_d_meas_order__enh_meas_param_pmo,
3477 /* 3459*/ CCD_ID_GRR__release_98_str_d_meas_order__lsa_param2,
3478 /* 3460*/ CCD_ID_GRR__release_98_str_d_meas_order__release_99_str_d_meas_order,
3479 /* 3461*/ CCD_ID_GRR__release_99_str_prr__flag,
3480 /* 3462*/ CCD_ID_GRR__release_99_str_prr__flag2,
3481 /* 3463*/ CCD_ID_GRR__release_99_str_prr__pfi,
3482 /* 3464*/ CCD_ID_GRR__release_99_str_prr__add_ms_rac,
3483 /* 3465*/ CCD_ID_GRR__release_99_str_prr__retrans_of_prr,
3484 /* 3466*/ CCD_ID_GRR__release_99_str_u_dl_ack__pfi,
3485 /* 3467*/ CCD_ID_GRR__release_99_str_psi_1__mscr,
3486 /* 3468*/ CCD_ID_GRR__release_99_str_psi_1__sgsnr,
3487 /* 3469*/ CCD_ID_GRR__release_99_str_psi_1__band_indicator,
3488 /* 3470*/ CCD_ID_GRR__release_99_str_psi_5__enh_rep_param_struct,
3489 /* 3471*/ CCD_ID_GRR__psi1_pbcch_info__psi1_rep_per,
3490 /* 3472*/ CCD_ID_GRR__psi1_pbcch_info__pbcch_des,
3491 /* 3473*/ CCD_ID_GRR__release_99_str_psi_13__sgsnr,
3492 /* 3474*/ CCD_ID_GRR__release_99_str_pmr__ba_psi3_str,
3493 /* 3475*/ CCD_ID_GRR__release_99_str_pmr__meas_rep_3g_str,
3494 /* 3476*/ CCD_ID_GRR__tgt_cell_3g_info__spare_0,
3495 /* 3477*/ CCD_ID_GRR__tgt_cell_3g_info__im_rel_c1,
3496 /* 3478*/ CCD_ID_GRR__tgt_cell_3g_info__target_cell_3g,
3497 /* 3479*/ CCD_ID_GRR__release_99_str_pcco__enh_meas_param_pcco,
3498 /* 3480*/ CCD_ID_GRR__release_98_str_pcco__lsa_param2,
3499 /* 3481*/ CCD_ID_GRR__release_98_str_pcco__release_99_str_pcco,
3500 /* 3482*/ CCD_ID_GRR__gsm_target_cell__arfcn,
3501 /* 3483*/ CCD_ID_GRR__gsm_target_cell__bsic,
3502 /* 3484*/ CCD_ID_GRR__gsm_target_cell__nc_meas_par_list,
3503 /* 3485*/ CCD_ID_GRR__gsm_target_cell__release_98_str_pcco,
3504 /* 3486*/ CCD_ID_GRR__tgt_cell_gsm_info__im_rel_c0,
3505 /* 3487*/ CCD_ID_GRR__tgt_cell_gsm_info__gsm_target_cell,
3506 /* 3488*/ CCD_ID_GRR__tqi_req_ref_p__Choice_flag,
3507 /* 3489*/ CCD_ID_GRR__tqi_req_ref_p__tqi,
3508 /* 3490*/ CCD_ID_GRR__tqi_req_ref_p__req_ref_p,
3509 /* 3491*/ CCD_ID_GRR__add4__flag,
3510 /* 3492*/ CCD_ID_GRR__add4__glob_tfi,
3511 /* 3493*/ CCD_ID_GRR__add4__tqi_req_ref_p,
3512 /* 3494*/ CCD_ID_GRR__release_99_str_ppcta__p_ext_ta,
3513 /* 3495*/ CCD_ID_GRR__D_ACCESS_REJ__msg_type,
3514 /* 3496*/ CCD_ID_GRR__D_ACCESS_REJ__page_mode,
3515 /* 3497*/ CCD_ID_GRR__D_ACCESS_REJ__reject,
3516 /* 3498*/ CCD_ID_GRR__D_ACCESS_REJ__add_reject_trnc_grp,
3517 /* 3499*/ CCD_ID_GRR__D_ACCESS_REJ__spare_0,
3518 /* 3500*/ CCD_ID_GRR__D_QUEUING_NOT__msg_type,
3519 /* 3501*/ CCD_ID_GRR__D_QUEUING_NOT__page_mode,
3520 /* 3502*/ CCD_ID_GRR__D_QUEUING_NOT__spare_0,
3521 /* 3503*/ CCD_ID_GRR__D_QUEUING_NOT__req_ref_p,
3522 /* 3504*/ CCD_ID_GRR__D_QUEUING_NOT__tqi,
3523 /* 3505*/ CCD_ID_GRR__D_QUEUING_NOT__spare_1,
3524 /* 3506*/ CCD_ID_GRR__U_RESOURCE_REQ__msg_type,
3525 /* 3507*/ CCD_ID_GRR__U_RESOURCE_REQ__access_type,
3526 /* 3508*/ CCD_ID_GRR__U_RESOURCE_REQ__flag,
3527 /* 3509*/ CCD_ID_GRR__U_RESOURCE_REQ__glob_tfi,
3528 /* 3510*/ CCD_ID_GRR__U_RESOURCE_REQ__tlli_value,
3529 /* 3511*/ CCD_ID_GRR__U_RESOURCE_REQ__ra_cap,
3530 /* 3512*/ CCD_ID_GRR__U_RESOURCE_REQ__chan_req_des,
3531 /* 3513*/ CCD_ID_GRR__U_RESOURCE_REQ__ma_ch_mark,
3532 /* 3514*/ CCD_ID_GRR__U_RESOURCE_REQ__c_value,
3533 /* 3515*/ CCD_ID_GRR__U_RESOURCE_REQ__signvar,
3534 /* 3516*/ CCD_ID_GRR__U_RESOURCE_REQ__ilev,
3535 /* 3517*/ CCD_ID_GRR__U_RESOURCE_REQ__release_99_str_prr,
3536 /* 3518*/ CCD_ID_GRR__U_RESOURCE_REQ__spare_0,
3537 /* 3519*/ CCD_ID_GRR__D_UL_ASSIGN__msg_type,
3538 /* 3520*/ CCD_ID_GRR__D_UL_ASSIGN__page_mode,
3539 /* 3521*/ CCD_ID_GRR__D_UL_ASSIGN__pers_lev,
3540 /* 3522*/ CCD_ID_GRR__D_UL_ASSIGN__add3,
3541 /* 3523*/ CCD_ID_GRR__D_UL_ASSIGN__egprs_flag,
3542 /* 3524*/ CCD_ID_GRR__D_UL_ASSIGN__chan_coding_cmd,
3543 /* 3525*/ CCD_ID_GRR__D_UL_ASSIGN__tlli_chan_coding,
3544 /* 3526*/ CCD_ID_GRR__D_UL_ASSIGN__pta,
3545 /* 3527*/ CCD_ID_GRR__D_UL_ASSIGN__freq_par,
3546 /* 3528*/ CCD_ID_GRR__D_UL_ASSIGN__flag,
3547 /* 3529*/ CCD_ID_GRR__D_UL_ASSIGN__flag2,
3548 /* 3530*/ CCD_ID_GRR__D_UL_ASSIGN__dyn_alloc_p,
3549 /* 3531*/ CCD_ID_GRR__D_UL_ASSIGN__sin_alloc,
3550 /* 3532*/ CCD_ID_GRR__D_UL_ASSIGN__f_alloc_ul,
3551 /* 3533*/ CCD_ID_GRR__D_UL_ASSIGN__release_99,
3552 /* 3534*/ CCD_ID_GRR__D_UL_ASSIGN__p_ext_ta,
3553 /* 3535*/ CCD_ID_GRR__D_UL_ASSIGN__spare_0,
3554 /* 3536*/ CCD_ID_GRR__D_DL_ASSIGN__msg_type,
3555 /* 3537*/ CCD_ID_GRR__D_DL_ASSIGN__page_mode,
3556 /* 3538*/ CCD_ID_GRR__D_DL_ASSIGN__pers_lev,
3557 /* 3539*/ CCD_ID_GRR__D_DL_ASSIGN__add1,
3558 /* 3540*/ CCD_ID_GRR__D_DL_ASSIGN__spare_0,
3559 /* 3541*/ CCD_ID_GRR__D_DL_ASSIGN__mac_mode,
3560 /* 3542*/ CCD_ID_GRR__D_DL_ASSIGN__rlc_mode,
3561 /* 3543*/ CCD_ID_GRR__D_DL_ASSIGN__ctrl_ack,
3562 /* 3544*/ CCD_ID_GRR__D_DL_ASSIGN__ts_alloc,
3563 /* 3545*/ CCD_ID_GRR__D_DL_ASSIGN__pta,
3564 /* 3546*/ CCD_ID_GRR__D_DL_ASSIGN__bts_pwr_ctrl,
3565 /* 3547*/ CCD_ID_GRR__D_DL_ASSIGN__pda_trnc_grp,
3566 /* 3548*/ CCD_ID_GRR__D_DL_ASSIGN__spare_1,
3567 /* 3549*/ CCD_ID_GRR__D_TBF_RELEASE__msg_type,
3568 /* 3550*/ CCD_ID_GRR__D_TBF_RELEASE__page_mode,
3569 /* 3551*/ CCD_ID_GRR__D_TBF_RELEASE__spare_0,
3570 /* 3552*/ CCD_ID_GRR__D_TBF_RELEASE__glob_tfi,
3571 /* 3553*/ CCD_ID_GRR__D_TBF_RELEASE__ul_release,
3572 /* 3554*/ CCD_ID_GRR__D_TBF_RELEASE__dl_release,
3573 /* 3555*/ CCD_ID_GRR__D_TBF_RELEASE__rel_cause,
3574 /* 3556*/ CCD_ID_GRR__D_TBF_RELEASE__spare_1,
3575 /* 3557*/ CCD_ID_GRR__D_PAGING_REQ__msg_type,
3576 /* 3558*/ CCD_ID_GRR__D_PAGING_REQ__page_mode,
3577 /* 3559*/ CCD_ID_GRR__D_PAGING_REQ__pers_lev,
3578 /* 3560*/ CCD_ID_GRR__D_PAGING_REQ__nln,
3579 /* 3561*/ CCD_ID_GRR__D_PAGING_REQ__rep_page_info_trnc_grp,
3580 /* 3562*/ CCD_ID_GRR__D_PAGING_REQ__spare_0,
3581 /* 3563*/ CCD_ID_GRR__U_DL_ACK__msg_type,
3582 /* 3564*/ CCD_ID_GRR__U_DL_ACK__dl_tfi,
3583 /* 3565*/ CCD_ID_GRR__U_DL_ACK__ack_nack_des,
3584 /* 3566*/ CCD_ID_GRR__U_DL_ACK__chan_req_des,
3585 /* 3567*/ CCD_ID_GRR__U_DL_ACK__chan_qual_rep,
3586 /* 3568*/ CCD_ID_GRR__U_DL_ACK__release_99_str_u_dl_ack,
3587 /* 3569*/ CCD_ID_GRR__U_DL_ACK__spare_0,
3588 /* 3570*/ CCD_ID_GRR__D_UL_ACK__msg_type,
3589 /* 3571*/ CCD_ID_GRR__D_UL_ACK__page_mode,
3590 /* 3572*/ CCD_ID_GRR__D_UL_ACK__spare_0,
3591 /* 3573*/ CCD_ID_GRR__D_UL_ACK__ul_tfi,
3592 /* 3574*/ CCD_ID_GRR__D_UL_ACK__egprs_flag,
3593 /* 3575*/ CCD_ID_GRR__D_UL_ACK__gprs_ul_ack_nack_info,
3594 /* 3576*/ CCD_ID_GRR__D_UL_ACK__spare_1,
3595 /* 3577*/ CCD_ID_GRR__PSI_1__msg_type,
3596 /* 3578*/ CCD_ID_GRR__PSI_1__page_mode,
3597 /* 3579*/ CCD_ID_GRR__PSI_1__pbcch_change_ma,
3598 /* 3580*/ CCD_ID_GRR__PSI_1__psi_change_field,
3599 /* 3581*/ CCD_ID_GRR__PSI_1__psi1_rep_per,
3600 /* 3582*/ CCD_ID_GRR__PSI_1__psi_cnt_lr,
3601 /* 3583*/ CCD_ID_GRR__PSI_1__psi_cnt_hr,
3602 /* 3584*/ CCD_ID_GRR__PSI_1__meas_order,
3603 /* 3585*/ CCD_ID_GRR__PSI_1__gprs_cell_opt,
3604 /* 3586*/ CCD_ID_GRR__PSI_1__prach_ctrl_par,
3605 /* 3587*/ CCD_ID_GRR__PSI_1__pccch_org_par,
3606 /* 3588*/ CCD_ID_GRR__PSI_1__g_pwr_par,
3607 /* 3589*/ CCD_ID_GRR__PSI_1__psi_status_ind,
3608 /* 3590*/ CCD_ID_GRR__PSI_1__release_99_str_psi_1,
3609 /* 3591*/ CCD_ID_GRR__PSI_1__spare_0,
3610 /* 3592*/ CCD_ID_GRR__PSI_2__msg_type,
3611 /* 3593*/ CCD_ID_GRR__PSI_2__page_mode,
3612 /* 3594*/ CCD_ID_GRR__PSI_2__psi2_cm,
3613 /* 3595*/ CCD_ID_GRR__PSI_2__psi2_ind,
3614 /* 3596*/ CCD_ID_GRR__PSI_2__psi2_cnt,
3615 /* 3597*/ CCD_ID_GRR__PSI_2__psi_2_trnc_grp,
3616 /* 3598*/ CCD_ID_GRR__PSI_2__spare_0,
3617 /* 3599*/ CCD_ID_GRR__PSI_3__msg_type,
3618 /* 3600*/ CCD_ID_GRR__PSI_3__page_mode,
3619 /* 3601*/ CCD_ID_GRR__PSI_3__psi3_cm,
3620 /* 3602*/ CCD_ID_GRR__PSI_3__psi3bis_cnt,
3621 /* 3603*/ CCD_ID_GRR__PSI_3__scell_par,
3622 /* 3604*/ CCD_ID_GRR__PSI_3__gen_cell_par,
3623 /* 3605*/ CCD_ID_GRR__PSI_3__ncell_par,
3624 /* 3606*/ CCD_ID_GRR__PSI_3__release_98_str_psi_3,
3625 /* 3607*/ CCD_ID_GRR__PSI_3__spare_0,
3626 /* 3608*/ CCD_ID_GRR__PSI_3_BIS__msg_type,
3627 /* 3609*/ CCD_ID_GRR__PSI_3_BIS__page_mode,
3628 /* 3610*/ CCD_ID_GRR__PSI_3_BIS__psi3_cm,
3629 /* 3611*/ CCD_ID_GRR__PSI_3_BIS__psi3bis_ind,
3630 /* 3612*/ CCD_ID_GRR__PSI_3_BIS__psi3bis_cnt,
3631 /* 3613*/ CCD_ID_GRR__PSI_3_BIS__ncell_par_trnc_grp,
3632 /* 3614*/ CCD_ID_GRR__PSI_3_BIS__spare_0,
3633 /* 3615*/ CCD_ID_GRR__PSI_3_TER__msg_type,
3634 /* 3616*/ CCD_ID_GRR__PSI_3_TER__page_mode,
3635 /* 3617*/ CCD_ID_GRR__PSI_3_TER__psi3_cm,
3636 /* 3618*/ CCD_ID_GRR__PSI_3_TER__psi3ter_ind,
3637 /* 3619*/ CCD_ID_GRR__PSI_3_TER__psi3ter_cnt,
3638 /* 3620*/ CCD_ID_GRR__PSI_3_TER__rtd_rep_prio_trnc_grp,
3639 /* 3621*/ CCD_ID_GRR__PSI_3_TER__spare_0,
3640 /* 3622*/ CCD_ID_GRR__PSI_3_QUA__msg_type,
3641 /* 3623*/ CCD_ID_GRR__PSI_3_QUA__page_mode,
3642 /* 3624*/ CCD_ID_GRR__PSI_3_QUA__psi3_cm,
3643 /* 3625*/ CCD_ID_GRR__PSI_3_QUA__psi3qua_ind,
3644 /* 3626*/ CCD_ID_GRR__PSI_3_QUA__psi3qua_cnt,
3645 /* 3627*/ CCD_ID_GRR__PSI_3_QUA__psi_3_qua_trnc_grp,
3646 /* 3628*/ CCD_ID_GRR__PSI_3_QUA__spare_0,
3647 /* 3629*/ CCD_ID_GRR__PSI_4__msg_type,
3648 /* 3630*/ CCD_ID_GRR__PSI_4__page_mode,
3649 /* 3631*/ CCD_ID_GRR__PSI_4__psi4_cm,
3650 /* 3632*/ CCD_ID_GRR__PSI_4__psi4_ind,
3651 /* 3633*/ CCD_ID_GRR__PSI_4__psi4_cnt,
3652 /* 3634*/ CCD_ID_GRR__PSI_4__chan_list_imeas,
3653 /* 3635*/ CCD_ID_GRR__PSI_4__spare_0,
3654 /* 3636*/ CCD_ID_GRR__PSI_5__msg_type,
3655 /* 3637*/ CCD_ID_GRR__PSI_5__page_mode,
3656 /* 3638*/ CCD_ID_GRR__PSI_5__psi5_cm,
3657 /* 3639*/ CCD_ID_GRR__PSI_5__psi5_ind,
3658 /* 3640*/ CCD_ID_GRR__PSI_5__psi5_cnt,
3659 /* 3641*/ CCD_ID_GRR__PSI_5__nc_meas_par,
3660 /* 3642*/ CCD_ID_GRR__PSI_5__xmeas_par,
3661 /* 3643*/ CCD_ID_GRR__PSI_5__release_99_str_psi_5,
3662 /* 3644*/ CCD_ID_GRR__PSI_5__spare_0,
3663 /* 3645*/ CCD_ID_GRR__PSI_8__msg_type,
3664 /* 3646*/ CCD_ID_GRR__PSI_8__page_mode,
3665 /* 3647*/ CCD_ID_GRR__PSI_8__psi8_cm,
3666 /* 3648*/ CCD_ID_GRR__PSI_8__psi8_ind,
3667 /* 3649*/ CCD_ID_GRR__PSI_8__psi8_cnt,
3668 /* 3650*/ CCD_ID_GRR__PSI_8__cbch_chan_desc,
3669 /* 3651*/ CCD_ID_GRR__PSI_8__spare_0,
3670 /* 3652*/ CCD_ID_GRR__PSI_13__msg_type,
3671 /* 3653*/ CCD_ID_GRR__PSI_13__page_mode,
3672 /* 3654*/ CCD_ID_GRR__PSI_13__bcch_change_ma,
3673 /* 3655*/ CCD_ID_GRR__PSI_13__si_change_ma,
3674 /* 3656*/ CCD_ID_GRR__PSI_13__si13_cm_gprs_alloc,
3675 /* 3657*/ CCD_ID_GRR__PSI_13__flag,
3676 /* 3658*/ CCD_ID_GRR__PSI_13__pbcch_n_pres,
3677 /* 3659*/ CCD_ID_GRR__PSI_13__psi1_pbcch_info,
3678 /* 3660*/ CCD_ID_GRR__PSI_13__release_99_str_psi_13,
3679 /* 3661*/ CCD_ID_GRR__PSI_13__spare_0,
3680 /* 3662*/ CCD_ID_GRR__U_CTRL_ACK__msg_type,
3681 /* 3663*/ CCD_ID_GRR__U_CTRL_ACK__tlli_value,
3682 /* 3664*/ CCD_ID_GRR__U_CTRL_ACK__pctrl_ack,
3683 /* 3665*/ CCD_ID_GRR__U_CTRL_ACK__spare_0,
3684 /* 3666*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__msg_type,
3685 /* 3667*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__tlli_value,
3686 /* 3668*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__arfcn,
3687 /* 3669*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__bsic,
3688 /* 3670*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__failure_cause,
3689 /* 3671*/ CCD_ID_GRR__U_CELL_CHAN_FAILURE__spare_0,
3690 /* 3672*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__msg_type,
3691 /* 3673*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__page_mode,
3692 /* 3674*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__add1,
3693 /* 3675*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__flag,
3694 /* 3676*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__tgt_cell_gsm_info,
3695 /* 3677*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__tgt_cell_3g_info,
3696 /* 3678*/ CCD_ID_GRR__D_CELL_CHAN_ORDER__spare_0,
3697 /* 3679*/ CCD_ID_GRR__D_DL_DUMMY__msg_type,
3698 /* 3680*/ CCD_ID_GRR__D_DL_DUMMY__page_mode,
3699 /* 3681*/ CCD_ID_GRR__D_DL_DUMMY__pers_lev,
3700 /* 3682*/ CCD_ID_GRR__D_DL_DUMMY__spare_0,
3701 /* 3683*/ CCD_ID_GRR__U_UL_DUMMY__msg_type,
3702 /* 3684*/ CCD_ID_GRR__U_UL_DUMMY__tlli_value,
3703 /* 3685*/ CCD_ID_GRR__U_UL_DUMMY__spare_0,
3704 /* 3686*/ CCD_ID_GRR__U_MEAS_REPORT__msg_type,
3705 /* 3687*/ CCD_ID_GRR__U_MEAS_REPORT__tlli_value,
3706 /* 3688*/ CCD_ID_GRR__U_MEAS_REPORT__psi5_cm,
3707 /* 3689*/ CCD_ID_GRR__U_MEAS_REPORT__flag,
3708 /* 3690*/ CCD_ID_GRR__U_MEAS_REPORT__nc_meas_rep,
3709 /* 3691*/ CCD_ID_GRR__U_MEAS_REPORT__xmeas_rep,
3710 /* 3692*/ CCD_ID_GRR__U_MEAS_REPORT__release_99_str_pmr,
3711 /* 3693*/ CCD_ID_GRR__U_MEAS_REPORT__spare_0,
3712 /* 3694*/ CCD_ID_GRR__D_MEAS_ORDER__msg_type,
3713 /* 3695*/ CCD_ID_GRR__D_MEAS_ORDER__page_mode,
3714 /* 3696*/ CCD_ID_GRR__D_MEAS_ORDER__add1,
3715 /* 3697*/ CCD_ID_GRR__D_MEAS_ORDER__pmo_index,
3716 /* 3698*/ CCD_ID_GRR__D_MEAS_ORDER__pmo_cnt,
3717 /* 3699*/ CCD_ID_GRR__D_MEAS_ORDER__nc_meas_par_list,
3718 /* 3700*/ CCD_ID_GRR__D_MEAS_ORDER__xmeas_par,
3719 /* 3701*/ CCD_ID_GRR__D_MEAS_ORDER__release_98_str_d_meas_order,
3720 /* 3702*/ CCD_ID_GRR__D_MEAS_ORDER__spare_0,
3721 /* 3703*/ CCD_ID_GRR__U_MS_TBF_STATUS__msg_type,
3722 /* 3704*/ CCD_ID_GRR__U_MS_TBF_STATUS__glob_tfi,
3723 /* 3705*/ CCD_ID_GRR__U_MS_TBF_STATUS__tbf_cause,
3724 /* 3706*/ CCD_ID_GRR__U_MS_TBF_STATUS__msg_type2,
3725 /* 3707*/ CCD_ID_GRR__U_MS_TBF_STATUS__spare_0,
3726 /* 3708*/ CCD_ID_GRR__U_ENHNC_MEAS_REPORT__msg_type,
3727 /* 3709*/ CCD_ID_GRR__U_ENHNC_MEAS_REPORT__tlli_value,
3728 /* 3710*/ CCD_ID_GRR__U_ENHNC_MEAS_REPORT__nc_meas_rep_enh,
3729 /* 3711*/ CCD_ID_GRR__U_ENHNC_MEAS_REPORT__spare_0,
3730 /* 3712*/ CCD_ID_GRR__D_PDCH_RELEASE__msg_type,
3731 /* 3713*/ CCD_ID_GRR__D_PDCH_RELEASE__page_mode,
3732 /* 3714*/ CCD_ID_GRR__D_PDCH_RELEASE__flag,
3733 /* 3715*/ CCD_ID_GRR__D_PDCH_RELEASE__ts_available,
3734 /* 3716*/ CCD_ID_GRR__D_PDCH_RELEASE__spare_0,
3735 /* 3717*/ CCD_ID_GRR__D_POLLING_REQ__msg_type,
3736 /* 3718*/ CCD_ID_GRR__D_POLLING_REQ__page_mode,
3737 /* 3719*/ CCD_ID_GRR__D_POLLING_REQ__add2,
3738 /* 3720*/ CCD_ID_GRR__D_POLLING_REQ__ctrl_ack_type,
3739 /* 3721*/ CCD_ID_GRR__D_POLLING_REQ__spare_0,
3740 /* 3722*/ CCD_ID_GRR__D_CTRL_PWR_TA__msg_type,
3741 /* 3723*/ CCD_ID_GRR__D_CTRL_PWR_TA__page_mode,
3742 /* 3724*/ CCD_ID_GRR__D_CTRL_PWR_TA__add4,
3743 /* 3725*/ CCD_ID_GRR__D_CTRL_PWR_TA__spare_0,
3744 /* 3726*/ CCD_ID_GRR__D_CTRL_PWR_TA__g_pwr_par,
3745 /* 3727*/ CCD_ID_GRR__D_CTRL_PWR_TA__flag,
3746 /* 3728*/ CCD_ID_GRR__D_CTRL_PWR_TA__flag2,
3747 /* 3729*/ CCD_ID_GRR__D_CTRL_PWR_TA__gpta,
3748 /* 3730*/ CCD_ID_GRR__D_CTRL_PWR_TA__pwr_par,
3749 /* 3731*/ CCD_ID_GRR__D_CTRL_PWR_TA__release_99_str_ppcta,
3750 /* 3732*/ CCD_ID_GRR__D_CTRL_PWR_TA__spare_1,
3751 /* 3733*/ CCD_ID_GRR__D_PRACH_PAR__msg_type,
3752 /* 3734*/ CCD_ID_GRR__D_PRACH_PAR__page_mode,
3753 /* 3735*/ CCD_ID_GRR__D_PRACH_PAR__prach_ctrl_par,
3754 /* 3736*/ CCD_ID_GRR__D_PRACH_PAR__spare_0,
3755 /* 3737*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__msg_type,
3756 /* 3738*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__glob_tfi,
3757 /* 3739*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__pbcch_change_ma,
3758 /* 3740*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__received_psi,
3759 /* 3741*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__unknown_psi,
3760 /* 3742*/ CCD_ID_GRR__U_PKT_PSI_STATUS_MSG__spare_0,
3761 /* 3743*/ CCD_ID_GRR__D_TS_RECONFIG__msg_type,
3762 /* 3744*/ CCD_ID_GRR__D_TS_RECONFIG__page_mode,
3763 /* 3745*/ CCD_ID_GRR__D_TS_RECONFIG__spare_0,
3764 /* 3746*/ CCD_ID_GRR__D_TS_RECONFIG__glob_tfi,
3765 /* 3747*/ CCD_ID_GRR__D_TS_RECONFIG__egprs_flag,
3766 /* 3748*/ CCD_ID_GRR__D_TS_RECONFIG__chan_coding_cmd,
3767 /* 3749*/ CCD_ID_GRR__D_TS_RECONFIG__gpta,
3768 /* 3750*/ CCD_ID_GRR__D_TS_RECONFIG__dl_rlc_mode,
3769 /* 3751*/ CCD_ID_GRR__D_TS_RECONFIG__ctrl_ack,
3770 /* 3752*/ CCD_ID_GRR__D_TS_RECONFIG__dl_tfi,
3771 /* 3753*/ CCD_ID_GRR__D_TS_RECONFIG__ul_tfi,
3772 /* 3754*/ CCD_ID_GRR__D_TS_RECONFIG__dl_tn_alloc,
3773 /* 3755*/ CCD_ID_GRR__D_TS_RECONFIG__freq_par,
3774 /* 3756*/ CCD_ID_GRR__D_TS_RECONFIG__flag,
3775 /* 3757*/ CCD_ID_GRR__D_TS_RECONFIG__dyn_alloc_ts,
3776 /* 3758*/ CCD_ID_GRR__D_TS_RECONFIG__f_alloc_re,
3777 /* 3759*/ CCD_ID_GRR__D_TS_RECONFIG__release_99,
3778 /* 3760*/ CCD_ID_GRR__D_TS_RECONFIG__p_ext_ta,
3779 /* 3761*/ CCD_ID_GRR__D_TS_RECONFIG__spare_1,
3780 /* 3762*/ CCD_ID_SM__nsapi__spare_0,
3781 /* 3763*/ CCD_ID_SM__nsapi__nsapi_val,
3782 /* 3764*/ CCD_ID_SM__llc_sapi__spare_0,
3783 /* 3765*/ CCD_ID_SM__llc_sapi__sapi,
3784 /* 3766*/ CCD_ID_SM__qos_r97__spare_0,
3785 /* 3767*/ CCD_ID_SM__qos_r97__delay,
3786 /* 3768*/ CCD_ID_SM__qos_r97__reliability,
3787 /* 3769*/ CCD_ID_SM__qos_r97__peak,
3788 /* 3770*/ CCD_ID_SM__qos_r97__spare_1,
3789 /* 3771*/ CCD_ID_SM__qos_r97__precedence,
3790 /* 3772*/ CCD_ID_SM__qos_r97__spare_2,
3791 /* 3773*/ CCD_ID_SM__qos_r97__mean,
3792 /* 3774*/ CCD_ID_SM__qos_r99__tc,
3793 /* 3775*/ CCD_ID_SM__qos_r99__order,
3794 /* 3776*/ CCD_ID_SM__qos_r99__del_err_sdu,
3795 /* 3777*/ CCD_ID_SM__qos_r99__max_sdu,
3796 /* 3778*/ CCD_ID_SM__qos_r99__max_br_ul,
3797 /* 3779*/ CCD_ID_SM__qos_r99__max_br_dl,
3798 /* 3780*/ CCD_ID_SM__qos_r99__ber,
3799 /* 3781*/ CCD_ID_SM__qos_r99__sdu_err_ratio,
3800 /* 3782*/ CCD_ID_SM__qos_r99__xfer_delay,
3801 /* 3783*/ CCD_ID_SM__qos_r99__handling_pri,
3802 /* 3784*/ CCD_ID_SM__qos_r99__guar_br_ul,
3803 /* 3785*/ CCD_ID_SM__qos_r99__guar_br_dl,
3804 /* 3786*/ CCD_ID_SM__qos__tlv_len,
3805 /* 3787*/ CCD_ID_SM__qos__qos_r97,
3806 /* 3788*/ CCD_ID_SM__qos__qos_r99,
3807 /* 3789*/ CCD_ID_SM__address__spare_0,
3808 /* 3790*/ CCD_ID_SM__address__pdp_type_org,
3809 /* 3791*/ CCD_ID_SM__address__pdp_type_no,
3810 /* 3792*/ CCD_ID_SM__address__add_info,
3811 /* 3793*/ CCD_ID_SM__apn__apn_value,
3812 /* 3794*/ CCD_ID_SM__pco__pco_value,
3813 /* 3795*/ CCD_ID_SM__radio_prio__spare_0,
3814 /* 3796*/ CCD_ID_SM__radio_prio__radio_prio_val,
3815 /* 3797*/ CCD_ID_SM__linked_ti__ti_flag,
3816 /* 3798*/ CCD_ID_SM__linked_ti__ti_val,
3817 /* 3799*/ CCD_ID_SM__linked_ti__spare_0,
3818 /* 3800*/ CCD_ID_SM__linked_ti__ti_ext_flag,
3819 /* 3801*/ CCD_ID_SM__linked_ti__ti_ext_val,
3820 /* 3802*/ CCD_ID_SM__tear_down__spare_0,
3821 /* 3803*/ CCD_ID_SM__tear_down__tear_down_flag,
3822 /* 3804*/ CCD_ID_SM__sm_cause__sm_cause_val,
3823 /* 3805*/ CCD_ID_SM__pfi__spare_0,
3824 /* 3806*/ CCD_ID_SM__pfi__pfi_val,
3825 /* 3807*/ CCD_ID_SM__tft_ipv4_addr_mask__src_addr,
3826 /* 3808*/ CCD_ID_SM__tft_ipv4_addr_mask__addr_mask,
3827 /* 3809*/ CCD_ID_SM__tft_ipv6_addr_mask__src_addr,
3828 /* 3810*/ CCD_ID_SM__tft_ipv6_addr_mask__addr_mask,
3829 /* 3811*/ CCD_ID_SM__tft_protocol__tft_protocol_val,
3830 /* 3812*/ CCD_ID_SM__tft_dest_port_range__low_limit,
3831 /* 3813*/ CCD_ID_SM__tft_dest_port_range__high_limit,
3832 /* 3814*/ CCD_ID_SM__tft_dest_port__low_limit,
3833 /* 3815*/ CCD_ID_SM__tft_ipsec_spi__ipsec_spi_value,
3834 /* 3816*/ CCD_ID_SM__tft_tos_and_mask__tos_value,
3835 /* 3817*/ CCD_ID_SM__tft_tos_and_mask__tos_mask,
3836 /* 3818*/ CCD_ID_SM__tft_flow_label__flow_label_value,
3837 /* 3819*/ CCD_ID_SM__tft_filter_entry__tft_ipv4_addr_mask,
3838 /* 3820*/ CCD_ID_SM__tft_filter_entry__tft_ipv6_addr_mask,
3839 /* 3821*/ CCD_ID_SM__tft_filter_entry__tft_protocol,
3840 /* 3822*/ CCD_ID_SM__tft_filter_entry__tft_dest_port_range,
3841 /* 3823*/ CCD_ID_SM__tft_filter_entry__tft_dest_port,
3842 /* 3824*/ CCD_ID_SM__tft_filter_entry__tft_src_port_range,
3843 /* 3825*/ CCD_ID_SM__tft_filter_entry__tft_src_port,
3844 /* 3826*/ CCD_ID_SM__tft_filter_entry__tft_ipsec_spi,
3845 /* 3827*/ CCD_ID_SM__tft_filter_entry__tft_tos_and_mask,
3846 /* 3828*/ CCD_ID_SM__tft_filter_entry__tft_flow_label,
3847 /* 3829*/ CCD_ID_SM__tft_filter__tft_filter_id,
3848 /* 3830*/ CCD_ID_SM__tft_filter__tft_filter_prio,
3849 /* 3831*/ CCD_ID_SM__tft_filter__tft_filter_entry,
3850 /* 3832*/ CCD_ID_SM__tft__tft_opcode,
3851 /* 3833*/ CCD_ID_SM__tft__spare_0,
3852 /* 3834*/ CCD_ID_SM__tft__tft_filter_count,
3853 /* 3835*/ CCD_ID_SM__tft__tft_filter_id,
3854 /* 3836*/ CCD_ID_SM__tft__tft_filter,
3855 /* 3837*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__msg_type,
3856 /* 3838*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__nsapi,
3857 /* 3839*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__llc_sapi,
3858 /* 3840*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__qos,
3859 /* 3841*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__address,
3860 /* 3842*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__apn,
3861 /* 3843*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REQUEST__pco,
3862 /* 3844*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__msg_type,
3863 /* 3845*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__llc_sapi,
3864 /* 3846*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__qos,
3865 /* 3847*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__radio_prio,
3866 /* 3848*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__spare_0,
3867 /* 3849*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__address,
3868 /* 3850*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__pco,
3869 /* 3851*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_ACCEPT__pfi,
3870 /* 3852*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REJECT__msg_type,
3871 /* 3853*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REJECT__sm_cause,
3872 /* 3854*/ CCD_ID_SM__ACTIVATE_PDP_CONTEXT_REJECT__pco,
3873 /* 3855*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__msg_type,
3874 /* 3856*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__nsapi,
3875 /* 3857*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__llc_sapi,
3876 /* 3858*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__qos,
3877 /* 3859*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__linked_ti,
3878 /* 3860*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REQUEST__tft,
3879 /* 3861*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__msg_type,
3880 /* 3862*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__llc_sapi,
3881 /* 3863*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__qos,
3882 /* 3864*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__radio_prio,
3883 /* 3865*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__spare_0,
3884 /* 3866*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_ACCEPT__pfi,
3885 /* 3867*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REJECT__msg_type,
3886 /* 3868*/ CCD_ID_SM__ACTIVATE_SECONDARY_PDP_CONTEXT_REJECT__sm_cause,
3887 /* 3869*/ CCD_ID_SM__REQUEST_PDP_CONTEXT_ACTIVATION__msg_type,
3888 /* 3870*/ CCD_ID_SM__REQUEST_PDP_CONTEXT_ACTIVATION__address,
3889 /* 3871*/ CCD_ID_SM__REQUEST_PDP_CONTEXT_ACTIVATION__apn,
3890 /* 3872*/ CCD_ID_SM__REQUEST_PDP_CONTEXT_ACTIVATION_REJECT__msg_type,
3891 /* 3873*/ CCD_ID_SM__REQUEST_PDP_CONTEXT_ACTIVATION_REJECT__sm_cause,
3892 /* 3874*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__msg_type,
3893 /* 3875*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__radio_prio,
3894 /* 3876*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__spare_0,
3895 /* 3877*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__llc_sapi,
3896 /* 3878*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__qos,
3897 /* 3879*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__address,
3898 /* 3880*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_REQUEST__pfi,
3899 /* 3881*/ CCD_ID_SM__U_MODIFY_PDP_CONTEXT_REQUEST__msg_type,
3900 /* 3882*/ CCD_ID_SM__U_MODIFY_PDP_CONTEXT_REQUEST__llc_sapi,
3901 /* 3883*/ CCD_ID_SM__U_MODIFY_PDP_CONTEXT_REQUEST__qos,
3902 /* 3884*/ CCD_ID_SM__U_MODIFY_PDP_CONTEXT_REQUEST__tft,
3903 /* 3885*/ CCD_ID_SM__U_MODIFY_PDP_CONTEXT_ACCEPT__msg_type,
3904 /* 3886*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_ACCEPT__msg_type,
3905 /* 3887*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_ACCEPT__qos,
3906 /* 3888*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_ACCEPT__llc_sapi,
3907 /* 3889*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_ACCEPT__radio_prio,
3908 /* 3890*/ CCD_ID_SM__D_MODIFY_PDP_CONTEXT_ACCEPT__pfi,
3909 /* 3891*/ CCD_ID_SM__MODIFY_PDP_CONTEXT_REJECT__msg_type,
3910 /* 3892*/ CCD_ID_SM__MODIFY_PDP_CONTEXT_REJECT__sm_cause,
3911 /* 3893*/ CCD_ID_SM__DEACTIVATE_PDP_CONTEXT_REQUEST__msg_type,
3912 /* 3894*/ CCD_ID_SM__DEACTIVATE_PDP_CONTEXT_REQUEST__sm_cause,
3913 /* 3895*/ CCD_ID_SM__DEACTIVATE_PDP_CONTEXT_REQUEST__tear_down,
3914 /* 3896*/ CCD_ID_SM__DEACTIVATE_PDP_CONTEXT_ACCEPT__msg_type,
3915 /* 3897*/ CCD_ID_SM__SM_STATUS__msg_type,
3916 /* 3898*/ CCD_ID_SM__SM_STATUS__sm_cause,
3917 /*65535*/ CCD_ID_END = 0x7fffffff
3918 } T_CCD_ID;