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comparison src/cs/drivers/drv_app/fchg/fchg_struct.h @ 360:ce6d71349af0

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FCHG: data structure changes in preparation for the new version
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 29 Dec 2017 05:42:54 +0000
parents 8a90038c0173
children 4c3d05866531
comparison
equal deleted inserted replaced
359:edd20483fa59 360:ce6d71349af0
13 13
14 struct charging_config { 14 struct charging_config {
15 UINT16 start_delay; 15 UINT16 start_delay;
16 UINT16 start_thresh; 16 UINT16 start_thresh;
17 UINT16 restart_thresh; 17 UINT16 restart_thresh;
18 UINT16 charge_to_mv; 18 UINT16 ci2cv_thresh;
19 UINT16 cv_init_set;
20 UINT16 cv_ctrl_loop_high;
21 UINT16 cv_ctrl_loop_low;
22 UINT16 cv_samples_needed;
19 UINT16 overvoltage; 23 UINT16 overvoltage;
20 UINT16 ci_current; 24 UINT16 ci_current;
21 UINT16 end_current; 25 UINT16 end_current;
26 UINT16 ichg_max_spike;
27 UINT16 ichg_samples_needed;
28 UINT16 charge_time_limit;
29 UINT16 recharge_delay;
22 UINT16 bciconf; 30 UINT16 bciconf;
23 }; 31 };
24 32
25 /* from original PWR SWE */ 33 /* from original PWR SWE */
26 typedef struct { 34 typedef struct {
27 UINT16 bat_voltage; 35 UINT16 bat_voltage;
28 T_PWR_PERCENT remain_capa; 36 T_PWR_PERCENT remain_capa;
29 } T_PWR_THRESHOLDS; 37 } T_PWR_THRESHOLDS;
30 38
31 #define MAX_THRESHOLDS 101 39 #define MAX_THRESHOLDS 101
40
41 #define ICHG_AVG_WINDOW 6
32 42
33 typedef struct { 43 typedef struct {
34 /* RiViera boilerplate */ 44 /* RiViera boilerplate */
35 T_RVF_ADDR_ID addr_id; 45 T_RVF_ADDR_ID addr_id;
36 T_RVF_MB_ID prim_id; 46 T_RVF_MB_ID prim_id;
43 enum fchg_state state; 53 enum fchg_state state;
44 UINT16 batt_mv; 54 UINT16 batt_mv;
45 UINT16 curr_disch_thresh; 55 UINT16 curr_disch_thresh;
46 /* valid only during a charging cycle */ 56 /* valid only during a charging cycle */
47 UINT16 i2v_offset; 57 UINT16 i2v_offset;
58 UINT16 cv_dac_init;
59 UINT16 cv_dac_curr;
60 UINT16 cv_high_vbat_count;
61 UINT16 cv_low_vbat_count;
62 UINT16 ichg_avg_buf[ICHG_AVG_WINDOW];
63 UINT16 ichg_fill_level;
64 UINT16 ichg_ring_ptr;
65 UINT16 ichg_average;
66 UINT16 ichg_low_count;
67 UINT32 start_time;
48 } T_PWR_CTRL_BLOCK; 68 } T_PWR_CTRL_BLOCK;
49 69
50 #endif /* include guard */ 70 #endif /* include guard */