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comparison src/cs/system/Main/init.c @ 270:d5a34ea92f2a

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init.c: Init_Unmask_IT() reconstructed the trivial way
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 06 Aug 2017 17:58:13 +0000
parents a498108254c9
children e18367b5427e
comparison
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269:a498108254c9 270:d5a34ea92f2a
789 #endif 789 #endif
790 #endif 790 #endif
791 } 791 }
792 792
793 /* 793 /*
794 * Init_Unmask_IT
795 *
796 * Unmask all used interrupts.
797 */
798
799 void Init_Unmask_IT (void)
800 {
801 #if (CODE_VERSION != SIMULATION)
802 /* Reset all current interrupts */
803 #if (CHIPSET == 12) || (CHIPSET == 15)
804 F_INTH2_VALID_NEXT(C_INTH_IRQ); /* Reset current IT in INTH2 IRQ */
805 F_INTH_VALID_NEXT(C_INTH_IRQ); /* Reset current IT in INTH IRQ */
806 F_INTH_VALID_NEXT(C_INTH_FIQ); /* Reset current IT in INTH FIQ */
807 F_INTH_RESET_ALL_IT; /* Reset all IRQ/FIQ source */
808 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
809 INTH_RESETALLIT;
810 INTH_CLEAR; /* reset IRQ/FIQ source */
811 #endif
812
813 // Disable all the IRQs of ARM before unmasking the interrupts. And enable them once the unmasking is
814 // complete. This will ensure that no context switch happens due to coming of an already unmasked interrupt
815 // before completing the unmasking of the rest of the interrupts. If the context switch happens in
816 // before all the interrupts have been unmasked, then the control will never return to this function
817 //since it will go to TCT_Scheduler() and so some interrupts may remain masked.
818 INT_DisableIRQ();
819
820 // SL: TEMPORARY FIX FOR BUG ON P2
821 // FRAME INTERRUPT STAY MASKED
822 #if ((BOARD == 35) || (BOARD == 46))
823 INTH_ENABLEONEIT(IQ_FRAME);
824 #endif
825 // TEMPORARY FIX FOR BUG ON P2
826
827
828 /* Enable Uart Modem and IrDA interrupts */
829 #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || \
830 (TESTMODE) || (TRACE_TYPE==7)) && (OP_L1_STANDALONE == 1)) || \
831 (OP_L1_STANDALONE == 0))
832
833 #if (CHIPSET == 12) || (CHIPSET == 15)
834 F_INTH_ENABLE_ONE_IT (C_INTH_UART_IRDA_IT); /* Enable UART_IRDA interrupts */
835 #if (CHIPSET == 12)
836 F_INTH_ENABLE_ONE_IT(C_INTH_UART_MODEM1_IT); /* Enable UART_MODEM interrupts */
837 #endif
838 #else
839 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || \
840 (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
841 #if ((BOARD != 35) && (BOARD != 46))
842 INTH_ENABLEONEIT (IQ_UART_IRDA_IT); /* Enable UART_IRDA interrupts */
843 #endif
844 #endif
845 INTH_ENABLEONEIT (IQ_UART_IT); /* Enable UART_MODEM interrupts */
846 #endif
847
848 #if (OP_L1_STANDALONE == 1)
849 #if (CHIPSET == 12)
850 F_INTH_ENABLE_ONE_IT (C_INTH_UART_MODEM2_IT); /* Enable UART_MODEM2 interrupts */
851 #endif
852 #endif /* (OP_L1_STANDALONE == 1) */
853
854 #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */
855
856 /* Enable other interrupts */
857 #if (OP_L1_STANDALONE == 1)
858 if (l1_config.pwr_mngt == PWR_MNGT)
859 {
860
861 #if GEMINI_TIMER
862 #if (CHIPSET == 12) || (CHIPSET == 15)
863 F_INTH_ENABLE_ONE_IT(C_INTH_TIMER1_IT); /* Enable Timer1 interrupt */
864 #else
865 INTH_ENABLEONEIT(IQ_TIM1); /* Enable Timer1 interrupt */
866 #endif
867 #endif
868
869 #if EXT_IRQ
870 #if (CHIPSET == 12) || (CHIPSET == 15)
871 F_INTH_ENABLE_ONE_IT (C_INTH_ABB_IRQ_IT); /* Enable ABB_IRQ_IT EXT_IRQ */
872 #else
873 INTH_ENABLEONEIT(IQ_EXT); /* Enable External interrupt */
874 #endif
875 #endif
876 }
877
878 #else
879 #if ((CHIPSET == 12) || (CHIPSET == 15))
880 F_INTH_ENABLE_ONE_IT(C_INTH_KEYBOARD_IT);
881 #else
882 #if ((BOARD == 35) || (BOARD == 46))
883 INTH_ENABLEONEIT (IQ_ICR);
884 #else
885 INTH_ENABLEONEIT (IQ_ARMIO); /* Enable Keypad/GPIO Interrupt */
886 #endif
887 #endif /* (CHIPSET == 12) */
888 #endif /* OP_L1_STANDALONE */
889
890
891 #if (CHIPSET == 12) || (CHIPSET == 15)
892 //enable LEAD2 interrupt
893 F_INTH_ENABLE_ONE_IT (C_INTH_API_IT);
894 #else
895 //enable LEAD2 interrupt
896 INTH_ENABLEONEIT(IQ_API);
897 #endif
898
899
900 /* Enable TDMA interrupt */
901 #if ((CHIPSET == 12) || (CHIPSET == 15))
902 #if (PSP_STANDALONE == 0)
903 F_INTH_ENABLE_ONE_IT (C_INTH_FRAME_IT);
904 #endif
905 #else
906 INTH_ENABLEONEIT(IQ_FRAME);
907 #endif
908 //--> to enable DMA Interrupt for Lite
909 #if ((CHIPSET == 15) )
910 #if (LOCOSTO_LITE == 1)
911 F_INTH_ENABLE_ONE_IT (C_INTH_DMA_IT);
912 #endif
913 #endif
914 //<-- to enable DMA Interrupt for Lite
915
916 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) )
917 #if (CHIPSET == 12) || (CHIPSET == 15)
918 F_INTH_ENABLE_ONE_IT(C_INTH_API_IT); // Enable API interrupt
919 #elif (CHIPSET == 10)
920 #if (L1_DYN_DSP_DWNLD == 1)
921
922 //enable interrupt
923 INTH_ENABLEONEIT (IQ_API);
924
925 #endif // L1_DYN_DSP_DWNLD == 1
926 #endif // CHIPSET
927 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC ==1) || (L1_DYN_DSP_DWNLD == 1)
928 // Enable the ARM IRQs once all the interrupts have been unmasked.
929 INT_EnableIRQ();
930 #endif /* NO SIMULATION */
931 }
932
933
934 /*
935 * Init_Serial_Flows 794 * Init_Serial_Flows
936 * 795 *
937 * Performs Serialswitch + related serial data flows initialization. 796 * Performs Serialswitch + related serial data flows initialization.
938 */ 797 */
939
940 void Init_Serial_Flows (void) 798 void Init_Serial_Flows (void)
941 { 799 {
942 #if (OP_L1_STANDALONE == 0) 800 #if (OP_L1_STANDALONE == 0)
943 801
944 /* 802 /*
997 855
998 #endif /* TRACE_TYPE */ 856 #endif /* TRACE_TYPE */
999 857
1000 #endif /* OP_L1_STANDALONE */ 858 #endif /* OP_L1_STANDALONE */
1001 } 859 }
860
861 /*
862 * Init_Unmask_IT
863 *
864 * Unmask all used interrupts.
865 */
866 void Init_Unmask_IT (void)
867 {
868 IQ_Unmask(IQ_FRAME);
869 IQ_Unmask(IQ_UART_IRDA_IT);
870 IQ_Unmask(IQ_UART_IT);
871 IQ_Unmask(IQ_ARMIO);
872 #if (L1_DYN_DSP_DWNLD == 1)
873 IQ_Unmask(IQ_API);
874 #endif
875 }