FreeCalypso > hg > fc-magnetite

comparison src/cs/drivers/drv_app/uart/uartfax.c @ 80:d6e59be562fd

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
uartfax.c: support for FreeCalypso targets
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 02 Oct 2016 06:23:18 +0000
parents 945cf7f506b2
children 3f7095c785b7
comparison
equal deleted inserted replaced
79:3928363c521f 80:d6e59be562fd
86 #include "board.cfg" 86 #include "board.cfg"
87 #include "chipset.cfg" 87 #include "chipset.cfg"
88 #ifdef BLUETOOTH_INCLUDED 88 #ifdef BLUETOOTH_INCLUDED
89 #include "btemobile.cfg" 89 #include "btemobile.cfg"
90 #endif 90 #endif
91
92 #include "fc-target.cfg"
91 93
92 94
93 #include <string.h> 95 #include <string.h>
94 #include "nucleus.h" 96 #include "nucleus.h"
95 97
551 553
552 SYS_BOOL esc_seq_received; 554 SYS_BOOL esc_seq_received;
553 SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. 555 SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side.
554 1: The RS232 line is deactivated (low). */ 556 1: The RS232 line is deactivated (low). */
555 557
556 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 558 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
557 SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and 559 SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and
558 handled by Calypso+ on E-Sample. 560 handled by Calypso+ on E-Sample.
559 1: The RS232 line is deactivated (low). */ 561 1: The RS232 line is deactivated (low). */
560 /* 562 /*
561 * When the DTR interrupt is detected the user's Rx callback function must 563 * When the DTR interrupt is detected the user's Rx callback function must
913 * Build the state parameter defined in UAF_GetLineState. 915 * Build the state parameter defined in UAF_GetLineState.
914 * The field state_2 is used when state_1 is set to 0 to avoid to 916 * The field state_2 is used when state_1 is set to 0 to avoid to
915 * lose events detected in the RX interrupt handler. 917 * lose events detected in the RX interrupt handler.
916 */ 918 */
917 919
918 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 920 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
919 if (call_source == 3) /* Call from Rx HISR */ 921 if (call_source == 3) /* Call from Rx HISR */
920 dtr_level = uart->dtr_level_saved[uart->index_hisr]; 922 dtr_level = uart->dtr_level_saved[uart->index_hisr];
921 else 923 else
922 dtr_level = uart->dtr_level; 924 dtr_level = uart->dtr_level;
923 #endif 925 #endif
930 uart->state_1 = 0; 932 uart->state_1 = 0;
931 uart->state = &(uart->state_1); 933 uart->state = &(uart->state_1);
932 934
933 state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | 935 state |= ((((SYS_UWORD32) uart->rts_level) << RTS) |
934 936
935 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 937 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
936 (((SYS_UWORD32) dtr_level) << DTR) | 938 (((SYS_UWORD32) dtr_level) << DTR) |
937 #endif 939 #endif
938 940
939 (((SYS_UWORD32) (uart->tx_stopped_by_application | 941 (((SYS_UWORD32) (uart->tx_stopped_by_application |
940 uart->tx_stopped_by_driver)) << TXSTP) | 942 uart->tx_stopped_by_driver)) << TXSTP) |
953 * X 0 RTS XON:0 XOFF:1 (transmitter) 955 * X 0 RTS XON:0 XOFF:1 (transmitter)
954 * 956 *
955 * DTR is supported on C, D & E-Sample. 957 * DTR is supported on C, D & E-Sample.
956 */ 958 */
957 959
958 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 960 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
959 state |= (((SYS_UWORD32) uart->dtr_level) << SA); 961 state |= (((SYS_UWORD32) uart->dtr_level) << SA);
960 #endif 962 #endif
961 963
962 if (uart->flow_control_mode != fc_rts) 964 if (uart->flow_control_mode != fc_rts)
963 state |= (((SYS_UWORD32) uart->rts_level) << SB); 965 state |= (((SYS_UWORD32) uart->rts_level) << SB);
1963 */ 1965 */
1964 1966
1965 SER_restart_uart_sleep_timer (); 1967 SER_restart_uart_sleep_timer ();
1966 uart_sleep_timer_enabled = 1; 1968 uart_sleep_timer_enabled = 1;
1967 1969
1968 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 1970 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
1969 uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ 1971 uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */
1970 #endif 1972 #endif
1971 1973
1972 xon_xoff_detected = 0; 1974 xon_xoff_detected = 0;
1973 1975
2164 if ((!uart->rd_call_from_hisr_in_progress) && 2166 if ((!uart->rd_call_from_hisr_in_progress) &&
2165 (uart->reading_suspended || 2167 (uart->reading_suspended ||
2166 (uart->rd_call_setup == rm_reInstall))) { 2168 (uart->rd_call_setup == rm_reInstall))) {
2167 2169
2168 if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || 2170 if ((bytes_in_rx_buffer >= uart->rx_threshold_level) ||
2169 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 2171 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
2170 uart->dtr_change_detected[uart->index_hisr] || 2172 uart->dtr_change_detected[uart->index_hisr] ||
2171 #endif 2173 #endif
2172 uart->break_received || 2174 uart->break_received ||
2173 xon_xoff_detected) { 2175 xon_xoff_detected) {
2174 2176
2177 update_reading_callback (uart, 3); /* 3: call from Rx HISR. */ 2179 update_reading_callback (uart, 3); /* 3: call from Rx HISR. */
2178 2180
2179 uart->reading_suspended = 0; 2181 uart->reading_suspended = 0;
2180 uart->break_received = 0; 2182 uart->break_received = 0;
2181 uart->esc_seq_received = 0; 2183 uart->esc_seq_received = 0;
2182 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 2184 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
2183 uart->dtr_change_detected[uart->index_hisr] = 0; 2185 uart->dtr_change_detected[uart->index_hisr] = 0;
2184 #endif 2186 #endif
2185 } 2187 }
2186 } 2188 }
2187 2189
2590 } 2592 }
2591 2593
2592 else { 2594 else {
2593 2595
2594 uart->tx_stopped_by_driver = 0; 2596 uart->tx_stopped_by_driver = 0;
2595 LowGPIO(1); 2597 #ifdef CONFIG_TARGET_GTAMODEM
2598 AI_ResetBit(1);
2599 #endif
2596 2600
2597 #if ((CHIPSET != 5) && (CHIPSET != 6)) 2601 #if ((CHIPSET != 5) && (CHIPSET != 6))
2598 /* 2602 /*
2599 * Disable sleep mode. 2603 * Disable sleep mode.
2600 */ 2604 */
2997 if (status & MCTS) 3001 if (status & MCTS)
2998 uart->rts_level = 0; 3002 uart->rts_level = 0;
2999 else 3003 else
3000 uart->rts_level = 1; 3004 uart->rts_level = 1;
3001 3005
3002 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) 3006 #if UARTFAX_CLASSIC_DTR_DCD
3003 /* 3007 /*
3004 * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. 3008 * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem.
3005 * DCD: I/O 2 (output) 3009 * DCD: I/O 2 (output)
3006 * DTR: I/O 3 (input) 3010 * DTR: I/O 3 (input)
3007 */ 3011 */
3217 * Mask all interrupts causes and disable sleep mode and low power mode. 3221 * Mask all interrupts causes and disable sleep mode and low power mode.
3218 */ 3222 */
3219 3223
3220 WRITE_UART_REGISTER (uart, IER, 0x00); 3224 WRITE_UART_REGISTER (uart, IER, 0x00);
3221 3225
3222 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) 3226 #if UARTFAX_CLASSIC_DTR_DCD
3223 AI_MaskIT (ARMIO_MASKIT_GPIO); 3227 AI_MaskIT (ARMIO_MASKIT_GPIO);
3224 #elif (CHIPSET == 12) 3228 #elif (CHIPSET == 12)
3225 DISABLE_DSR_INTERRUPT (uart); 3229 DISABLE_DSR_INTERRUPT (uart);
3226 #endif 3230 #endif
3227 3231
3358 if (status & MCTS) 3362 if (status & MCTS)
3359 uart->rts_level = 0; 3363 uart->rts_level = 0;
3360 else 3364 else
3361 uart->rts_level = 1; 3365 uart->rts_level = 1;
3362 3366
3363 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) 3367 #if UARTFAX_CLASSIC_DTR_DCD
3364 /* 3368 /*
3365 * Read the state of DTR and select the edge. 3369 * Read the state of DTR and select the edge.
3366 */ 3370 */
3367 3371
3368 uart->dtr_level = AI_ReadBit (ARMIO_DTR); 3372 uart->dtr_level = AI_ReadBit (ARMIO_DTR);
4320 if (uart->tx_in >= &(uart->tx_buffer[0]) + uart->buffer_size + 1) 4324 if (uart->tx_in >= &(uart->tx_buffer[0]) + uart->buffer_size + 1)
4321 uart->tx_in = uart->tx_in - uart->buffer_size - 1; 4325 uart->tx_in = uart->tx_in - uart->buffer_size - 1;
4322 4326
4323 /* If we have been stopped due to high RTS, we have to 4327 /* If we have been stopped due to high RTS, we have to
4324 * wake up application processor by IRQ via IO1 -HW */ 4328 * wake up application processor by IRQ via IO1 -HW */
4325 if (uart->tx_stopped_by_driver) 4329 #ifdef CONFIG_TARGET_GTAMODEM
4326 HighGPIO(1); 4330 if (uart->tx_stopped_by_driver)
4331 AI_SetBit(1);
4332 #endif
4327 4333
4328 /* 4334 /*
4329 * If: 4335 * If:
4330 * - there is no break to send, 4336 * - there is no break to send,
4331 * - the flow control is not activated, 4337 * - the flow control is not activated,
4542 uart->state_1 = 0; 4548 uart->state_1 = 0;
4543 uart->state = &(uart->state_1); 4549 uart->state = &(uart->state_1);
4544 4550
4545 *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | 4551 *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) |
4546 4552
4547 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4553 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4548 (((SYS_UWORD32) uart->dtr_level) << DTR) | 4554 (((SYS_UWORD32) uart->dtr_level) << DTR) |
4549 #endif 4555 #endif
4550 4556
4551 (((SYS_UWORD32) (uart->tx_stopped_by_application | 4557 (((SYS_UWORD32) (uart->tx_stopped_by_application |
4552 uart->tx_stopped_by_driver)) << TXSTP) | 4558 uart->tx_stopped_by_driver)) << TXSTP) |
4566 * X 0 RTS XON:0 XOFF:1 (transmitter) 4572 * X 0 RTS XON:0 XOFF:1 (transmitter)
4567 * 4573 *
4568 * DTR is supported on C, D & E-Sample. 4574 * DTR is supported on C, D & E-Sample.
4569 */ 4575 */
4570 4576
4571 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4577 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4572 *state |= (((SYS_UWORD32) uart->dtr_level) << SA); 4578 *state |= (((SYS_UWORD32) uart->dtr_level) << SA);
4573 #endif 4579 #endif
4574 4580
4575 if (uart->flow_control_mode != fc_rts) 4581 if (uart->flow_control_mode != fc_rts)
4576 *state |= (((SYS_UWORD32) uart->rts_level) << SB); 4582 *state |= (((SYS_UWORD32) uart->rts_level) << SB);
4637 * There is no case where FD_INTERNAL_ERR may be returned. 4643 * There is no case where FD_INTERNAL_ERR may be returned.
4638 * DCD is supported on C, D & E-Sample. The SA field is not supported because 4644 * DCD is supported on C, D & E-Sample. The SA field is not supported because
4639 * DSR is not supported on all platforms. 4645 * DSR is not supported on all platforms.
4640 */ 4646 */
4641 4647
4642 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4648 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4643 if (mask & (1 << SA)) 4649 if (mask & (1 << SA))
4644 #else 4650 #else
4645 if ((mask & (1 << SA)) || (mask & (1 << DCD))) 4651 if ((mask & (1 << SA)) || (mask & (1 << DCD)))
4646 #endif 4652 #endif
4647 return (FD_NOT_SUPPORTED); /* Return used to simplify the code */ 4653 return (FD_NOT_SUPPORTED); /* Return used to simplify the code */
4739 4745
4740 /* 4746 /*
4741 * The DCD field is ignored if the SB bit of the mask is set. 4747 * The DCD field is ignored if the SB bit of the mask is set.
4742 */ 4748 */
4743 4749
4744 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4750 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4745 4751
4746 if (!(mask & (1 << SB)) && (mask & (1 << DCD))) { 4752 if (!(mask & (1 << SB)) && (mask & (1 << DCD))) {
4747 4753
4748 if (state & (1 << DCD)) { 4754 if (state & (1 << DCD)) {
4749 /* Turn on DCD */ 4755 /* Turn on DCD */
4775 * 4781 *
4776 * ns: signal not supported. 4782 * ns: signal not supported.
4777 * DCD is supported on C, D & E-Sample. 4783 * DCD is supported on C, D & E-Sample.
4778 */ 4784 */
4779 4785
4780 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4786 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4781 4787
4782 if (mask & (1 << SB)) { 4788 if (mask & (1 << SB)) {
4783 4789
4784 if (state & (1 << SB)) { 4790 if (state & (1 << SB)) {
4785 /* Turn on DCD */ 4791 /* Turn on DCD */
4881 4887
4882 switch (interrupt_status) { 4888 switch (interrupt_status) {
4883 4889
4884 case RX_DATA: 4890 case RX_DATA:
4885 4891
4886 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) 4892 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
4887 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ 4893 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */
4888 uart->dtr_change_detected[uart->index_it] = 0; 4894 uart->dtr_change_detected[uart->index_it] = 0;
4889 uart->dtr_level_saved[uart->index_it] = uart->dtr_level; 4895 uart->dtr_level_saved[uart->index_it] = uart->dtr_level;
4890 #endif 4896 #endif
4891 read_rx_fifo (uart); 4897 read_rx_fifo (uart);
5015 result = FD_NOT_READY; 5021 result = FD_NOT_READY;
5016 5022
5017 return (result); 5023 return (result);
5018 } 5024 }
5019 5025
5020 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) 5026 #if UARTFAX_CLASSIC_DTR_DCD
5021 /******************************************************************************* 5027 /*******************************************************************************
5022 * 5028 *
5023 * UAF_DTRInterruptHandler 5029 * UAF_DTRInterruptHandler
5024 * 5030 *
5025 * Purpose : This function is only used on C & D-Sample. On this platform, the 5031 * Purpose : This function is only used on C & D-Sample. On this platform, the