FreeCalypso > hg > fc-magnetite
view blobs/patches/main-fchw.patch @ 605:07d0dc4431f4
bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix
Both MEMIF and DPLL settings are now the same between int.s and bootloader.s
assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode,
which persisted until _INT_Initialize code with the bootloader body omitted,
or was changed to /1 in the hardware init function in the
bootloader.lib:start.obj module.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 17 Jun 2019 18:40:32 +0000 |
| parents | acb07ce22054 |
| children |
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# This patch applies to the Init_Target() function in the init.obj module in # main.lib; it is an example of how this code will need to be patched for # running on our own future FreeCalypso hardware if we choose to use the same # Spansion S71PL129NC0 flash+pSRAM MCP as used in the Pirelli DP-L10 and use # the same memory timings as set by Pirelli's firmware. [init.obj] # value goes into nCS0, nCS1 and nCS3 config registers .text 66 A4 # value goes into nCS2 config reg .text 6C A4 # nop out the write into 0x02700000 .text 128 C0 .text 129 46