FreeCalypso > hg > fc-magnetite
view components/frame_na7_db_ir-partial @ 605:07d0dc4431f4
bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix
Both MEMIF and DPLL settings are now the same between int.s and bootloader.s
assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode,
which persisted until _INT_Initialize code with the bootloader body omitted,
or was changed to /1 in the hardware init function in the
bootloader.lib:start.obj module.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 17 Jun 2019 18:40:32 +0000 |
parents | 41b6a18ffa0b |
children |
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# Building frame_na7_db_ir.lib using the GPF source bits we got with TCS3.2 # This version uses the original TCS211 objects for the OSL part CFLAGS="-mw -x -pw2 -o3 -me -mt -g -mn" # Defines CPPFLAGS="-DNU_DEBUG -D_FF_RV_EXIST_ -DRUN_INT_RAM" CPPFLAGS="$CPPFLAGS -D_TARGET_ -D_NUCLEUS_" # Includes CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/frame" CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc" CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc/arm7" CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc" CPPFLAGS="$CPPFLAGS -I$SRC/gpf2/tst" # Source modules SRCDIR=$SRC/gpf3/frame cfile_symlink $SRCDIR/frame.c cfile_symlink $SRCDIR/vsi_sem.c cfile_symlink $SRCDIR/vsi_com.c cfile_symlink $SRCDIR/vsi_mem.c cfile_symlink $SRCDIR/vsi_tim.c cfile_symlink $SRCDIR/vsi_mis.c cfile_symlink $SRCDIR/vsi_drv.c cfile_symlink $SRCDIR/vsi_trc.c cfile_symlink $SRCDIR/vsi_pro.c cfile_symlink $SRCDIR/xalert.c cfile_symlink $SRCDIR/route.c cfile_symlink $SRCDIR/prf_func.c cfile_symlink $SRCDIR/frm_ext.c cfile_symlink $SRCDIR/frame_version.c # OSL OBJDIR=../../blobs/obj/osl/ir OBJS="$OBJS $OBJDIR/os_com.obj" OBJS="$OBJS $OBJDIR/os_drv.obj" OBJS="$OBJS $OBJDIR/os_evt.obj" OBJS="$OBJS $OBJDIR/os_isr.obj" OBJS="$OBJS $OBJDIR/os_mem.obj" OBJS="$OBJS $OBJDIR/os_mis.obj" OBJS="$OBJS $OBJDIR/os_pro.obj" OBJS="$OBJS $OBJDIR/os_sem.obj" OBJS="$OBJS $OBJDIR/os_tim.obj"