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view components/tif_na7_db_fl @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 41b6a18ffa0b
children
line wrap: on
line source

# Building tif_na7_db_fl.lib using the GPF source bits we got with TCS211

CFLAGS="-mw -x -pw2 -o -me -mt -g -mn"

# Defines

CPPFLAGS="-DNU_DEBUG -DRUN_FLASH"
CPPFLAGS="$CPPFLAGS -D_TARGET_ -D_NUCLEUS_"

if [ "$TRACEMASK_IN_FFS" = 1 ]
then
	CPPFLAGS="$CPPFLAGS -D_FF_RV_EXIST_"
fi

# Includes

CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc"
CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc/arm7"
CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc"
CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/frame"
CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/ccd"
CPPFLAGS="$CPPFLAGS -I$SRC/gpf2/tst"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/system"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/riviera"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/riviera/rvt"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/drivers/drv_core"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/drivers/drv_core/uart"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/drivers/drv_app"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/drivers/drv_app/uart"
CPPFLAGS="$CPPFLAGS -I$SRC/cs/services"
CPPFLAGS="$CPPFLAGS -I.."
CPPFLAGS="$CPPFLAGS -I../config"

# Source modules

SRCDIR=$SRC/gpf2/tst

ln -sf $SRCDIR/drv $BUILD_DIR/$LIBNAME

cfile_plain ./drv/tr2.c
cfile_plain ./drv/tif2.c
cfile_plain ./drv/ser_tr.c
cfile_plain ./drv/titrc.c

cfile_symlink $SRCDIR/tst_pei.c
cfile_symlink $SRCDIR/tstdriver.c
cfile_symlink $SRCDIR/tif_version.c