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view scripts/cfg-template @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 3d772a6268c4
children 8cf3029429f3
line wrap: on
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[board.cfg]

BOARD 41
DSAMPLE_FULL_COLOR var

[chipset.cfg]

ANLG_FAM 2
ANLG_PG 0
CHIPSET var

[debug.cfg]

TI_NUC_MONITOR 0
TI_PROFILER 0

[dio.cfg]

DIOIL_CONFIG 0

[ffs.cfg]

TARGET 1
_RVF 1

[l1sw.cfg]

AMR var
CUST 0
DCO_ALGO 0
IDS var
L1_12NEIGH 1
L1_EOTD 0
L1_EOTD_QBIT_ACC 0
L1_GPRS var
L1_GTT 0
L1_MIDI 0
L1_VOICE_MEMO_AMR var
MELODY_E2 var
OP_L1_STANDALONE 0
OP_RIV_AUDIO 1
ORDER2_TX_TEMP_CAL 1
RAZ_VULSWITCH_REGAUDIO 0
SECURITY 0
SPEECH_RECO var
TESTMODE 1
TRACE_TYPE 4
VCXO_ALGO 1

[r2d.cfg]

R2D_ASM 0
R2D_LCD_TEST 0

[rf.cfg]

RF var
RF_FAM var
RF_PA var
RF_PG var

[rv.cfg]

RVTOOL 0
TEST 0
_GSM 1

[swconfig.cfg]

ALR 1
BT 0
DP 0
DWNLD 1
GSMLITE 0
L1_DYN_DSP_DWNLD var
LONG_JUMP 3
MOVE_IN_INTERNAL_RAM 1
OP_WCP 0
PMODE var
RVDATA_INTERNALRAM 0
SRVC var
TR_BAUD_CONFIG var
WCP_PROF 0

[sys.cfg]

DSP var
STD 6

[trace.cfg]

LAYER_DBG 0xFFFFFFFF
TRACE_LEVEL_FILTER 5