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view src/aci2/alr/alr_test/alr_ncell_steps.h @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 93999a60b835
children
line wrap: on
line source

T_STEP meas_rep_bs_pa_mfrms_2();
T_STEP meas_rep_bs_pa_mfrms_3();
T_STEP meas_rep_bs_pa_mfrms_4();
T_STEP meas_rep_bs_pa_mfrms_5();
T_STEP meas_rep_bs_pa_mfrms_6();
T_STEP meas_rep_bs_pa_mfrms_8();
T_STEP wait_ncsync_idle_2_14(int count);
T_STEP wait_ncsync_idle_2_31(int count);
T_STEP wait_ncsync_idle_3_33(int count);
T_STEP wait_ncsync_dedicated(int count);
T_STEP wait_ncsync_dedicated_1020A(int count);
T_STEP wait_ncsync_dedicated_102(int count);
T_STEP wait_ncsync_dedicated_102a(int count);
T_STEP wait_ncsync_dedicated_102b(int count);
T_STEP wait_ncsync_dedicated_102c(int count);
T_STEP sync_to_ncell_14_fails_once();
T_STEP ncell_bcch_read_fails_for_ncell_14();
T_STEP ncell_reporting_multiband_0_scell_is_gsm900();
T_STEP ncell_reporting_multiband_0_scell_is_gsm1800();
T_STEP ncell_sync_ncc_permitted_check();
T_STEP ncell_reporting_multiband_1_scell_is_gsm900();
T_STEP ncell_reporting_multiband_1_scell_is_gsm900_4ch();