FreeCalypso > hg > fc-magnetite
view cdg-hybrid/cdginc/p_8010_137_nas_include.val @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Thu, 02 Jan 2020 05:38:26 +0000 |
parents | e7a67accfad9 |
children |
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/* +--------------------------------------------------------------------------+ | PROJECT : PROTOCOL STACK | | FILE : p_8010_137_nas_include.val | | SOURCE : "sap\8010_137_nas_include.pdf" | | LastModified : "2004-06-09" | | IdAndVersion : "8010.137.02.017" | | SrcFileTime : "Thu Nov 29 09:28:24 2007" | | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | +--------------------------------------------------------------------------+ */ /* PRAGMAS * PREFIX : NAS * COMPATIBILITY_DEFINES : NO * ALWAYS_ENUM_IN_VAL_FILE: YES * ENABLE_GROUP: NO * CAPITALIZE_TYPENAME: NO */ #ifndef P_8010_137_NAS_INCLUDE_VAL #define P_8010_137_NAS_INCLUDE_VAL #define CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL #define CDG_ENTER__FILENAME _P_8010_137_NAS_INCLUDE_VAL #define CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL__FILE_TYPE CDGINC #define CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL__LAST_MODIFIED _2004_06_09 #define CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL__ID_AND_VERSION _8010_137_02_017 #define CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL__SRC_FILE_TIME _Thu_Nov_29_09_28_24_2007 #include "CDG_ENTER.h" #undef CDG_ENTER__P_8010_137_NAS_INCLUDE_VAL #undef CDG_ENTER__FILENAME /* * Enum to value table VAL_nsapi * CCDGEN:WriteEnum_Count==45 */ #ifndef __T_NAS_VAL_nsapi__ #define __T_NAS_VAL_nsapi__ typedef enum { NAS_NSAPI_0 = 0x0, /* escape mechanism for future extensions */ NAS_NSAPI_1 = 0x1, /* Point-To-Multipoint Multicast information */ NAS_NSAPI_2 = 0x2, /* reserved for future use */ NAS_NSAPI_3 = 0x3, /* reserved for future use */ NAS_NSAPI_4 = 0x4, /* reserved for future use */ NAS_NSAPI_5 = 0x5, /* dynamically allocated NSAPI value */ NAS_NSAPI_6 = 0x6, /* dynamically allocated NSAPI value */ NAS_NSAPI_7 = 0x7, /* dynamically allocated NSAPI value */ NAS_NSAPI_8 = 0x8, /* dynamically allocated NSAPI value */ NAS_NSAPI_9 = 0x9, /* dynamically allocated NSAPI value */ NAS_NSAPI_10 = 0xa, /* dynamically allocated NSAPI value */ NAS_NSAPI_11 = 0xb, /* dynamically allocated NSAPI value */ NAS_NSAPI_12 = 0xc, /* dynamically allocated NSAPI value */ NAS_NSAPI_13 = 0xd, /* dynamically allocated NSAPI value */ NAS_NSAPI_14 = 0xe, /* dynamically allocated NSAPI value */ NAS_NSAPI_15 = 0xf /* dynamically allocated NSAPI value */ }T_NAS_VAL_nsapi; #endif /* * Enum to value table VAL_dti_direction * CCDGEN:WriteEnum_Count==46 */ #ifndef __T_NAS_VAL_dti_direction__ #define __T_NAS_VAL_dti_direction__ typedef enum { NAS_HOME = 0x0, /* mapped to HOME from dti.h */ NAS_NEIGHBOR = 0x1 /* mapped to NEIGHBOR from dti.h */ }T_NAS_VAL_dti_direction; #endif /* * Enum to value table VAL_dti_conn * CCDGEN:WriteEnum_Count==47 */ #ifndef __T_NAS_VAL_dti_conn__ #define __T_NAS_VAL_dti_conn__ typedef enum { NAS_CONNECT_DTI = 0x0, /* Connect DTI connection. */ NAS_DISCONNECT_DTI = 0x1 /* Disconnect DTI connection. */ }T_NAS_VAL_dti_conn; #endif /* * Enum to value table VAL_dcomp * CCDGEN:WriteEnum_Count==48 */ #ifndef __T_NAS_VAL_dcomp__ #define __T_NAS_VAL_dcomp__ typedef enum { NAS_DCOMP_OFF = 0x0, /* compress neither direction */ NAS_DCOMP_ON = 0x1, /* compress MS to SGSN direction only */ NAS_DCOMP_V_42_BIS = 0x2 /* compress SGSN to MS direction only */ }T_NAS_VAL_dcomp; #endif /* * Enum to value table VAL_ppp_hc * CCDGEN:WriteEnum_Count==49 */ #ifndef __T_NAS_VAL_ppp_hc__ #define __T_NAS_VAL_ppp_hc__ typedef enum { NAS_PPP_HC_NOT_USED = 0x0, /* Header compression not used */ NAS_PPP_HC_RFC_1144_USED = 0x1 /* Van Jacobson is used */ }T_NAS_VAL_ppp_hc; #endif /* * Enum to value table VAL_hcomp * CCDGEN:WriteEnum_Count==50 */ #ifndef __T_NAS_VAL_hcomp__ #define __T_NAS_VAL_hcomp__ typedef enum { NAS_HCOMP_OFF = 0x0, /* compress neither direction */ NAS_HCOMP_ON = 0x1, /* compress MS to SGSN direction only */ NAS_HCOMP_RFC1144 = 0x2, /* compress SGSN to MS direction only */ NAS_HCOMP_RFC2507 = 0x3 /* compress both directions */ }T_NAS_VAL_hcomp; #endif /* * Enum to value table VAL_sync_event * CCDGEN:WriteEnum_Count==51 */ #ifndef __T_NAS_VAL_sync_event__ #define __T_NAS_VAL_sync_event__ typedef enum { NAS_SYNC_RESSOURCE_ASSIGNED = 0x20, /* Traffic channel resource assigned */ NAS_SYNC_CHANNEL_MODE_MODIFIED = 0x30 /* Channel mode modified */ }T_NAS_VAL_sync_event; #endif /* * Enum to value table VAL_ti * CCDGEN:WriteEnum_Count==52 */ #ifndef __T_NAS_VAL_ti__ #define __T_NAS_VAL_ti__ typedef enum { NAS_VAL_TI__RANGE_MIN = 0x0, /* minimum */ NAS_VAL_TI__RANGE_MAX = 0x6, /* maximum */ NAS_VAL_TI__RANGE_1_MIN = 0x8, /* minimum */ NAS_VAL_TI__RANGE_1_MAX = 0xe, /* maximum */ NAS_TI_RES_1 = 0x7, /* reserved */ NAS_TI_RES_2 = 0xf /* reserved */ }T_NAS_VAL_ti; #endif /* * Enum to value table VAL_ch_mode * CCDGEN:WriteEnum_Count==53 */ #ifndef __T_NAS_VAL_ch_mode__ #define __T_NAS_VAL_ch_mode__ typedef enum { NAS_CHM_SIG_ONLY = 0x0, /* signalling only */ NAS_CHM_SPEECH = 0x1, /* speech full rate or half rate version 1 */ NAS_CHM_SPEECH_V2 = 0x21, /* speech full rate or half rate version 2 */ NAS_CHM_SPEECH_V3 = 0x41, /* speech full rate or half rate version 3 */ NAS_CHM_DATA_9_6 = 0x3, /* data 9.6 kBit/s */ NAS_CHM_DATA_4_8 = 0xb, /* data 4.8 kBit/s */ NAS_CHM_DATA_2_4 = 0x13, /* data 2.4 kBit/s */ NAS_CHM_DATA_14_4 = 0xf /* data 14.4 kBit/s */ }T_NAS_VAL_ch_mode; #endif /* * Enum to value table VAL_ch_type * CCDGEN:WriteEnum_Count==54 */ #ifndef __T_NAS_VAL_ch_type__ #define __T_NAS_VAL_ch_type__ typedef enum { NAS_CH_SDCCH = 0x0, /* SDCCH channel */ NAS_CH_TCH_F = 0x1, /* TCH Fullrate */ NAS_CH_TCH_H = 0x2 /* TCH Halfrate */ }T_NAS_VAL_ch_type; #endif /* * Enum to value table VAL_k_ms_iwf * CCDGEN:WriteEnum_Count==55 */ #ifndef __T_NAS_VAL_k_ms_iwf__ #define __T_NAS_VAL_k_ms_iwf__ typedef enum { NAS_VAL_K_MS_IWF__RANGE_MIN = 0x0, /* minimum */ NAS_VAL_K_MS_IWF__RANGE_MAX = 0x3d /* maximum */ }T_NAS_VAL_k_ms_iwf; #endif /* * Enum to value table VAL_k_iwf_ms * CCDGEN:WriteEnum_Count==56 */ #ifndef __T_NAS_VAL_k_iwf_ms__ #define __T_NAS_VAL_k_iwf_ms__ typedef enum { NAS_VAL_K_IWF_MS__RANGE_MIN = 0x0, /* minimum */ NAS_VAL_K_IWF_MS__RANGE_MAX = 0x3d /* maximum */ }T_NAS_VAL_k_iwf_ms; #endif /* * Enum to value table VAL_pt * CCDGEN:WriteEnum_Count==57 */ #ifndef __T_NAS_VAL_pt__ #define __T_NAS_VAL_pt__ typedef enum { NAS_COMPR_TYPE_V42BIS = 0x0 /* V.42bis */ }T_NAS_VAL_pt; #endif /* * Enum to value table VAL_p0 * CCDGEN:WriteEnum_Count==58 */ #ifndef __T_NAS_VAL_p0__ #define __T_NAS_VAL_p0__ typedef enum { NAS_COMP_DIR_NONE = 0x0, /* compress in neither direction */ NAS_COMP_DIR_TRANSMIT = 0x1, /* compress in uplink direction only */ NAS_COMP_DIR_RECEIVE = 0x2, /* compress in downlink direction only */ NAS_COMP_DIR_BOTH = 0x3 /* compress in both directions */ }T_NAS_VAL_p0; #endif /* * Enum to value table VAL_p1 * CCDGEN:WriteEnum_Count==59 */ #ifndef __T_NAS_VAL_p1__ #define __T_NAS_VAL_p1__ typedef enum { NAS_VAL_P1__RANGE_MIN = 0x200, /* minimum */ NAS_VAL_P1__RANGE_MAX = 0xffff /* maximum */ }T_NAS_VAL_p1; #endif /* * Enum to value table VAL_p2 * CCDGEN:WriteEnum_Count==60 */ #ifndef __T_NAS_VAL_p2__ #define __T_NAS_VAL_p2__ typedef enum { NAS_VAL_P2__RANGE_MIN = 0x6, /* minimum */ NAS_VAL_P2__RANGE_MAX = 0xfa /* maximum */ }T_NAS_VAL_p2; #endif /* * Enum to value table VAL_rate * CCDGEN:WriteEnum_Count==61 */ #ifndef __T_NAS_VAL_rate__ #define __T_NAS_VAL_rate__ typedef enum { NAS_HALFRATE_4800 = 0x0, /* halfrate 4,8/6 Kb */ NAS_FULLRATE_4800 = 0x1, /* fullrate 4,8/6 Kb */ NAS_FULLRATE_9600 = 0x2, /* fullrate 9,6/12 Kb */ NAS_FULLRATE_14400 = 0x3 /* fullrate 13,4/14,4 Kb */ }T_NAS_VAL_rate; #endif /* * Enum to value table VAL_ack_flg * CCDGEN:WriteEnum_Count==62 */ #ifndef __T_NAS_VAL_ack_flg__ #define __T_NAS_VAL_ack_flg__ typedef enum { NAS_FLAG_ACK = 0x0, /* acknowledged */ NAS_FLAG_NAK = 0x1 /* not acknowledged */ }T_NAS_VAL_ack_flg; #endif /* * Enum to value table VAL_tft_pf_valid_bits * CCDGEN:WriteEnum_Count==63 */ #ifndef __T_NAS_VAL_tft_pf_valid_bits__ #define __T_NAS_VAL_tft_pf_valid_bits__ typedef enum { NAS_TFT_ID_RES = 0x0, /* Reserved */ NAS_TFT_ID_IPv4_SRC_ADDR_MASK = 0x1, /* source address and subnet mask */ NAS_TFT_ID_IPv6_SRC_ADDR_MASK = 0x2, /* source address and subnet mask */ NAS_TFT_ID_PROTOCOL_OR_NEXT_HDR = 0x4, /* IPv4 protocol number or IPv6 next header */ NAS_TFT_ID_DEST_PORT_RANGE = 0x8, /* destination port range */ NAS_TFT_ID_SRC_PORT_RANGE = 0x10, /* source port range */ NAS_TFT_ID_IPSEC_SPI = 0x20, /* IPSec security parameter index */ NAS_TFT_ID_TOS_AND_MASK = 0x40, /* IPv4 ToS or IPv6 traffic class) and mask */ NAS_TFT_ID_FLOW_LABEL = 0x80 /* IPv6 flow label */ }T_NAS_VAL_tft_pf_valid_bits; #endif /* * Enum to value table VAL_org_entity * CCDGEN:WriteEnum_Count==64 */ #ifndef __T_NAS_VAL_org_entity__ #define __T_NAS_VAL_org_entity__ typedef enum { NAS_ORG_ENTITY_CC = 0x0, /* Originator is CC */ NAS_ORG_ENTITY_SM = 0x1, /* Originator is SM */ NAS_ORG_ENTITY_SMS = 0x2, /* Originator is SMS */ NAS_ORG_ENTITY_SS = 0x3, /* Originator is SS */ NAS_ORG_ENTITY_UPM = 0x4, /* Originator is UPM */ NAS_ORG_ENTITY_CLT = 0x5 /* Originator is CLT (COMLIB test ) */ }T_NAS_VAL_org_entity; #endif /* * Enum to value table VAL_reset * CCDGEN:WriteEnum_Count==65 */ #ifndef __T_NAS_VAL_reset__ #define __T_NAS_VAL_reset__ typedef enum { NAS_RESET_NO = 0x0, /* no reset */ NAS_RESET_YES = 0x1 /* reset */ }T_NAS_VAL_reset; #endif /* * Enum to value table VAL_pkt_flow_id * CCDGEN:WriteEnum_Count==66 */ #ifndef __T_NAS_VAL_pkt_flow_id__ #define __T_NAS_VAL_pkt_flow_id__ typedef enum { NAS_PFI_BEST_EFFORT = 0x0, /* Best Effort */ NAS_PFI_SIGNALING = 0x1, /* Signalling */ NAS_PFI_SMS = 0x2, /* SMS */ NAS_PKT_FLOW_ID_NOT_PRES = 0xff /* Value FF is used to indicate when Packet Flow Identifier is not present. */ }T_NAS_VAL_pkt_flow_id; #endif /* * enum to UnionController ip_address * CCDGEN:WriteEnum_Count==67 */ #ifndef __T_NAS_ctrl_ip_address__ #define __T_NAS_ctrl_ip_address__ typedef enum { NAS_is_ip_not_present = 0x0, NAS_is_ipv4 = 0x1, NAS_is_ipv6 = 0x2 }T_NAS_ctrl_ip_address; #endif /* * enum to UnionController tft_pf_entry * CCDGEN:WriteEnum_Count==68 */ #ifndef __T_NAS_ctrl_tft_pf_entry__ #define __T_NAS_ctrl_tft_pf_entry__ typedef enum { NAS_is_tft_pf_ipv4 = 0x0, NAS_is_tft_pf_ipv6 = 0x1 }T_NAS_ctrl_tft_pf_entry; #endif /* * user defined constants */ #define NAS_SIZE_ENTITY_NAME (0x6) #define NAS_SIZE_TFT_FILTER (0x8) #define NAS_SIZE_IPv4_ADDR (0x4) #define NAS_SIZE_IPv6_ADDR (0x10) #define NAS_SIZE_NSAPI (0x10) #define NAS_FACILITY_LEN (0xfb) #include "CDG_LEAVE.h" #endif