FreeCalypso > hg > fc-magnetite
view cdg211/cdginc/p_l2r.val @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 02 Jan 2020 05:38:26 +0000 |
| parents | 56abf6cf8a0b |
| children |
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/* +--------------------------------------------------------------------------+ | PROJECT : PROTOCOL STACK | | FILE : p_l2r.val | | SOURCE : "__out__\g23m_dfile\prim\l2r.pdf" | | LastModified : "2001-10-31" | | IdAndVersion : "8411.102.01.124" | | SrcFileTime : "Mon Nov 24 15:49:40 2003" | | Generated by CCDGEN_2.5.5 on Fri Jun 08 13:59:15 2007 | | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | +--------------------------------------------------------------------------+ */ /* PRAGMAS * PREFIX : NONE * COMPATIBILITY_DEFINES : NO (require PREFIX) * ALWAYS_ENUM_IN_VAL_FILE: NO * ENABLE_GROUP: NO * CAPITALIZE_TYPENAME: NO */ #ifndef P_L2R_VAL #define P_L2R_VAL #define CDG_ENTER__P_L2R_VAL #define CDG_ENTER__FILENAME _P_L2R_VAL #define CDG_ENTER__P_L2R_VAL__FILE_TYPE CDGINC #define CDG_ENTER__P_L2R_VAL__LAST_MODIFIED _2001_10_31 #define CDG_ENTER__P_L2R_VAL__ID_AND_VERSION _8411_102_01_124 #define CDG_ENTER__P_L2R_VAL__SRC_FILE_TIME _Mon_Nov_24_15_49_40_2003 #include "CDG_ENTER.h" #undef CDG_ENTER__P_L2R_VAL #undef CDG_ENTER__FILENAME /* * Value constants for VAL_pt */ #define L2R_COMPR_TYPE_V42BIS (0x0) /* V.42bis */ /* * Value constants for VAL_p0 */ #define L2R_COMP_DIR_NONE (0x0) /* compress in neither direction */ #define L2R_COMP_DIR_TRANSMIT (0x1) /* compress in uplink direction only */ #define L2R_COMP_DIR_RECEIVE (0x2) /* compress in downlink direction only */ #define L2R_COMP_DIR_BOTH (0x3) /* compress in both directions */ /* * Value constants for VAL_uil2p */ #define L2R_ISO6429 (0x0) /* ISO6429, codeset 0, DC1/DC3 (with flow control) */ #define L2R_COPnoFlCt (0x1) /* Character Oriented Protocol with No Flow Control */ /* * Value constants for VAL_rate */ #define L2R_HALFRATE_4800 (0x0) /* halfrate 4,8/6 kBit */ #define L2R_FULLRATE_4800 (0x1) /* fullrate 4,8/6 kBit */ #define L2R_FULLRATE_9600 (0x2) /* fullrate 9,6/12 kBit */ #define L2R_FULLRATE_14400 (0x3) /* fullrate 13,4/14,4 kBit */ /* * Value constants for VAL_ack_flg */ #define L2R_ACK (0x0) /* acknowledged */ #define L2R_NAK (0x1) /* not acknowledged */ /* * Value constants for VAL_cause */ #define CAUSE_DUMMY (0x0) /* The following causes can occur within this primitive: all those possible within the RLP_ERROR_IND primitive of the RLP SAP */ /* * Value constants for VAL_dti_conn */ #define L2R_CONNECT_DTI (0x0) /* Connect DTI to L2R */ #define L2R_DISCONNECT_DTI (0x1) /* Connect DTI to upper layer */ /* * Value constants for VAL_link_id */ #define L2R_LINK_ID_DEFAULT (0x0) /* Default link id */ /* * Value constants for VAL_dti_direction */ #define L2R_DTI_NORMAL (0x0) /* DTI used normally */ #define L2R_DTI_INVERTED (0x1) /* DTI is inverted */ /* * user defined constants */ #define L2R_K_MS_IWF_MIN (0x0) #define L2R_K_MS_IWF_MAX (0x3d) #define L2R_K_MS_IWF_DEF (0x3d) #define L2R_K_IWF_MS_MIN (0x0) #define L2R_K_IWF_MS_MAX (0x3d) #define L2R_K_IWF_MS_DEF (0x3d) #define L2R_T1_MIN_FULLRATE_14400 (0x2a) #define L2R_T1_MIN_FULLRATE_9600 (0x26) #define L2R_T1_MIN_FULLRATE_4800 (0x2c) #define L2R_T1_MIN_HALFRATE_4800 (0x3c) #define L2R_T1_MIN (0x26) #define L2R_T1_MAX (0xff) #define L2R_T1_DEF_FULLRATE_14400 (0x34) #define L2R_T1_DEF_FULLRATE_9600 (0x30) #define L2R_T1_DEF_FULLRATE_4800 (0x36) #define L2R_T1_DEF_HALFRATE_4800 (0x4e) #define L2R_T1_DEF (0x30) #define L2R_T2_MIN (0x0) #define L2R_T2_MAX (0xff) #define L2R_T2_DEF (0x14) #define L2R_N2_MIN (0x1) #define L2R_N2_MAX (0xff) #define L2R_N2_DEF (0x6) #define L2R_PT_MIN (0x0) #define L2R_PT_MAX (0x0) #define L2R_PT_DEF (0x0) #define L2R_P0_MIN (0x0) #define L2R_P0_MAX (0x0) #define L2R_P0_DEF (0x0) #define L2R_P1_MIN (0x200) #define L2R_P1_MAX (0xffff) #define L2R_P1_DEF (0x200) #define L2R_P2_MIN (0x6) #define L2R_P2_MAX (0xfa) #define L2R_P2_DEF (0x6) #define L2R_BYTES_PER_PRIM_MIN (0x19) #define L2R_BYTES_PER_PRIM_MAX (0xfa) #define L2R_BYTES_PER_PRIM_DEF (0xfa) #define L2R_BUFFER_SIZE_MIN (0x800) #define L2R_BUFFER_SIZE_MAX (0x1000) #define L2R_BUFFER_SIZE_DEF (0x800) #define L2R_ENTITY_NAME_LEN (0x6) #include "CDG_LEAVE.h" #endif