FreeCalypso > hg > fc-magnetite
view cdg211/cdginc/p_uart.h @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 02 Jan 2020 05:38:26 +0000 |
| parents | 56abf6cf8a0b |
| children |
line wrap: on
line source
/* +--------------------------------------------------------------------------+ | PROJECT : PROTOCOL STACK | | FILE : p_uart.h | | SOURCE : "__out__\g23m_dfile\prim\uart.pdf" | | LastModified : "2002-03-11" | | IdAndVersion : "8441.117.99.014" | | SrcFileTime : "Tue Nov 30 11:21:48 2004" | | Generated by CCDGEN_2.5.5 on Fri Jun 08 13:59:16 2007 | | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | +--------------------------------------------------------------------------+ */ /* PRAGMAS * PREFIX : NONE * COMPATIBILITY_DEFINES : NO (require PREFIX) * ALWAYS_ENUM_IN_VAL_FILE: NO * ENABLE_GROUP: NO * CAPITALIZE_TYPENAME: NO */ #ifndef P_UART_H #define P_UART_H #define CDG_ENTER__P_UART_H #define CDG_ENTER__FILENAME _P_UART_H #define CDG_ENTER__P_UART_H__FILE_TYPE CDGINC #define CDG_ENTER__P_UART_H__LAST_MODIFIED _2002_03_11 #define CDG_ENTER__P_UART_H__ID_AND_VERSION _8441_117_99_014 #define CDG_ENTER__P_UART_H__SRC_FILE_TIME _Tue_Nov_30_11_21_48_2004 #include "CDG_ENTER.h" #undef CDG_ENTER__P_UART_H #undef CDG_ENTER__FILENAME #include "p_uart.val" #ifndef __T_comPar__ #define __T_comPar__ /* * Parameters of serial link * CCDGEN:WriteStruct_Count==2206 */ typedef struct { U8 speed; /*< 0: 1> baud rate */ U8 bpc; /*< 1: 1> bits per character */ U8 nsb; /*< 2: 1> stop bits */ U8 parity; /*< 3: 1> parity of serial link */ U8 flow_rx; /*< 4: 1> flow control mode RX */ U8 flow_tx; /*< 5: 1> flow control mode TX */ U8 xon_valid; /*< 6: 1> indicator whether xon is valid */ U8 xon; /*< 7: 1> XOn character for XON/XOFF flow control */ U8 xoff_valid; /*< 8: 1> indicator whether xoff is valid */ U8 xoff; /*< 9: 1> XOff character for XON/XOFF flow control */ U8 esc_valid; /*< 10: 1> indicator whether esc_char and esc_gp are valid */ U8 esc_char; /*< 11: 1> escape character */ U16 esc_gp; /*< 12: 2> guard period */ U8 _align0; /*< 14: 1> alignment */ U8 _align1; /*< 15: 1> alignment */ } T_comPar; #endif /* * End of substructure section, begin of primitive definition section */ #ifndef __T_UART_PARAMETERS_REQ__ #define __T_UART_PARAMETERS_REQ__ /* * * CCDGEN:WriteStruct_Count==2207 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ T_comPar comPar; /*< 4: 16> Parameters of serial link */ } T_UART_PARAMETERS_REQ; #endif #ifndef __T_UART_PARAMETERS_CNF__ #define __T_UART_PARAMETERS_CNF__ /* * * CCDGEN:WriteStruct_Count==2208 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_PARAMETERS_CNF; #endif #ifndef __T_UART_PARAMETERS_IND__ #define __T_UART_PARAMETERS_IND__ /* * * CCDGEN:WriteStruct_Count==2209 */ typedef struct { U8 uart_instances; /*< 0: 1> number of UART instances */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_PARAMETERS_IND; #endif #ifndef __T_UART_DTI_REQ__ #define __T_UART_DTI_REQ__ /* * * CCDGEN:WriteStruct_Count==2210 */ typedef struct { U8 dti_conn; /*< 0: 1> DTI connect */ U8 device; /*< 1: 1> device number */ U8 dlci; /*< 2: 1> data link connection identifier */ U8 direction; /*< 3: 1> direction of the DTI link */ U32 link_id; /*< 4: 4> identifier of DTI connection */ U32 entity_name; /*< 8: 4> communication entity name */ } T_UART_DTI_REQ; #endif #ifndef __T_UART_DTI_CNF__ #define __T_UART_DTI_CNF__ /* * * CCDGEN:WriteStruct_Count==2211 */ typedef struct { U8 dti_conn; /*< 0: 1> DTI connect */ U8 device; /*< 1: 1> device number */ U8 dlci; /*< 2: 1> data link connection identifier */ U8 _align0; /*< 3: 1> alignment */ } T_UART_DTI_CNF; #endif #ifndef __T_UART_DTI_IND__ #define __T_UART_DTI_IND__ /* * * CCDGEN:WriteStruct_Count==2212 */ typedef struct { U8 dti_conn; /*< 0: 1> DTI connect */ U8 device; /*< 1: 1> device number */ U8 dlci; /*< 2: 1> data link connection identifier */ U8 _align0; /*< 3: 1> alignment */ } T_UART_DTI_IND; #endif #ifndef __T_UART_DISABLE_REQ__ #define __T_UART_DISABLE_REQ__ /* * * CCDGEN:WriteStruct_Count==2213 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_DISABLE_REQ; #endif #ifndef __T_UART_DISABLE_CNF__ #define __T_UART_DISABLE_CNF__ /* * * CCDGEN:WriteStruct_Count==2214 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_DISABLE_CNF; #endif #ifndef __T_UART_RING_REQ__ #define __T_UART_RING_REQ__ /* * * CCDGEN:WriteStruct_Count==2215 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 line_state; /*< 2: 1> state of line */ U8 _align0; /*< 3: 1> alignment */ } T_UART_RING_REQ; #endif #ifndef __T_UART_RING_CNF__ #define __T_UART_RING_CNF__ /* * * CCDGEN:WriteStruct_Count==2216 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 _align0; /*< 2: 1> alignment */ U8 _align1; /*< 3: 1> alignment */ } T_UART_RING_CNF; #endif #ifndef __T_UART_DCD_REQ__ #define __T_UART_DCD_REQ__ /* * * CCDGEN:WriteStruct_Count==2217 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 line_state; /*< 2: 1> state of line */ U8 _align0; /*< 3: 1> alignment */ } T_UART_DCD_REQ; #endif #ifndef __T_UART_DCD_CNF__ #define __T_UART_DCD_CNF__ /* * * CCDGEN:WriteStruct_Count==2218 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 _align0; /*< 2: 1> alignment */ U8 _align1; /*< 3: 1> alignment */ } T_UART_DCD_CNF; #endif #ifndef __T_UART_ESCAPE_REQ__ #define __T_UART_ESCAPE_REQ__ /* * * CCDGEN:WriteStruct_Count==2219 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 detection; /*< 2: 1> escape sequence detection */ U8 _align0; /*< 3: 1> alignment */ } T_UART_ESCAPE_REQ; #endif #ifndef __T_UART_ESCAPE_CNF__ #define __T_UART_ESCAPE_CNF__ /* * * CCDGEN:WriteStruct_Count==2220 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 _align0; /*< 2: 1> alignment */ U8 _align1; /*< 3: 1> alignment */ } T_UART_ESCAPE_CNF; #endif #ifndef __T_UART_DETECTED_IND__ #define __T_UART_DETECTED_IND__ /* * * CCDGEN:WriteStruct_Count==2221 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 cause; /*< 2: 1> cause of indication */ U8 _align0; /*< 3: 1> alignment */ } T_UART_DETECTED_IND; #endif #ifndef __T_UART_ERROR_IND__ #define __T_UART_ERROR_IND__ /* * * CCDGEN:WriteStruct_Count==2222 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 error; /*< 2: 1> error code */ U8 _align0; /*< 3: 1> alignment */ } T_UART_ERROR_IND; #endif #ifndef __T_UART_MUX_START_REQ__ #define __T_UART_MUX_START_REQ__ /* * * CCDGEN:WriteStruct_Count==2223 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 mode; /*< 1: 1> transparency mechanism */ U8 frame_type; /*< 2: 1> type of frame */ U8 _align0; /*< 3: 1> alignment */ U16 n1; /*< 4: 2> maximum frame size */ U8 t1; /*< 6: 1> acknowledgement timer */ U8 n2; /*< 7: 1> maximum numer of retransmissions */ U8 t2; /*< 8: 1> response timer for the multiplexer control channel */ U8 t3; /*< 9: 1> wake up response timer */ U8 _align1; /*< 10: 1> alignment */ U8 _align2; /*< 11: 1> alignment */ } T_UART_MUX_START_REQ; #endif #ifndef __T_UART_MUX_START_CNF__ #define __T_UART_MUX_START_CNF__ /* * * CCDGEN:WriteStruct_Count==2224 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_START_CNF; #endif #ifndef __T_UART_MUX_DLC_ESTABLISH_IND__ #define __T_UART_MUX_DLC_ESTABLISH_IND__ /* * * CCDGEN:WriteStruct_Count==2225 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 convergence; /*< 2: 1> convergence layer */ U8 _align0; /*< 3: 1> alignment */ U16 n1; /*< 4: 2> maximum frame size */ U8 service; /*< 6: 1> service on DLC */ U8 _align1; /*< 7: 1> alignment */ } T_UART_MUX_DLC_ESTABLISH_IND; #endif #ifndef __T_UART_MUX_DLC_ESTABLISH_RES__ #define __T_UART_MUX_DLC_ESTABLISH_RES__ /* * * CCDGEN:WriteStruct_Count==2226 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U16 n1; /*< 2: 2> maximum frame size */ } T_UART_MUX_DLC_ESTABLISH_RES; #endif #ifndef __T_UART_MUX_DLC_RELEASE_REQ__ #define __T_UART_MUX_DLC_RELEASE_REQ__ /* * * CCDGEN:WriteStruct_Count==2227 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 _align0; /*< 2: 1> alignment */ U8 _align1; /*< 3: 1> alignment */ } T_UART_MUX_DLC_RELEASE_REQ; #endif #ifndef __T_UART_MUX_DLC_RELEASE_IND__ #define __T_UART_MUX_DLC_RELEASE_IND__ /* * * CCDGEN:WriteStruct_Count==2228 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 dlci; /*< 1: 1> data link connection identifier */ U8 _align0; /*< 2: 1> alignment */ U8 _align1; /*< 3: 1> alignment */ } T_UART_MUX_DLC_RELEASE_IND; #endif #ifndef __T_UART_MUX_SLEEP_REQ__ #define __T_UART_MUX_SLEEP_REQ__ /* * * CCDGEN:WriteStruct_Count==2229 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_SLEEP_REQ; #endif #ifndef __T_UART_MUX_SLEEP_IND__ #define __T_UART_MUX_SLEEP_IND__ /* * * CCDGEN:WriteStruct_Count==2230 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_SLEEP_IND; #endif #ifndef __T_UART_MUX_WAKEUP_REQ__ #define __T_UART_MUX_WAKEUP_REQ__ /* * * CCDGEN:WriteStruct_Count==2231 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_WAKEUP_REQ; #endif #ifndef __T_UART_MUX_WAKEUP_IND__ #define __T_UART_MUX_WAKEUP_IND__ /* * * CCDGEN:WriteStruct_Count==2232 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_WAKEUP_IND; #endif #ifndef __T_UART_MUX_CLOSE_REQ__ #define __T_UART_MUX_CLOSE_REQ__ /* * * CCDGEN:WriteStruct_Count==2233 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_CLOSE_REQ; #endif #ifndef __T_UART_MUX_CLOSE_IND__ #define __T_UART_MUX_CLOSE_IND__ /* * * CCDGEN:WriteStruct_Count==2234 */ typedef struct { U8 device; /*< 0: 1> device number */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ } T_UART_MUX_CLOSE_IND; #endif #ifndef __T_UART_DRIVER_SENT_IND__ #define __T_UART_DRIVER_SENT_IND__ /* * * CCDGEN:WriteStruct_Count==2235 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_SENT_IND; #endif #ifndef __T_UART_DRIVER_RECEIVED_IND__ #define __T_UART_DRIVER_RECEIVED_IND__ /* * * CCDGEN:WriteStruct_Count==2236 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_RECEIVED_IND; #endif #ifndef __T_UART_DRIVER_FLUSHED_IND__ #define __T_UART_DRIVER_FLUSHED_IND__ /* * * CCDGEN:WriteStruct_Count==2237 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_FLUSHED_IND; #endif #ifndef __T_UART_DRIVER_CONNECT_IND__ #define __T_UART_DRIVER_CONNECT_IND__ /* * * CCDGEN:WriteStruct_Count==2238 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_CONNECT_IND; #endif #ifndef __T_UART_DRIVER_DISCONNECT_IND__ #define __T_UART_DRIVER_DISCONNECT_IND__ /* * * CCDGEN:WriteStruct_Count==2239 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_DISCONNECT_IND; #endif #ifndef __T_UART_DRIVER_CLEAR_IND__ #define __T_UART_DRIVER_CLEAR_IND__ /* * * CCDGEN:WriteStruct_Count==2240 */ typedef struct { U32 devId; /*< 0: 4> device ID */ } T_UART_DRIVER_CLEAR_IND; #endif #include "CDG_LEAVE.h" #endif