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view src/cs/drivers/drv_app/lcc/lcc_env.h @ 629:3231dd9b38c1

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armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively, and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code for C-Sample and earlier turns them into GPIOs configured as outputs also driving 1 - so far, so good - but TI's code for BOARD 41 (which covers D-Sample, Leonardo and all real world Calypso devices derived from the latter) switches them from MCUEN to GPIOs, but then leaves them as inputs. Given that the hardware powerup state of these two pins is outputs driving 1, every Calypso board design MUST be compatible with such driving; typically these GPIO signals will be either unused and unconnected or connected as outputs driving some peripheral. Turning these pins into GPIO inputs will result in floating inputs on every reasonably-wired board, thus I am convinced that this configuration is nothing but a bug on the part of whoever wrote this code at TI. This floating input bug had already been fixed earlier for GTA modem and FCDEV3B targets; the present change makes the fix unconditional for all "classic" targets. The newly affected targets are D-Sample, Leonardo, Tango and GTM900.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Jan 2020 05:38:26 +0000
parents 945cf7f506b2
children
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/*******************************************************************************
 *
 * PWR_ENV.H
 *
 *
 * (C) Texas Instruments 2001
 *
 ******************************************************************************/

#ifndef __LCC_ENV_H__
#define __LCC_ENV_H__

#include "rvm/rvm_gen.h"
#include "lcc/lcc_api.h"

#include "rvf/rvf_pool_size.h"	/* Stack & Memory Bank sizes definitions */

#define LCC_TASK_VERSION 0x0001 

#define LCC_MAILBOX_USED   RVF_TASK_MBOX_1

/* memory bank size and watermark */
#define LCC_MB_PRIM_SIZE            LCC_MB1_SIZE

#define LCC_MB_PRIM_WATERMARK     (LCC_MB_PRIM_SIZE)

#define LCC_MB_PRIM_INC_SIZE        0
#define LCC_MB_PRIM_INC_WATERMARK   0

extern T_PWR_CTRL_BLOCK *pwr_ctrl;
extern T_PWR_CFG_BLOCK *pwr_cfg;

/* Prototypes */

T_RVM_RETURN lcc_get_info (T_RVM_INFO_SWE  *infoSWE);

T_RVM_RETURN pwr_set_info( T_RVF_ADDR_ID  addr_id,
                           T_RV_RETURN    return_path[],
                           T_RVF_MB_ID    mbId[],
                           T_RVM_RETURN   (*callBackFct) (T_RVM_NAME SWEntName,
                           T_RVM_RETURN errorCause,
                           T_RVM_ERROR_TYPE errorType,
                           T_RVM_STRING errorMsg));

T_RVM_RETURN pwr_init (void);
T_RVM_RETURN pwr_start (void);
T_RVM_RETURN pwr_stop (T_RV_HDR *msg);
T_RVM_RETURN pwr_kill (void);


#endif /* __LCC_ENV_H__ */