view src/cs/drivers/drv_app/lcc/lcc_tm_i.h @ 629:3231dd9b38c1

armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively, and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code for C-Sample and earlier turns them into GPIOs configured as outputs also driving 1 - so far, so good - but TI's code for BOARD 41 (which covers D-Sample, Leonardo and all real world Calypso devices derived from the latter) switches them from MCUEN to GPIOs, but then leaves them as inputs. Given that the hardware powerup state of these two pins is outputs driving 1, every Calypso board design MUST be compatible with such driving; typically these GPIO signals will be either unused and unconnected or connected as outputs driving some peripheral. Turning these pins into GPIO inputs will result in floating inputs on every reasonably-wired board, thus I am convinced that this configuration is nothing but a bug on the part of whoever wrote this code at TI. This floating input bug had already been fixed earlier for GTA modem and FCDEV3B targets; the present change makes the fix unconditional for all "classic" targets. The newly affected targets are D-Sample, Leonardo, Tango and GTM900.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Jan 2020 05:38:26 +0000
parents 945cf7f506b2
children
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/******************************************************************************
 * Power Task (pwr)
 * Design and coding by Svend Kristian Lindholm, skl@ti.com
 *
 * PWR ETM interface
 *
 * $Id: pwr_tm_i.h 1.1 Wed, 20 Aug 2003 10:22:37 +0200 skl $
 *
 ******************************************************************************/

#ifndef _LCC_TM_I_H_
#define _LCC_TM_I_H_

#define PWR_CFG_ID_SIZE      2
#define PWR_COMMON_CFG_SIZE 14
#define PWR_BAT_CFG_SIZE    36
#define PWR_TEMP_CFG_SIZE   72
#define PWR_MMI_CFG_SIZE     2
#define PWR_CHG_CFG_SIZE     8
#define PWR_I2V_CAL_SIZE     6
#define PWR_VBAT_CAL_SIZE    6
#define PWR_DYNAMIC_SIZE     1
#define PWR_TMASK_SIZE       4

// This enumeration should be shared with the PC test mode side
enum {
    PWR_CFG_ID = 0,
    PWR_COMMON,
    PWR_CHG,
    PWR_BAT,
    PWR_TEMP,
    PWR_MMI,
    PWR_I2V_CAL = 10,
    PWR_VBAT_CAL,
    PWR_MMI_TEST = 15,
    PWR_DYNAMIC = 20,
    PWR_TRACE_MASK= 21
} ;

// Test mode indication mail sent to ETM
// NOTE: Also used as request mail
struct etm_tm_ind_s {
     T_RV_HDR header;
     uint8 size;
     uint8 status;
     uint8 data[127];
};

typedef struct etm_tm_ind_s    T_ETM_TM_IND; // Use same buffer in both directions

#endif //_LCC_TM_I_H_