view src/cs/services/audio/audio_mode_i.h @ 629:3231dd9b38c1

armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively, and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code for C-Sample and earlier turns them into GPIOs configured as outputs also driving 1 - so far, so good - but TI's code for BOARD 41 (which covers D-Sample, Leonardo and all real world Calypso devices derived from the latter) switches them from MCUEN to GPIOs, but then leaves them as inputs. Given that the hardware powerup state of these two pins is outputs driving 1, every Calypso board design MUST be compatible with such driving; typically these GPIO signals will be either unused and unconnected or connected as outputs driving some peripheral. Turning these pins into GPIO inputs will result in floating inputs on every reasonably-wired board, thus I am convinced that this configuration is nothing but a bug on the part of whoever wrote this code at TI. This floating input bug had already been fixed earlier for GTA modem and FCDEV3B targets; the present change makes the fix unconditional for all "classic" targets. The newly affected targets are D-Sample, Leonardo, Tango and GTM900.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Jan 2020 05:38:26 +0000
parents 838eeafb0051
children
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/****************************************************************************/
/*                                                                          */
/*  File Name:  audio_mode_i.h                                              */
/*                                                                          */
/*  Purpose:  This file contains symbolic constant used for the audio mode  */
/*                                                                          */
/*  Version   0.1                                                           */
/*                                                                          */
/*  Date         Modification                                               */
/*  ------------------------------------                                    */
/*  18 Jan 2002  Create                                                     */
/*                                                                          */
/*  Author       Francois Mazard                                            */
/*                                                                          */
/* (C) Copyright 2001 by Texas Instruments Incorporated, All Rights Reserved*/
/****************************************************************************/

#include "rv/rv_defined_swe.h"
#ifdef RVM_AUDIO_MAIN_SWE

  #ifndef __AUDIO_MODE_I_H_
    #define __AUDIO_MODE_I_H_

    #ifdef __cplusplus
      extern "C"
        {
    #endif

    #if (ANLG_FAM == 1)
      /* Register mapping for OMEGA, NAUSICA */

      /* VBCR register */
      #define AUDIO_VBCR_VFBYP        (0x0200)
      #define AUDIO_VBCR_VBDFAUXG     (0x0100)
      #define AUDIO_VBCR_VSYNC        (0x0080)
      #define AUDIO_VBCR_VCLKMODE     (0x0040)
      #define AUDIO_VBCR_VALOOP       (0x0020)
      #define AUDIO_VBCR_MICBIAS      (0x0010)
      #define AUDIO_VBCR_VULSWITCH    (0x0008)
      #define AUDIO_VBCR_VBUZ         (0x0004)
      #define AUDIO_VBCR_VDLEAR       (0x0002)
      #define AUDIO_VBCR_VDLAUX       (0x0001)

      /* VBUR */
      #define AUDIO_VBUR_DXEN         (0x0200)
      #define AUDIO_VBUR_VDLST        (0x000F)
      #define AUDIO_VBUR_VULPG        (0x001F)

      /* VBDR */
      #define AUDIO_VBDR_VDLPG        (0x000F)
      #define AUDIO_VBDR_VOLCTL       (0x000F)
    #endif
    #if (ANLG_FAM == 2)
      /* Register mapping for IOTA */

      /* VBCR register */
      #define AUDIO_VBCR_VFBYP        (0x0200)
      #define AUDIO_VBCR_VBDFAUXG     (0x0100)
      #define AUDIO_VBCR_VSYNC        (0x0080)
      #define AUDIO_VBCR_VCLKMODE     (0x0040)
      #define AUDIO_VBCR_VALOOP       (0x0020)
      #define AUDIO_VBCR_MICBIAS      (0x0010)
      #define AUDIO_VBCR_VULSWITCH    (0x0008)
      #define AUDIO_VBCR_VBUZ         (0x0004)
      #define AUDIO_VBCR_VDLEAR       (0x0002)
      #define AUDIO_VBCR_VDLAUX       (0x0001)

      /* VBCR2 */
      #define AUDIO_VBCR2_MICBIASEL   (0x0001)
      #define AUDIO_VBCR2_VDLHSO      (0x0002)
      #define AUDIO_VBCR2_MICNAUX     (0x0004)

      /* VBUR */
      #define AUDIO_VBUR_DXEN         (0x0200)
      #define AUDIO_VBUR_VDLST        (0x000F)
      #define AUDIO_VBUR_VULPG        (0x001F)

      /* VBDR */
      #define AUDIO_VBDR_VDLPG        (0x000F)
      #define AUDIO_VBDR_VOLCTL       (0x000F)
    #endif
    #if (ANLG_FAM == 3)
      /* Register mapping for SYREN */

      /* VBCR register */
      #define AUDIO_VBCR_VFBYP        (0x0200)
      #define AUDIO_VBCR_VBDFAUXG     (0x0100)
      #define AUDIO_VBCR_VSYNC        (0x0080)
      #define AUDIO_VBCR_VCLKMODE     (0x0040)
      #define AUDIO_VBCR_VALOOP       (0x0020)
      #define AUDIO_VBCR_MICBIAS      (0x0010)
      #define AUDIO_VBCR_VULSWITCH    (0x0008)

      /* VBCR2 */
      #define AUDIO_VBCR2_MICBIASEL   (0x0004)

      /* VBUR */
      #define AUDIO_VBUR_DXEN         (0x0200)
      #define AUDIO_VBUR_VDLST        (0x01E0)
      #define AUDIO_VBUR_VULPG        (0x001F)

      /* VBDR */
      #define AUDIO_VBDR_VDLPG        (0x000F)
      #define AUDIO_VBDR_VOLCTL       (0x0070)
    #endif

    #ifdef __cplusplus
      }
    #endif

  #endif /* __AUDIO_MODE_I_H_ */
#endif /* #ifdef RVM_AUDIO_MAIN_SWE */