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view src/cs/system/main/init.asm @ 636:57e67ca2e1cb

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pcmdata.c: default +CGMI to "FreeCalypso" and +CGMM to model The present change has no effect whatsoever on Falconia-made and Openmoko-made devices on which /pcm/CGMI and /pcm/CGMM files have been programmed in FFS with sensible ID strings by the respective factories, but what should AT+CGMI and AT+CGMM queries return when the device is a Huawei GTM900 or Tango modem that has been converted to FreeCalypso with a firmware change? Before the present change they would return compiled-in defaults of "<manufacturer>" and "<model>", respectively; with the present change the firmware will self-identify as "FreeCalypso GTM900-FC" or "FreeCalypso Tango" on the two respective targets. This firmware identification will become important if someone incorporates an FC-converted GTM900 or Tango modem into a ZeroPhone-style smartphone where some high-level software like ofono will be talking to the modem and will need to properly identify this modem as FreeCalypso, as opposed to some other AT command modem flavor with different quirks. In technical terms, the compiled-in default for the AT+CGMI query (which will always be overridden by the /pcm/CGMI file in FFS if one is present) is now "FreeCalypso" in all configs on all targets; the compiled-in default for the AT+CGMM query (likewise always overridden by /pcm/CGMM if present) is "GTM900-FC" if CONFIG_TARGET_GTM900 or "Tango" if CONFIG_TARGET_TANGO or the original default of "<model>" otherwise.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 19 Jan 2020 20:14:58 +0000
parents a7ed7d4483b0
children
line wrap: on
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;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 1987, (C) Copyright 1996 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename       	: init.asm
;
;   Description    	: Environment configuration
;
;   Project        	: drivers
;
;   Author         	: pmonteil@tif.ti.com Patrice Monteil.
;
;   Version number	: 1.4
;
;   Date and time	: 03/06/01 10:44:19
;
;   Previous delta 	: 12/19/00 14:28:47
;
;   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_C_SAMPLE_REQ1145_BIS/drivers1/board_7/SCCS/s.init.asm
;
;   Sccs Id  (SID)       : '@(#) init.asm 1.4 03/06/01 10:44:19 '
;
; 
;*****************************************************************************

; use in int.s for first initializations 

  .if BOARD = 6

  .if CHIPSET != 12
CS0_MEM_REG  .short  0x2A0	;ROM   init : 0 WS, 16 bits, little
CS1_MEM_REG  .short  0x281	;RAM   init : 1 WS, 8 bits, little
CS2_MEM_REG  .short  0x2A1	;RAM   init : 1 WS, 16 bits, little
CS3_MEM_REG  .short  0x283	;RAM   init : 5 WS, 8 bits, little
CS4_MEM_REG  .short  0xe85	;RAM   init : 5 WS, 8 bits, little
  .endif

  .if CHIPSET = 3
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
  .elseif CHIPSET = 4
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
  .elseif CHIPSET = 5
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
  .elseif CHIPSET = 6
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
  .elseif CHIPSET = 7
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG  .short  0x040	;Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
  .elseif CHIPSET = 8
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG  .short  0x040	;Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
  .elseif CHIPSET = 10
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG  .short  0x040	;Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
  .elseif CHIPSET = 11
CS6_MEM_REG  .short  0x0C0	;Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG  .short  0x040	;Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
  .elseif CHIPSET = 12
CS0_MEM_REG  .short  0x2A1	;CALYPSO PLUS TEST MODE - TO BE ERASED - RAM   init : 1 WS, 16 bits, little
CS4_MEM_REG  .short  0x2A1	;RAM   init : 1 WS, 16 bits, little
CS5_MEM_REG  .short  0x2A1	;ROM   init : 0 WS, 16 bits, little
  .endif ; CHIPSET = 3, 4, 5, 6, 7, 8, 10 or 11 or 12
  
  .elseif BOARD = 7

CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
   .if OP_WCP = 1
CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
   .else
CS1_MEM_REG   .short  0x2a0  ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
   .endif
CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
CS4_MEM_REG   .short  0x281  ; 1 Dummy Cycle  8 bit 1 WS SW BP enable
    .if CHIPSET = 3
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .elseif CHIPSET = 4
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .elseif CHIPSET = 5
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .elseif CHIPSET = 6
   .if OP_WCP = 1
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .else
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .endif
    .endif ; CHIPSET = 3, 4, 5 or 6

  .elseif BOARD = 8

CS0_MEM_REG   .short  0x2a0  ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
CS4_MEM_REG   .short  0xe85  ; default reset value
    .if CHIPSET = 4
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .elseif CHIPSET = 7
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 8
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .endif ; CHIPSET = 4, 7 or 8
  .elseif BOARD = 9

CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
CS4_MEM_REG   .short  0xe85  ; default reset value
    .if CHIPSET = 4
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
    .elseif CHIPSET = 7
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 8
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .endif ; CHIPSET = 4, 7 or 8
    
  .elseif BOARD = 35

CS0_MEM_REG   .short  0x7C0   ; 7 WS, 32 bits, write enabled
CS1_MEM_REG   .short  0x7C0   ; 7 WS, 32 bits, write enabled
CS2_MEM_REG   .short  0x7C0   ; 7 WS, 32 bits, write enabled
CS6_MEM_REG   .short  0x7C0   ; 7 WS, 32 bits, write enabled
CS7_MEM_REG   .short  0x7C0   ; 7 WS, 32 bits, write enabled

API_ADAPT     .equ    0x6A
CS7_SIZE      .equ    0x2000      ; 8 kB
CS7_ADDR      .equ    0x03800000  ; Initial address before toggling nIBOOT
SRAM_ADDR     .equ    0x00800000  ; Internal SRAM start address
SRAM_SIZE     .equ    0x00050000  ; 2.5 MBits
armio_in       .word  0xFFFE4800  ; ARMIO_IN  register address
armio_out      .word  0xFFFE4802  ; ARMIO_OUT register address
addrExtraConf  .word  0xFFFFFB10  ; Extra configuration
addrCS7        .word  0xFFFFFB08  ; CS7 configuration
DEF_EXTRA_CONF .short 0x033E      ; Default configuration
EXTRA_CONF     .short 0x013E      ; Boot configuration

  .elseif BOARD = 40

CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
CS4_MEM_REG   .short  0xe85  ; default reset value

    .if CHIPSET = 8
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 10
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 11
CS6_MEM_REG   .short  0x0c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .endif ; CHIPSET = 8, 10 or 11

  .elseif BOARD = 41

; FreeCalypso change, please see MEMIF-wait-states document
; in the freecalypso-docs repository for the explanation.

    .if VCXO_26MHZ = 1
CS0_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
CS1_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
CS2_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
    .else
CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
    .endif

CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
CS4_MEM_REG   .short  0xe85  ; default reset value

    .if CHIPSET = 8
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 10
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .elseif CHIPSET = 11
CS6_MEM_REG   .short  0x2c0  ; Internal RAM   init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG   .short  0x040  ; Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
    .endif ; CHIPSET = 8, 10 or 11

  .elseif BOARD = 43

    .if CHIPSET = 12
CS0_MEM_REG  .short  0x2A0	;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM   init : 1 WS, 16 bits, little
CS4_MEM_REG  .short  0x2A1	;RAM   init : 1 WS, 16 bits, little
CS5_MEM_REG  .short  0x2A0	;ROM   init : 0 WS, 16 bits, little
    .endif ; CHIPSET = 12

  .elseif BOARD = 45

    .if CHIPSET = 12
CS0_MEM_REG  .short  0x2A1	;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM   init : 1 WS, 16 bits, little
CS4_MEM_REG  .short  0x2A1	;RAM   init : 1 WS, 16 bits, little
CS5_MEM_REG  .short  0x2A1	;      init : 0 WS, 16 bits, little
    .endif ; CHIPSET = 12

  .endif ; BOARD

CLKM_MEM_REG  .equ  0x31	;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
CTL_MEM_REG   .short  0x02a   ; rhea strobe 0/1 + API access size adaptation