FreeCalypso > hg > fc-magnetite
view src/cs/drivers/drv_app/lcc/lcc_modulate.c @ 600:8f50b202e81f
board preprocessor conditionals: prep for more FC hw in the future
This change eliminates the CONFIG_TARGET_FCDEV3B preprocessor symbol and
all preprocessor conditionals throughout the code base that tested for it,
replacing them with CONFIG_TARGET_FCFAM or CONFIG_TARGET_FCMODEM. These
new symbols are specified as follows:
CONFIG_TARGET_FCFAM is intended to cover all hardware designs created by
Mother Mychaela under the FreeCalypso trademark. This family will include
modem products (repackagings of the FCDEV3B, possibly with RFFE or even
RF transceiver changes), and also my desired FreeCalypso handset product.
CONFIG_TARGET_FCMODEM is intended to cover all FreeCalypso modem products
(which will be firmware-compatible with the FCDEV3B if they use TI Rita
transceiver, or will require a different fw build if we switch to one of
Silabs Aero transceivers), but not the handset product. Right now this
CONFIG_TARGET_FCMODEM preprocessor symbol is used to conditionalize
everything dealing with MCSI.
At the present moment the future of FC hardware evolution is still unknown:
it is not known whether we will ever have any beyond-FCDEV3B hardware at all
(contingent on uncertain funding), and if we do produce further FC hardware
designs, it is not known whether they will retain the same FIC modem core
(triband), if we are going to have a quadband design that still retains the
classic Rita transceiver, or if we are going to switch to Silabs Aero II
or some other transceiver. If we produce a quadband modem that still uses
Rita, it will run exactly the same fw as the FCDEV3B thanks to the way we
define TSPACT signals for the RF_FAM=12 && CONFIG_TARGET_FCFAM combination,
and the current fcdev3b build target will be renamed to fcmodem. OTOH, if
that putative quadband modem will be Aero-based, then it will require a
different fw build target, the fcdev3b target will stay as it is, and the
two targets will both define CONFIG_TARGET_FCFAM and CONFIG_TARGET_FCMODEM,
but will have different RF_FAM numbers. But no matter which way we are
going to evolve, it is not right to have conditionals on CONFIG_TARGET_FCDEV3B
in places like ACI, and the present change clears the way for future
evolution.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 01 Apr 2019 01:05:24 +0000 |
| parents | 945cf7f506b2 |
| children |
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/****************************************************************************** * Power Task (pwr) * Design and coding by Svend Kristian Lindholm, skl@ti.com * * PWR SW Modulation * * $Id: pwr_modulate.c 1.1 Wed, 20 Aug 2003 10:22:37 +0200 skl $ * ******************************************************************************/ #include <string.h> #include "lcc/lcc.h" #include "lcc/lcc_trace.h" #include "lcc/lcc_modulate.h" #include "lcc/lcc_cfg_i.h" #include "lcc/lcc_cfg.h" #include "rv/rv_defined_swe.h" #include "abb/abb.h" /****************************************************************************** * Function prototypes ******************************************************************************/ void pwr_modulate_init(void); void pwr_modulate_on(void); void pwr_modulate_off(void); #if (USE_Q401_CHG_CIRCUIT == 1) extern T_PWR_CFG_BLOCK *pwr_cfg; #endif void pwr_modulate_init(void) { ttw(ttr(TTrEventLow,"pwr_modulate_init(%d)" NL, 0)); #if (USE_PWL_AS_MODULATOR == 1) BUZZ_LIGHT_REG |= 0x02; PWL_LEVEL_REG = 0xFF; // Full envelope function PWL_CTRL_REG = 0x00; // No 32KHz clock #else // Set GPIO 6 HIGH *((volatile uint16 *) 0xfffe4806) |= 0x0020; // Enable GPIO module *((volatile uint16 *) 0xfffe4804) &= 0xffbf; // Set GPIO-6 = output *((volatile uint16 *) 0xfffe4802) |= 0x0080; // Set GPIO-6 = HIGH #endif ttw(ttr(TTrEventLow,"pwr_modulate_init(%d)" NL, 0xff)); } void pwr_modulate_on(void) { ttw(ttr(TTrEventLow,"pwr_modulate_on(%d)" NL, 0)); #if (USE_Q401_CHG_CIRCUIT== 1) /* Program the DAC with the constant current value taken from /pwr/chg/chg<N>.cfg multiplied by k/255, where current k is in [1..255] */ ABB_Write_Register_on_page(PAGE0, CHGREG, (pwr_cfg->data.k * pwr_cfg->chg.ichg_max) / 255); #endif #if (USE_Q402_CHG_CIRCUIT == 1) #if (USE_PWL_AS_MODULATOR == 1) BUZZ_LIGHT_REG |= 0x02; PWL_LEVEL_REG = 0xFF; // Full envelope function PWL_CTRL_REG = 0x00; // No 32KHz clock #else // Use GPIO 6 *((volatile uint16 *) 0xfffe4806) |= 0x0020; // Enable GPIO module *((volatile uint16 *) 0xfffe4804) &= 0xffbf; // Set GPIO-6 = output *((volatile uint16 *) 0xfffe4802) |= 0x0080; // Set GPIO-6 = HIGH #endif #endif ttw(ttr(TTrEventLow,"pwr_modulate_on(%d)" NL, 0xFF)); } void pwr_modulate_off(void) { ttw(ttr(TTrEventLow,"pwr_modulate_off(%d)" NL, 0)); #if (USE_Q401_CHG_CIRCUIT == 1) // Don't do anything - FET is fully controlled in pwr_modulate_on() #endif #if (USE_Q402_CHG_CIRCUIT == 1) #ifdef USE_PWL_AS_MODULATOR BUZZ_LIGHT_REG &= 0xfd; PWL_LEVEL_REG = 0x00; // No envelope function PWL_CTRL_REG = 0x00; // No 32KHz clock #else // Use GPIO 6 *((volatile uint16 *) 0xfffe4806) |= 0x0020; // Enable GPIO module *((volatile uint16 *) 0xfffe4804) &= 0xffbf; // Set GPIO-6 = output *((volatile uint16 *) 0xfffe4802) &= 0x007f; // Set GPIO-6 = LOW #endif #endif ttw(ttr(TTrEventLow,"pwr_modulate_off(%d)" NL, 0xFF)); }
