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−Our current FCDEV3B boards exhibit a hardware bug: the reset input to the flash
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−chip is connected to Calypso's FDP output per both TI's Leonardo reference
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−schematics and Openmoko's working design, but this arrangement turns out to be
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−unsuitable for the high-capacity Spansion S71PL129NC0HFW4B flash+pSRAM chip we
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−are using, copied from Pirelli DP-L10.  This hardware bug has manifested itself
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−in two different ways so far:
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−
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−* Out of the 20 boards we've built so far, on just one board there was an issue
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−  where our standard Magnetite fw would have trouble booting from flash, but
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−  RAM-loaded fw booted fine.  Interrupting the boot process serially and having
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−  the serially loaded code jump to the image in flash also worked fine.
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−  Eventually it was found that the flash boot problem on that one board occurs
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−  only when flash boot mode 1 is used, whereas flash boot mode 0 works fine.  I
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−  (Mychaela) suspect that the problem has something to do with the watchdog
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−  reset that happens as part of flash boot mode 1, the FDP output behaviour
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−  during that watchdog reset, and the flash chip's reaction to the latter.
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−
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−* On all of the boards there is a problem with sleep modes: when the firmware
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−  is running from flash as opposed to RAM, certain sleep-wake sequences cause
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−  an erratic self-reboot or a hang.  It is suspected (though not proven yet)
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−  that the FDP output goes low during all sleep modes, our Spansion flash chip
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−  gets unhappy with the reset timing it gets subjected to, and some flash reads
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−  (instruction fetches) don't work after wakeup.  So far the only workable
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−  solution has been to disable all sleep modes in all FCDEV3B fw builds;
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−  nothing else has been successful.
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−
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−The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B
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−firmware images (fwimage.bin builds) as xxd binary patches:
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−
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−* The first hack dating from 2017-05 patches the fw to use flash boot mode 0
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−  instead of TI's original flash boot mode 1, but after boot the FFFF:FB10
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−  register is set to put the flash and not the internal ROM at address 0, so
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−  the interrupt and exception vectors go to the flash like in TI's original fw,
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−  not through the internal ROM.  This hack was put together for the purpose of
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−  producing flashable fw images that boot without problems on that one board on
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−  which flash boot mode 1 didn't work, and worked successfully for that purpose.
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−
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−* The second hack dating from 2018-03 patches the fw to not only use flash boot
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−  mode 0, but also route the interrupt and exception vectors through Calypso's
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−  internal ROM.  I was hoping that this hack would make the sleep mode problem
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−  go away by having the Calypso execute some cycles out of its internal ROM and
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−  RAM before hitting the flash after wakeup, but nope, bringing up the SIM
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−  interface with AT+CFUN=1 in the l1reconst config when running from flash with
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−  small sleep enabled still triggers erratic misbehaviour even with this patch.
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−
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−The proper fix will be to change the PCB to not connect the flash chip's reset
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−input to FDP any more, and connect it to a pull-up resistor instead.  But this
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−fix will require an expensive PCB respin, hence some experiments to test this
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−idea will need to be done first.