view cdg-hybrid/cdginc/ccdent.cdg @ 604:a7ed7d4483b0

main assembly boot path code: MEMIF change for 26 MHz targets as explained in the MEMIF-wait-states document
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 02:11:17 +0000
parents e7a67accfad9
children
line wrap: on
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/*
+--------------------------------------------------------------------------+
| PROJECT : PROTOCOL STACK                                                 |
| FILE    : ccdent.cdg                                                     |
| SOURCE  : "msg\rr_com.mdf"                                               |
| LastModified : "2004-01-16"                                              |
| IdAndVersion : "8010.606.02.008"                                         |
| SrcFileTime  : "Wed Nov 28 10:20:42 2007"                                |
| Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016                   |
|           !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!!                |
+--------------------------------------------------------------------------+
*/


#ifndef CCDENT_CDG
#define CCDENT_CDG


/*    0*/ { "RR_COM"      , CCDENT_RR_COM        },
/*    1*/ { "RR"          , CCDENT_RR            },
/*    2*/ { "RR_SHORT"    , CCDENT_RR_SHORT      },
/*    3*/ { "MM"          , CCDENT_MM            },
/*    4*/ { "CC"          , CCDENT_CC            },
/*    5*/ { "SS"          , CCDENT_SS            },
/*    6*/ { "SMS"         , CCDENT_SMS           },
/*    7*/ { "FAC"         , CCDENT_FAC           },
/*    8*/ { "SAT"         , CCDENT_SAT           },
/*    9*/ { "T30"         , CCDENT_T30           },
/*   10*/ { "GMM"         , CCDENT_GMM           },
/*   11*/ { "TST"         , CCDENT_TST           },
/*   12*/ { "GRLC"        , CCDENT_GRLC          },
/*   13*/ { "GRR"         , CCDENT_GRR           },
/*   14*/ { "SM"          , CCDENT_SM            },
/*65535*/ { (char *) NULL , 65535 },

#endif