niq32.c DTR handling restored for targets that have it TI's original TCS211 fw treated GPIO 3 as the DTR input (wired so on C-Sample and D-Sample boards, also compatible with Leonardo and FCDEV3B which have a fixed pull-down resistor on this GPIO line), and the code in niq32.c called UAF_DTRInterruptHandler() (implemented in uartfax.c) from the IQ_KeypadGPIOHandler() function. But on Openmoko's GTA02 with their official fw this GPIO is a floating input, all of the DTR handling code in uartfax.c including the interrupt logic is still there, but the hobbled TCS211-20070608 semi-src delivery which OM got from TI contained a change in niq32.c (which had been kept in FC until now) that removed the call to UAF_DTRInterruptHandler() as part of those not-quite-understood "CC test" hacks. The present change fixes this bug at a long last: if we are building fw for a target that has TI's "classic" DTR & DCD GPIO arrangement (dsample, fcmodem and gtm900), we bring back all of TI's original code in both uartfax.c and niq32.c, whereas if we are building fw for a target that does not use this classic GPIO arrangement, the code in niq32.c goes back to what we got from OM and all DTR & DCD code in uartfax.c is conditioned out. This change also removes the very last remaining bit of "CC test" bogosity from our FreeCalypso code base.

[board.cfg]

BOARD 41
DSAMPLE_FULL_COLOR var

[chipset.cfg]

ANLG_FAM 2
ANLG_PG 0
CHIPSET var

[debug.cfg]

TI_NUC_MONITOR 0
TI_PROFILER 0

[dio.cfg]

DIOIL_CONFIG 0

[ffs.cfg]

TARGET 1
_RVF 1

[l1sw.cfg]

AMR var
CUST 0
DCO_ALGO 0
IDS var
L1_12NEIGH 1
L1_EOTD 0
L1_EOTD_QBIT_ACC 0
L1_GPRS var
L1_GTT 0
L1_MIDI 0
L1_VOICE_MEMO_AMR var
MELODY_E2 var
OP_L1_STANDALONE 0
OP_RIV_AUDIO 1
ORDER2_TX_TEMP_CAL 1
RAZ_VULSWITCH_REGAUDIO 0
SECURITY 0
SPEECH_RECO var
TESTMODE 1
TRACE_TYPE 4
VCXO_ALGO 1

[r2d.cfg]

R2D_ASM 0
R2D_LCD_TEST 0

[rf.cfg]

RF var
RF_FAM var
RF_PA var
RF_PG var

[rv.cfg]

RVTOOL 0
TEST 0
_GSM 1

[swconfig.cfg]

ALR 1
BT 0
DP 0
DWNLD 1
GSMLITE 0
L1_DYN_DSP_DWNLD var
LONG_JUMP 3
MOVE_IN_INTERNAL_RAM 1
OP_WCP 0
PMODE var
RVDATA_INTERNALRAM 0
SRVC var
TR_BAUD_CONFIG var
WCP_PROF 0

[sys.cfg]

DSP var
STD 6

[trace.cfg]

LAYER_DBG 0xFFFFFFFF
TRACE_LEVEL_FILTER 5