FreeCalypso > hg > fc-magnetite
view src/cs/system/main/init.c @ 632:d968a3216ba0
new tangomdm build target
TCS211/Magnetite built for target leonardo runs just fine on the Tango-based
Caramel board, but a more proper tangomdm build target is preferable in order
to better market these Tango modems to prospective commercial customers. The
only differences are in GPIO and MCSI config:
* MCSI is enabled in the tangomdm build config.
* GPIO 1 is loudspeaker amplifier control on Leonardo, but on Tango platforms
it can be used for anything. On Caramel boards this GPIO should be
configured as an output driving high.
* GPIO 2 needs to be configured as Calypso input on Leonardo, but on Tango
platforms it can be used for anything. On Caramel boards this GPIO should be
configured as an output, either high or low is OK.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 04 Jan 2020 19:27:41 +0000 |
| parents | 238b67a785f2 |
| children | 37396b85f3f7 |
line wrap: on
line source
/* * INIT.C * * This module allows to initialize the board: * - wait states, * - unmask selected interrupts, * - initialize clock, * - disable watchdog. * Dummy functions used by the EVA3 library are defined. */ /* Config Files */ #ifndef _WINDOWS #include "l1sw.cfg" #include "rf.cfg" #include "chipset.cfg" #include "board.cfg" #include "swconfig.cfg" #include "fc-target.h" #if (OP_L1_STANDALONE == 0) #include "rv.cfg" #include "sys.cfg" #include "debug.cfg" #ifdef BLUETOOTH_INCLUDED #include "btemobile.cfg" #endif #ifdef BLUETOOTH #include "bluetooth.cfg" #endif #endif #if (OP_L1_STANDALONE == 0) #include "rv/rv_defined_swe.h" #endif #endif /* Include Files */ #include <assert.h> #include <ctype.h> #include <stdarg.h> #include <stdlib.h> #include <string.h> #include "nucleus.h" #include "sys_types.h" #include "l1_types.h" #include "l1_confg.h" #include "l1_const.h" #if TESTMODE #include "l1tm_defty.h" #endif // TESTMODE #if (AUDIO_TASK == 1) #include "l1audio_const.h" #include "l1audio_cust.h" #include "l1audio_defty.h" #endif // AUDIO_TASK #if (L1_GTT == 1) #include "l1gtt_const.h" #include "l1gtt_defty.h" #endif #if (L1_MP3 == 1) #include "l1mp3_defty.h" #endif #if (L1_MIDI == 1) #include "l1midi_defty.h" #endif #if (L1_AAC == 1) #include "l1aac_defty.h" #endif #if (L1_DYN_DSP_DWNLD == 1) #include "l1_dyn_dwl_defty.h" #endif #if (TRACE_TYPE == 4) #include "l1_defty.h" #endif #if ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE == 0)) #if (AUDIO_TASK == 1) #include "l1audio_signa.h" #include "l1audio_msgty.h" #endif // AUDIO_TASK #if (L1_GTT == 1) #include "l1gtt_signa.h" #include "l1gtt_msgty.h" #endif #include "l1_defty.h" #include "cust_os.h" #include "l1_msgty.h" #include "nu_main.h" #include "l1_varex.h" #include "l1_proto.h" #include "hw_debug.h" #include "l1_trace.h" #endif /* ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE==0)) */ #include "armio/armio.h" #include "timer/timer.h" #if (OP_L1_STANDALONE == 0) #include "rvf/rvf_api.h" #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */ #include "sim/sim.h" #endif #include "abb/abb.h" #include "inth/iq.h" #include "tpudrv.h" #include "memif/mem.h" #include "clkm/clkm.h" #include "inth/inth.h" #if (OP_L1_STANDALONE == 1) #include "uart/serialswitch_core.h" #else #include "uart/serialswitch.h" #endif #include "uart/traceswitch.h" #include "dma/dma.h" #include "rhea/rhea_arm.h" #include "ulpd/ulpd.h" #if (PSP_STANDALONE == 0) #if (OP_L1_STANDALONE == 0) extern void ffs_main_init(void); extern void create_tasks(void); #if TI_NUC_MONITOR == 1 extern void ti_nuc_monitor_tdma_action( void ); #endif #if WCP_PROF == 1 #if PRF_CALIBRATION == 1 extern NU_HISR prf_CalibrationHISR; #endif #endif #else void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz); extern void L1_trace_string(char *s); #endif /* (OP_L1_STANDALONE) */ #endif #if (OP_L1_STANDALONE == 1) #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) || TESTMODE) #include "uart/uart.h" /* * Serial Configuration set up. */ extern char ser_cfg_info[NUMBER_OF_TR_UART]; #include "rvt_gen.h" extern T_RVT_USER_ID trace_id; #endif #endif /* (OP_L1_STANDALONE == 1) */ /* * Serial Configuration set up. */ /* ** One config is: ** {XXX_BT_HCI, // Bluetooth HCI ** XXX_FAX_DATA, // Fax/Data AT-Cmd ** XXX_TRACE, // L1/Riviera Trace Mux ** XXX_TRACE}, // Trace PS ** ** with XXX being DUMMY, UART_IRDA or UART_MODEM */ #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) ||\ (TESTMODE)) && (OP_L1_STANDALONE == 1)) || (OP_L1_STANDALONE == 0)) #if (OP_L1_STANDALONE == 1) static T_AppliSerialInfo appli_ser_cfg_info = #else T_AppliSerialInfo appli_ser_cfg_info = #endif /* OP_L1_STANDALONE */ { #ifdef CONFIG_RVTMUX_ON_MODEM {DUMMY_BT_HCI, DUMMY_FAX_DATA, UART_MODEM_TRACE, DUMMY_TRACE}, // 0x0248 #else // RVTMUX_ON_MODEM {DUMMY_BT_HCI, UART_MODEM_FAX_DATA, UART_IRDA_TRACE, DUMMY_TRACE}, // default config = 0x0168 #endif #ifdef BTEMOBILE 12, // 12 serial config allowed #else // BTEMOBILE 9, // 9 serial config allowed #endif { // Configs with Condat Panel only {DUMMY_BT_HCI, DUMMY_FAX_DATA, DUMMY_TRACE, UART_IRDA_TRACE}, // 0x1048 {DUMMY_BT_HCI, DUMMY_FAX_DATA, DUMMY_TRACE, UART_MODEM_TRACE}, // 0x2048 // Configs with L1/Riviera Trace only {DUMMY_BT_HCI, DUMMY_FAX_DATA, UART_IRDA_TRACE, DUMMY_TRACE}, // 0x0148 {DUMMY_BT_HCI, DUMMY_FAX_DATA, UART_MODEM_TRACE, DUMMY_TRACE}, // 0x0248 // Configs with AT-Cmd only {DUMMY_BT_HCI, UART_MODEM_FAX_DATA, DUMMY_TRACE, DUMMY_TRACE}, // 0x0068 // Configs with Condat Panel and L1/Riviera Trace {DUMMY_BT_HCI, DUMMY_FAX_DATA, UART_MODEM_TRACE, UART_IRDA_TRACE}, // 0x1248 {DUMMY_BT_HCI, DUMMY_FAX_DATA, UART_IRDA_TRACE, UART_MODEM_TRACE}, // 0x2148 // Configs with Condat Panel and AT-Cmd {DUMMY_BT_HCI, UART_MODEM_FAX_DATA, DUMMY_TRACE, UART_IRDA_TRACE}, // 0x1068 #ifdef BTEMOBILE // Configs with L1/Riviera Trace and Bluetooth HCI {UART_IRDA_BT_HCI, DUMMY_FAX_DATA, UART_MODEM_TRACE, DUMMY_TRACE}, // 0x0249 {UART_MODEM_BT_HCI, DUMMY_FAX_DATA, UART_IRDA_TRACE, DUMMY_TRACE}, // 0x014A // Configs with AT-Cmd and Bluetooth HCI {UART_IRDA_BT_HCI, UART_MODEM_FAX_DATA, DUMMY_TRACE, DUMMY_TRACE}, // 0x0069 #endif // BTEMOBILE // Configs with L1/Riviera Trace and AT-Cmd {DUMMY_BT_HCI, UART_MODEM_FAX_DATA, UART_IRDA_TRACE, DUMMY_TRACE} // 0x0168 } }; #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */ /* * Init_Target * * Performs low-level HW Initialization. */ void Init_Target(void) { #if (BOARD == 5) #define WS_ROM (1) #define WS_RAM (1) #define WS_APIF (1) #define WS_CS2 (7) /* LCD on EVA3. */ #define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */ #define WS_CS1 (7) /* LCD on A-Sample. */ IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1); IQ_InitClock (2); /* Internal clock division factor. */ IQ_MaskAll (); /* Mask all interrupts. */ IQ_SetupInterrupts (); /* IRQ priorities. */ TM_DisableWatchdog (); /* * Reset all TSP and DBG fdefault values */ AI_ResetTspIO (); AI_ResetDbgReg (); AI_ResetIoConfig (); /* * Warning! The external reset signal is connected to the Omega and the * external device. If the layer 1 is used its initialization removes * the external reset. If the application does not use the layer 1 * you must remove the external reset (bit 2 of the reset control * register 0x505808). */ AI_ResetTspIO(); AI_ResetDbgReg(); AI_ResetIoConfig(); /* * Configure all IOs (see RD300 specification). */ AI_ConfigBitAsInput (1); AI_EnableBit (1); AI_ConfigBitAsOutput (2); AI_EnableBit (2); AI_ConfigBitAsInput (11); AI_EnableBit (11); AI_ConfigBitAsOutput (13); AI_EnableBit (13); AI_Power (1); /* Maintain power supply. */ #elif (BOARD == 6) || (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || \ (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) || \ (BOARD == 35) || (BOARD == 46) || (BOARD == 70) || (BOARD == 71) #if (PSP_STANDALONE == 0) // RIF/SPI rising edge clock for ULYSSE //-------------------------------------------------- #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)|| (ANLG_FAM == 11)) #if ((CHIPSET >= 3)) #if (CHIPSET == 12) F_CONF_RIF_RX_RISING_EDGE; F_CONF_SPI_RX_RISING_EDGE; #elif (CHIPSET == 15) //do the DRP init here for Locosto #if (L1_DRP == 1) // drp_power_on(); This should be done after the script is downloaded. #endif #else #if (BOARD==35) *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000; #elif defined(CONFIG_TARGET_PIRELLI) /* * Pirelli's version of this Init_Target() function * in their fw sets the ASIC_CONF register to 0x6050, * which means PWL on the LT/PWL pin and LPG on the * DSR_MODEM pin. */ *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050; #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900) /* * The DSR_MODEM/LPG Calypso signal is unconnected on * Openmoko's modem, so let's mux it as LPG (output) * so it doesn't float, like Foxconn seem to have done * on the Pirelli. * * On the GTM900 module this signal is explicitly defined as LPG. */ *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040; #else *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000; #endif /* (BOARD == 35) */ #endif #endif #endif /* ANLG(ANALOG)) */ #if (OP_L1_STANDALONE == 1) #if (BOARD == 40) || (BOARD == 41) || \ (BOARD == 42) || (BOARD == 43) || (BOARD == 45) // enable 8 Ohm amplifier for audio on D-sample AI_ConfigBitAsOutput (1); AI_SetBit(1); #elif (BOARD == 70) || (BOARD == 71) //Locosto I-sample or UPP costo board.BOARD // Initialize the ARMIO bits as per the I-sample spec // FIXME #endif #endif /* (OP_L1_STANDALONE == 1) */ #endif /* PSP_STANDALONE ==0 */ // Watchdog //-------------------------------------------------- TM_DisableWatchdog(); /* Disable Watchdog */ #if (CHIPSET == 12) || (CHIPSET == 15) TM_SEC_DisableWatchdog(); #endif #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) #if (CHIPSET == 12) #if 0 /* example of configuration for DMA debug */ #if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */ /* TPU_FRAME, NMIIT, IACKn */ F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4|C_DBG_IRQ_NMIIT|C_DBG_IRQ_IACKN); /* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/ F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 | C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 | C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 ); /* DMA_REQ_S(2)*/ F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2); /* DMA_CLK_REQ, BRIDGE_CLK */ F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ | C_DBG_CLK1_BRIDGE_CLK ); /* XIO_nREADY */ F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM); /* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */ F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 | C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 | C_DBG_KB_USIM_SHD_BRIDGE_EN ); /* RHEA_nREADY , RHEA_nSTROBE */ F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE | C_DBG_USIM_RHEA_NREADY ); /* XIO_STROBE */ F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN); /* DMA_CLK_REQ */ F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2); /* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */ F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA, C_DBG_DSP_INT_DMA, C_DMA_CHANNEL_RIF_RX, C_DMA_CHANNEL_RIF_RX); #endif /* (BOARD == 6) */ #endif /* DMA debug example */ #else /* * Configure ASIC in order to output the DPLL and ARM clock */ // (*( volatile UWORD16* )(0xFFFEF008)) = 0x8000; // DPLL // (*( volatile UWORD16* )(0xFFFEF00E)) = 0x0004; // ARM clock // (*( volatile UWORD16* )(0xfffef004)) = 0x0600; // DSP clock + nIACK #endif /* (CHIPSET == 12) || CHIPSET == 15*/ /* * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules */ // IRQ, Timer and bridge may SLEEP // In first step, same configuration as SAMSON //-------------------------------------------------- #if (CHIPSET == 12) CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS); #elif (CHIPSET == 15) CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/ #else CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS); // Select VTCXO input frequency //-------------------------------------------------- CLKM_UNUSED_VTCXO_26MHZ; // Rita RF uses 26MHz VCXO #if (RF_FAM == 12) CLKM_USE_VTCXO_26MHZ; #endif // Renesas RF uses 26MHz on F-sample but 13MHz on TEB #if (RF_FAM == 43) && (BOARD == 46) CLKM_USE_VTCXO_26MHZ; #endif #endif // Control HOM/SAM automatic switching //-------------------------------------------------- *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG; /* * The following part has been reconstructed from disassembly. */ RHEA_INITRHEA(0,0,0xFF); DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); #if (CHIPSET == 8) DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6); #elif (CHIPSET == 10) || (CHIPSET == 11) DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); #else #error "We only have DPLL setup for CHIPSETs 8 and 10" #endif CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ /* * FreeCalypso change: memory timings and widths are target-dependent; * please refer to the MEMIF-wait-states document in the freecalypso-docs * repository for the full explanation. */ #ifdef CONFIG_TARGET_PIRELLI /* * Pirelli's version of this Init_Target() function * in their fw does the following: */ MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); #elif defined(CONFIG_TARGET_C155) /* * C155/156 official fw MEMIF config is almost the same as Pirelli's, * only nCS4 WS is different, but nCS4 is unused on this model... */ MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0); #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \ defined(CONFIG_TARGET_GTAMODEM) /* * The original settings from Openmoko, * only nCS0 and nCS1 are actually used, * same as on Mot C1xx phones, * the nCS2/3/4 settings are dummies from TI. */ MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); #elif defined(CONFIG_TARGET_J100) /* * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS: * it appears that SE J100 has its ringtone melody generator chip * hooked up there. */ MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); #elif (CHIPSET == 8) /* * Our only Calypso C05 target is Mother Mychaela's D-Sample board. * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns, * so we should be good on this board. */ MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); #elif (CHIPSET == 10) || (CHIPSET == 11) /* * Default for Calypso C035 targets in the absence of a more specific * selection above. We put the WS=4 memory-oriented setting on all * chip selects so we automatically cover targets with a second flash * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even * weirder targets with XRAM somewhere other than nCS1. */ MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); #else #error "Unknown MEMIF configuration" #endif MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0); MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0); RHEA_INITAPI(0,1); RHEA_INITARM(0,0); DPLL_SET_PLL_ENABLE; /* * Disable and Clear all pending interrupts */ #if (CHIPSET == 12) || (CHIPSET == 15) F_INTH_DISABLE_ALL_IT; // MASK all it F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source #else INTH_DISABLEALLIT; #if 0 /* not present in our reference binary object */ INTH_RESETALLIT; #endif INTH_CLEAR; /* reset IRQ/FIQ source */ #endif // INTH //-------------------------------------------------- #if (CHIPSET == 12) || (CHIPSET == 15) #if (GSM_IDLE_RAM != 0) f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers #else f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers #endif #else IQ_SetupInterrupts(); #endif #if (CHIPSET == 12) || (CHIPSET == 15) #if (OP_L1_STANDALONE == 0) f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter); #endif f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP); #if (OP_L1_STANDALONE == 1) f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter); f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP); #endif #else // DMA //-------------------------------------------------- // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same #if (OP_L1_STANDALONE == 0) DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX #endif #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */ #else // RHEA Bridge //-------------------------------------------------- // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F RHEA_INITRHEA(0,0,0x7F); #if (CHIPSET == 6) // WS_H = 1 , WS_L = 15 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz #else // WS_H = 0 , WS_L = 7 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz #endif // Write_en_0 = 0 , Write_en_1 = 0 RHEA_INITARM(0,0); // INTH //-------------------------------------------------- INTH_DISABLEALLIT; // MASK all it INTH_CLEAR; // reset IRQ/FIQ source IQ_SetupInterrupts(); // DMA //-------------------------------------------------- // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead) #if (CHIPSET == 6) // Memory WS configuration for ULYSS/G1 (26 Mhz) board //----------------------------------------------------- MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0); #endif // CLKM //-------------------------------------------------- CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */ #if (CHIPSET == 6) CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26); #else CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS); #endif #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */ // Freeze ULPD timer .... //-------------------------------------------------- *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0; *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE; // reset INC_SIXTEEN and INC_FRAC //-------------------------------------------------- #if (OP_L1_STANDALONE == 1) l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE); #else ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133 // 26000 --> 166 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845 // 26000 --> 43691 #endif /* OP_L1_STANDALONE */ // program ULPD WAKE-UP .... //================================================= #if (CHIPSET == 2) *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods #else *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods #endif // Set Gauging versus HF (PLL) //================================================= ULDP_GAUGING_SET_HF; // Enable gauging versus HF ULDP_GAUGING_HF_PLL; // Gauging versus PLL // current supply for quartz oscillation //================================================= #if (OP_L1_STANDALONE == 1) #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27; #endif #else #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41)) *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27; #elif (BOARD == 7) *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24; #endif #endif /* OP_L1_STANDALONE */ // stop Gauging if any (debug purpose ...) //-------------------------------------------------- if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN) { volatile UWORD32 j; ULDP_GAUGING_STOP; /* Stop the gauging */ /* wait for gauging it*/ // one 32khz period = 401 periods of 13Mhz for (j=1; j<50; j++); while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING); } #if (OP_L1_STANDALONE == 0) AI_ClockEnable (); #if (BOARD == 7) // IOs configuration of the B-Sample in order to optimize the power consumption AI_InitIOConfig(); // Set LPG instead of DSR_MODEM *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40; // Reset the PERM_ON bit of LCR_REG *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80); #elif ((BOARD == 8) || (BOARD == 9)) // IOs configuration of the C-Sample in order to optimize the power consumption AI_InitIOConfig(); // set the debug latch to 0x00. *((volatile SYS_UWORD8 *) 0x2800000) = 0x00; #elif ((BOARD == 35) || (BOARD == 46)) AI_InitIOConfig(); // CSMI INTERFACE // Initialize CSMI clients for GSM control // and Fax/Data services CSMI_Init(); GC_Initialize(); // GSM control initialization CU_Initialize(); // Trace initialization CF_Initialize(); // Fax/Data pre-initialization #elif ((BOARD == 40) || (BOARD == 41)) // IOs configuration of the D-Sample in order to optimize the power consumption AI_InitIOConfig(); #ifdef BTEMOBILE // Reset BT chip by toggling the Island's nRESET_OUT signal *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04; *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4); #endif // set the debug latch to 0x0000. /* * FreeCalypso change: this write is only correct when running * on an actual D-Sample board, but not on any of the real-world * Calypso target devices. */ #ifdef CONFIG_TARGET_DSAMPLE *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; #endif #endif // BOARD // Enable HW Timers 1 & 2 TM_EnableTimer (1); TM_EnableTimer (2); #endif /* (OP_L1_STANDALONE == 0) */ #endif /* #if (BOARD == 5) */ } /* * Init_Drivers * * Performs Drivers Initialization. */ void Set_Switch_ON_Cause(void); void Init_Drivers(void) { #if (CHIPSET==15) bspI2c_init(); bspTwl3029_init(); #if (OP_L1_STANDALONE == 0) Set_Switch_ON_Cause(); #endif /* Turn on DRP We will make VRMCC to device group Modem * And Switch it on. */ bspTwl3029_Power_setDevGrp(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_DEV_GRP_MODEM); wait_ARM_cycles(convert_nanosec_to_cycles(100000*2)); bspTwl3029_Power_enable(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_STATE_ACTIVE); #endif #if (CHIPSET!=15) #if ABB_SEMAPHORE_PROTECTION // Create the ABB semaphore ABB_Sem_Create(); #endif // SEMAPHORE_PROTECTION #endif #if (OP_L1_STANDALONE == 0) /* * Initialize FFS invoking restore procedure by MPU-S */ #if ((BOARD == 35) || (BOARD == 46)) GC_FfsRestore(); #endif /* * FFS main initialization. */ ffs_main_init(); /* * Initialize Riviera manager and create tasks thanks to it. */ #if (CHIPSET!=15) || (REMU==0) rvf_init(); rvm_init(); /* A-M-E-M-D-E-D! */ create_tasks(); #endif /* * SIM Main Initialization. */ #if (CHIPSET!=15) SIM_Initialize (); #else bspUicc_bootInit(); #endif #endif } /* * Init_Serial_Flows * * Performs Serialswitch + related serial data flows initialization. */ void Init_Serial_Flows (void) { #if (OP_L1_STANDALONE == 0) /* * Initialize Serial Switch module. */ #if ((BOARD==35) || (BOARD == 46)) SER_InitSerialConfig (GC_GetSerialConfig()); #else SER_InitSerialConfig (&appli_ser_cfg_info); #endif /* * Then Initialize the Serial Data Flows and the associated UARTs: * - G2-3 Trace if GSM/GPRS Protocol Stack * - AT-Cmd/Fax & Data Flow * * Layer1/Riviera Trace Flow and Bluetooth HCI Flow are initialized * by the appropriate SW Entities. * * G2-3 Trace => No more Used */ SER_tr_Init(SER_PROTOCOL_STACK, TR_BAUD_38400, NULL); /* * Fax & Data / AT-Command Interpreter Serial Data Flow Initialization */ #if ((BOARD != 35) && (BOARD != 46)) (void) SER_fd_Initialize (); #endif #else /* OP_L1_STANDALONE */ #if (TESTMODE || (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==6) || (TRACE_TYPE==7)) #if ((BOARD == 35) || (BOARD == 46)) ser_cfg_info[UA_UART_0] = '0'; #else ser_cfg_info[UA_UART_0] = 'G'; #endif #if (CHIPSET !=15) ser_cfg_info[UA_UART_1] = 'R'; // Riviear Demux on UART MODEM #else ser_cfg_info[UA_UART_0] = 'R'; // Riviear Demux on UART MODEM #endif /* init Uart Modem */ SER_InitSerialConfig (&appli_ser_cfg_info); #if TESTMODE || (TRACE_TYPE == 1) || (TRACE_TYPE == 7) SER_tr_Init (SER_LAYER_1, TR_BAUD_115200, rvt_activate_RX_HISR); rvt_register_id("OTHER",&trace_id,(RVT_CALLBACK_FUNC)NULL); #else SER_tr_Init (SER_LAYER_1, TR_BAUD_38400, NULL); #endif L1_trace_string(" \n\r"); #endif /* TRACE_TYPE */ #endif /* OP_L1_STANDALONE */ } /* * Init_Unmask_IT * * Unmask all used interrupts. */ void Init_Unmask_IT (void) { IQ_Unmask(IQ_FRAME); IQ_Unmask(IQ_UART_IRDA_IT); IQ_Unmask(IQ_UART_IT); IQ_Unmask(IQ_ARMIO); #if (L1_DYN_DSP_DWNLD == 1) IQ_Unmask(IQ_API); #endif }