# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1520222490 0
# Node ID 395e464e4005ee0ca8afeaa59bcc84478e13cb1b
# Parent  3bf62c0a7f34e20a5c53f912d045eb38e372347d
Compal & Pirelli targets: APCOFF register setting
changed to match what the respective original firmwares set

diff -r 3bf62c0a7f34 -r 395e464e4005 src/cs/layer1/cust0/l1_rf12.h
--- a/src/cs/layer1/cust0/l1_rf12.h	Mon Jan 29 06:27:47 2018 +0000
+++ b/src/cs/layer1/cust0/l1_rf12.h	Mon Mar 05 04:01:30 2018 +0000
@@ -169,10 +169,12 @@
   #define  C_VBDCTRL        ((0x006 << 6) | VBDCTRL   | TRUE)   // Downlink gain amp 0dB, Volume control -12 dB
  // RITA does not need an APCOFFSET because the PACTRL is internal: 
   // REMOVE //#define  C_APCOFF          0x1016 | (0x3c << 6) | TRUE   // x2 slope 128 
-#if (RF_PA == 0 || RF_PA == 3) 
-  #define  C_APCOFF         ((0x040 << 6) | APCOFF    | TRUE) // x2 slope 128 
-#elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4) 
-  #define  C_APCOFF         ((0x070 << 6) | APCOFF    | TRUE) // x2 slope 128 
+#if (RF_PA == 0 || RF_PA == 3) || defined(CONFIG_TARGET_PIRELLI)
+  #define  C_APCOFF         ((0x040 << 6) | APCOFF    | TRUE) // x2 slope 128
+#elif defined(CONFIG_TARGET_COMPAL)
+  #define  C_APCOFF         ((0x060 << 6) | APCOFF    | TRUE) // x2 slope 128
+#elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
+  #define  C_APCOFF         ((0x070 << 6) | APCOFF    | TRUE) // x2 slope 128
 #endif
   #define  C_BULIOFF        ((0x0FF << 6) | BULIOFF   | TRUE)   // value at reset
   #define  C_BULQOFF        ((0x0FF << 6) | BULQOFF   | TRUE)   // value at reset