# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1516474595 0
# Node ID 706f4b71acebdb7a1689e64ca7af71b611388b62
# Parent  5ca341a26dda2de082b50c039900f512f3c5ce6e
more sensible MEMIF setup for D-Sample C05 target

diff -r 5ca341a26dda -r 706f4b71aceb src/cs/system/Main/init.c
--- a/src/cs/system/Main/init.c	Sat Jan 20 00:37:48 2018 +0000
+++ b/src/cs/system/Main/init.c	Sat Jan 20 18:56:35 2018 +0000
@@ -520,7 +520,7 @@
         MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
-      #elif defined(CONFIG_TARGET_FCFAM) || defined(CONFIG_TARGET_DSAMPLE)
+      #elif defined(CONFIG_TARGET_FCFAM)
         /*
          * The settings currently adopted for the FreeCalypso
          * hardware family, only nCS0, nCS1 and nCS2 are used
@@ -531,6 +531,18 @@
         MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+      #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8)
+        /*
+         * On D-Sample C05 (older Calypso silicon version) the clocks
+         * run slower: the ARM clock runs at 39 MHz instead of 52 MHz.
+         * Therefore, we need to use fewer wait states to effect
+         * the same memory speed.
+         */
+        MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
       #else
         /*
          * The original settings from Openmoko,