# HG changeset patch # User Mychaela Falconia # Date 1475427082 0 # Node ID 7bd197063b9e7f4296c1f8eba39b9ab8d4ca48a6 # Parent 6c3881378a315105a18b501e61609e713dc50271 building RAM fw images for the Pirelli: initial concept diff -r 6c3881378a31 -r 7bd197063b9e configure.sh --- a/configure.sh Sun Oct 02 14:17:39 2016 +0000 +++ b/configure.sh Sun Oct 02 16:51:22 2016 +0000 @@ -185,6 +185,13 @@ helpers/makeline def LINK_SCRIPT_SRC ../$LINK_SCRIPT_SRC >> $BUILD_DIR/Makefile echo >> $BUILD_DIR/Makefile +if [ -n "$RAM_LINK_SCRIPT_SRC" ] +then + helpers/makeline def RAM_LINK_SCRIPT_SRC ../$RAM_LINK_SCRIPT_SRC \ + >> $BUILD_DIR/Makefile + echo >> $BUILD_DIR/Makefile +fi + cat makefile-frags/first-part >> $BUILD_DIR/Makefile if [ "$USE_STR2IND" = 1 ] @@ -205,6 +212,11 @@ cat makefile-frags/m0-to-bin-c139 >> $BUILD_DIR/Makefile fi +if [ -n "$RAM_LINK_SCRIPT_SRC" ] +then + cat makefile-frags/ram-link-steps >> $BUILD_DIR/Makefile +fi + cat makefile-frags/clean-always >> $BUILD_DIR/Makefile if [ "$str2ind_blobs_used" = 0 ] then diff -r 6c3881378a31 -r 7bd197063b9e makefile-frags/ram-link-steps --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/makefile-frags/ram-link-steps Sun Oct 02 16:51:22 2016 +0000 @@ -0,0 +1,10 @@ +link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen + perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \ + ${SPECIAL_LINK_LIBS} + +ramimage.out: ${LIBS} str2ind.obj link_ram.cmd + ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^ + +ramimage.m0: ramimage.out + ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $< + diff -r 6c3881378a31 -r 7bd197063b9e src/cs/system/template/gsm_ds_pirelli_ram.template --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/cs/system/template/gsm_ds_pirelli_ram.template Sun Oct 02 16:51:22 2016 +0000 @@ -0,0 +1,191 @@ +/* + * Integrated Protocol Stack Linker command file (all components) + * + * Target : ARM + * + * Copyright (c) Texas Instruments 2002, Condat 2002 + * + * This version of the linker script template has been concocted + * by Spacefalcon the Outlaw based on previous hacks. + */ + +-c /* Autoinitialize variables at runtime */ + +/*********************************/ +/* SPECIFY THE SYSTEM MEMORY MAP */ +/*********************************/ + +MEMORY +{ + /* using XRAM instead of flash */ + /* Interrupt Vectors Table */ + I_MEM (RXI) : org = 0x01000000 len = 0x00000100 + + /* Boot Sector */ + B_MEM (RXI) : org = 0x01000100 len = 0x00001f00 + + /* Magic Word for Calypso Boot ROM */ + MWC_MEM (RXI) : org = 0x01002000 len = 0x00000004 fill = 0x0000001 + + /* Program Memory */ + P_MEM1 (RXI) : org = 0x01004000 len = 0x00000700 + P_MEM2 (RXI) : org = 0x01004700 len = 0x00000004 + P_MEM3 (RXI) : org = 0x01004704 len = 0x003fb8fc + + /* FFS Area */ + FFS_MEM (RX) : org = 0x02000000 len = 0x00800000 + /**************************************************************************/ + + /* CS1: External SRAM 1 Mbytes ********************************************/ + /* Data Memory */ + + /* + * Huge XRAM on the Pirelli: present it as two banks of 4 MiB each + * ... or a little less since we just stole half of it for "flash" + */ + + D_MEM1 (RW) : org = 0x01400000 len = 0x00380000 + D_MEM2 (RW) : org = 0x01780000 len = 0x00080000 + /**************************************************************************/ + + /* CS6: Calypso Internal SRAM 512 kbytes **********************************/ + /* Code & Variables Memory */ + S_MEM (RXW) : org = 0x00800000 len = 0x00080000 + /**************************************************************************/ +} + +/***********************************************/ +/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ +/***********************************************/ + +/* + * Since the bootloader directly calls the INT_Initialize() routine located + * in int.s, this int.s code must always be mapped at the same address + * (usually in the second flash sector). Its length is about 0x500 bytes. + * Then comes the code that need to be loaded into the internal RAM. + */ + +SECTIONS +{ + .intvecs : {} > I_MEM /* Interrupt Vectors Table */ + .monitor : > B_MEM /* Monitor Constants & Code */ + { + $(CONST_BOOT_LIB) + } + + .inttext : {} > P_MEM1 /* int.s Code */ + + .bss_dar : > D_MEM1 /* DAR SWE Variables */ + { + $(BSS_DAR_LIB) + } + + /* + * The .bss section should not be split to ensure it is initialized to 0 + * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 + * or in D_MEM2. + * + * Falcon's note for K5A3281: see the comments above where the memory + * regions are defined. + */ + + .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ + { + $(BSS_BOOT_LIB) + } + + /* + * All .bss sections, which must be mapped in internal RAM must be + * grouped in order to initialized the corresponding memory to 0. + * This initialization is done in int.s file before calling the Nucleus + * routine. + */ + + GROUP + { + S_D_Mem /* Label of start address of .bss section in Int. RAM */ + .DintMem + { + + /* + * .bss sections of the application + */ + + $(BSS_LIBS) + + } + + API_HISR_stack : {} + + E_D_Mem /* Label of end address of .bss section in Int. RAM */ + } > S_MEM + + /* + * .text and .const sections which must be mapped in internal RAM. + */ + + .ldfl : {} > P_MEM2 /* Used to know the start load address */ + GROUP load = P_MEM3, run = S_MEM + { + S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ + .PIntMem + { + /* + * .text and .const sections of the application. + * + * The .veneer sections correspond exactly to .text:v&n sections + * implementing the veneer functions. The .text:v$n -> .veneer + * translation is performed by PTOOL software when PTOOL_OPTIONS + * environement variable is set to veneer_section. + */ + + $(CONST_LIBS) + + } + E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ + } + + /* + * The rest of the code is mapped in flash, however the trampolines + * load address should be consistent with .text. + */ + COMMENT2START + `trampolines load = P_MEM3, run = S_MEM + COMMENT2END + + .text : {} > P_MEM3 /* Code */ + + /* + * The rest of the constants is mapped in flash. + * The .cinit section should not be split. + */ + + .cinit : {} > P_MEM3 /* Initialization Tables */ + .const : {} > P_MEM3 /* Constant Data */ + KadaAPI : {} > P_MEM3 /* ROMized CLDC */ + + .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ + + .stackandheap : > D_MEM1 /* System Stacks, etc... */ + { + /* Leave 20 32bit words for register pushes. */ + . = align(8); + . += 20 * 4; + + /* Stack for abort and/or undefined modes. */ + exception_stack = .; + + /* Leave 38 32bit words for state saving on exceptions. */ + _xdump_buffer = .; + . += 38 * 4; + . = align(8); + + /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ + stack_segment = .; + . += 0xB00; + } + + .data : {} > D_MEM1 /* Initialized Data */ + .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ + +} diff -r 6c3881378a31 -r 7bd197063b9e targets/pirelli.conf --- a/targets/pirelli.conf Sun Oct 02 14:17:39 2016 +0000 +++ b/targets/pirelli.conf Sun Oct 02 16:51:22 2016 +0000 @@ -1,3 +1,4 @@ LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_flash.template +RAM_LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_ram.template MAIN_blob=blobs/patches/main-pirelli.lib TPUDRV_blob=