--- a/src/cs/system/main/init.c	Sat Apr 06 23:54:20 2019 +0000
+++ b/src/cs/system/main/init.c	Mon Jun 17 01:36:38 2019 +0000
@@ -500,15 +500,16 @@
       DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
       #if (CHIPSET == 8)
         DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
-      #elif (CHIPSET == 10)
+      #elif (CHIPSET == 10) || (CHIPSET == 11)
         DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
       #else
         #error "We only have DPLL setup for CHIPSETs 8 and 10"
       #endif
       CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
       /*
-       * FreeCalypso change: memory timings and widths
-       * are target-dependent.
+       * FreeCalypso change: memory timings and widths are target-dependent;
+       * please refer to the MEMIF-wait-states document in the freecalypso-docs
+       * repository for the full explanation.
        */
       #ifdef CONFIG_TARGET_PIRELLI
         /*
@@ -520,30 +521,18 @@
         MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
-      #elif defined(CONFIG_TARGET_FCFAM)
+      #elif defined(CONFIG_TARGET_C155)
         /*
-         * The settings currently adopted for the FreeCalypso
-         * hardware family, only nCS0, nCS1 and nCS2 are used
-         * presently.
+         * C155/156 official fw MEMIF config is almost the same as Pirelli's,
+         * only nCS4 WS is different, but nCS4 is unused on this model...
          */
         MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
-      #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8)
-        /*
-         * On D-Sample C05 (older Calypso silicon version) the clocks
-         * run slower: the ARM clock runs at 39 MHz instead of 52 MHz.
-         * Therefore, we need to use fewer wait states to effect
-         * the same memory speed.
-         */
-        MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0);
-        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
-      #else
+        MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
+      #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
+            defined(CONFIG_TARGET_GTAMODEM)
         /*
          * The original settings from Openmoko,
          * only nCS0 and nCS1 are actually used,
@@ -555,6 +544,43 @@
         MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      #elif defined(CONFIG_TARGET_J100)
+        /*
+         * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
+         * it appears that SE J100 has its ringtone melody generator chip
+         * hooked up there.
+         */
+        MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      #elif (CHIPSET == 8)
+        /*
+         * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
+         * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
+         * so we should be good on this board.
+         */
+        MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      #elif (CHIPSET == 10) || (CHIPSET == 11)
+        /*
+         * Default for Calypso C035 targets in the absence of a more specific
+         * selection above.  We put the WS=4 memory-oriented setting on all
+         * chip selects so we automatically cover targets with a second flash
+         * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
+         * weirder targets with XRAM somewhere other than nCS1.
+         */
+        MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+      #else
+        #error "Unknown MEMIF configuration"
       #endif
       MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
       MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);