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annotate fpga/mcsi-rx/uart_tx.v @ 5:3ae4a6ca5639

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add README
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 12 Oct 2024 03:11:17 +0000
parents b3190839cce3
children
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1 /*
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2 * This Verilog module captures the UART output logic.
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3 */
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4
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5 module uart_tx (IntClk, Tx_trigger, Tx_data, UART_out);
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6
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7 input IntClk;
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8 input Tx_trigger;
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9 input [15:0] Tx_data;
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10 output UART_out;
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11 reg UART_out;
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13 reg tx_active;
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14 reg [5:0] clk_div;
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15 reg [4:0] bit_count;
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16 reg [17:0] shift_reg;
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17
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18 initial begin
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19 tx_active = 1'b0;
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20 UART_out = 1'b1;
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21 end
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22
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23 always @(posedge IntClk)
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24 if (!tx_active && Tx_trigger)
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25 begin
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26 tx_active <= 1'b1;
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27 UART_out <= 1'b0;
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28 clk_div <= 6'd0;
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29 shift_reg <= {Tx_data[15:8],2'b01,Tx_data[7:0]};
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30 bit_count <= 5'd0;
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31 end
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32 else if (tx_active)
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33 begin
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34 clk_div <= clk_div + 6'd1;
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35 if (clk_div == 6'd63)
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36 begin
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37 UART_out <= shift_reg[0];
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38 shift_reg <= {1,shift_reg[17:1]};
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39 bit_count <= bit_count + 5'd1;
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40 if (bit_count == 5'd19)
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41 tx_active <= 1'b0;
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42 end
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43 end
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44
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45 endmodule