FreeCalypso > hg > fc-pcm-if
annotate fpga/mcsi-rx/clk_check.v @ 9:62579cfff4fc
fc-mcsi-rxtx: more proper integration with ttyhacks
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 28 Oct 2024 06:02:04 +0000 |
parents | b3190839cce3 |
children |
rev | line source |
---|---|
1
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 /* |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 * The logic implemented in this module detects if MCSI_CLK is running or not, |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 * for the purpose of visual indication on a LED. In the future Tx-capable |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 * FPGA, this logic will also be used to reset the Tx buffer when the clock |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 * stops. |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 */ |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 module clk_check (IntClk, MCSI_CLK_sync, MCSI_CLK_running); |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 input IntClk; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 input MCSI_CLK_sync; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 output MCSI_CLK_running; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 reg [15:0] shift_reg; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 always @(posedge IntClk) |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 shift_reg <= {shift_reg[14:0],MCSI_CLK_sync}; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 assign MCSI_CLK_running = (shift_reg != 16'h0000) && (shift_reg != 16'hFFFF); |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 endmodule |