FreeCalypso > hg > fc-pcm-if

annotate fpga/mcsi-rx/clk_edge.v @ 9:62579cfff4fc

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
fc-mcsi-rxtx: more proper integration with ttyhacks
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 28 Oct 2024 06:02:04 +0000
parents b3190839cce3
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This Verilog module captures the logic that detects falling edges of
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 * MCSI_CLK: it is the edge on which we have to sample data and frame sync.
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 */
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 module clk_edge (IntClk, MCSI_CLK_sync, MCSI_CLK_negedge);
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 input IntClk;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 input MCSI_CLK_sync;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 output MCSI_CLK_negedge;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 reg prev_state;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 always @(posedge IntClk)
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 prev_state <= MCSI_CLK_sync;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 assign MCSI_CLK_negedge = !MCSI_CLK_sync && prev_state;
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18
b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 endmodule