FreeCalypso > hg > fc-pcm-if

annotate fpga/common/icestick-mcsi.pcf @ 2:a4918a161d2e

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sw: starting with libserial, copied from fc-sim-sniff
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 22:37:11 +0000
parents 4624f3da093a
children
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4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 # Pin Constraint File for the HK1X FPGA as wired on the Icestick board,
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 # adapted for FCDEV3B MCSI application.
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 # Board essentials
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 set_io CLK12 21
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 set_io LED1 99
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 set_io LED2 98
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 set_io LED3 97
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 set_io LED4 96
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 set_io LED5 95
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 # FT2232H UART channel, signal names are from FT2232H DTE perspective,
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 # the logic in the FPGA has to act as DCE.
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 set_io UART_TxD 9
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 set_io UART_RxD 8
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 set_io UART_RTS 7
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 set_io UART_CTS 4
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 set_io UART_DTR 3
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 set_io UART_DSR 2
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 set_io UART_DCD 1
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22
4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 # Calypso MCSI connection on J1 header pins, pinout chosen to match FCDEV3B.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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24
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 set_io MCSI_CLK 115
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 set_io MCSI_RXD 114
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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27 set_io MCSI_TXD 113
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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28 set_io MCSI_FSYNCH 112