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annotate fpga/mcsi-rx/sync_inputs.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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b3190839cce3 first FPGA version, MCSI Rx only
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1 /*
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2 * This Verilog module captures the input synchronizer logic: passing
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3 * all 3 MCSI inputs through double-DFF synchronizers to bring them into
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4 * our internal clock domain.
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5 */
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7 module sync_inputs (IntClk, MCSI_CLK_raw, MCSI_CLK_sync, MCSI_FS_raw,
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8 MCSI_FS_sync, MCSI_Din_raw, MCSI_Din_sync);
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10 input IntClk;
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11 input MCSI_CLK_raw, MCSI_FS_raw, MCSI_Din_raw;
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12 output MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
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13 reg MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
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15 reg MCSI_CLK_sync1, MCSI_FS_sync1, MCSI_Din_sync1;
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17 always @(posedge IntClk)
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18 MCSI_CLK_sync1 <= MCSI_CLK_raw;
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20 always @(posedge IntClk)
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21 MCSI_CLK_sync <= MCSI_CLK_sync1;
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23 always @(posedge IntClk)
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24 MCSI_FS_sync1 <= MCSI_FS_raw;
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26 always @(posedge IntClk)
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27 MCSI_FS_sync <= MCSI_FS_sync1;
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29 always @(posedge IntClk)
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30 MCSI_Din_sync1 <= MCSI_Din_raw;
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32 always @(posedge IntClk)
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33 MCSI_Din_sync <= MCSI_Din_sync1;
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34
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35 endmodule