FreeCalypso > hg > fc-pcm-if
annotate fpga/mcsi-rx/clk_check.v @ 11:e93a11f44e6f
fc-mcsi-rxtx: implement basic Tx
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 28 Oct 2024 06:34:42 +0000 |
parents | b3190839cce3 |
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rev | line source |
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b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 /* |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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2 * The logic implemented in this module detects if MCSI_CLK is running or not, |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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3 * for the purpose of visual indication on a LED. In the future Tx-capable |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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4 * FPGA, this logic will also be used to reset the Tx buffer when the clock |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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5 * stops. |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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6 */ |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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7 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 module clk_check (IntClk, MCSI_CLK_sync, MCSI_CLK_running); |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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10 input IntClk; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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11 input MCSI_CLK_sync; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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12 output MCSI_CLK_running; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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14 reg [15:0] shift_reg; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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15 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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16 always @(posedge IntClk) |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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17 shift_reg <= {shift_reg[14:0],MCSI_CLK_sync}; |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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19 assign MCSI_CLK_running = (shift_reg != 16'h0000) && (shift_reg != 16'hFFFF); |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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20 |
b3190839cce3
first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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21 endmodule |