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annotate fpga/mcsi-rx/clk_edge.v @ 16:f422d19c0118 default tip

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fc-mcsi-rxtx: fix bug in PCM sample Rx
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Oct 2024 01:41:33 +0000
parents b3190839cce3
children
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1 /*
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2 * This Verilog module captures the logic that detects falling edges of
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3 * MCSI_CLK: it is the edge on which we have to sample data and frame sync.
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4 */
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6 module clk_edge (IntClk, MCSI_CLK_sync, MCSI_CLK_negedge);
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8 input IntClk;
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9 input MCSI_CLK_sync;
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10 output MCSI_CLK_negedge;
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12 reg prev_state;
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14 always @(posedge IntClk)
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15 prev_state <= MCSI_CLK_sync;
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17 assign MCSI_CLK_negedge = !MCSI_CLK_sync && prev_state;
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18
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19 endmodule