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comparison fpga/mcsi-rx/clk_check.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * The logic implemented in this module detects if MCSI_CLK is running or not,
3 * for the purpose of visual indication on a LED. In the future Tx-capable
4 * FPGA, this logic will also be used to reset the Tx buffer when the clock
5 * stops.
6 */
7
8 module clk_check (IntClk, MCSI_CLK_sync, MCSI_CLK_running);
9
10 input IntClk;
11 input MCSI_CLK_sync;
12 output MCSI_CLK_running;
13
14 reg [15:0] shift_reg;
15
16 always @(posedge IntClk)
17 shift_reg <= {shift_reg[14:0],MCSI_CLK_sync};
18
19 assign MCSI_CLK_running = (shift_reg != 16'h0000) && (shift_reg != 16'hFFFF);
20
21 endmodule