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comparison fpga/mcsi-rx/clk_edge.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * This Verilog module captures the logic that detects falling edges of
3 * MCSI_CLK: it is the edge on which we have to sample data and frame sync.
4 */
5
6 module clk_edge (IntClk, MCSI_CLK_sync, MCSI_CLK_negedge);
7
8 input IntClk;
9 input MCSI_CLK_sync;
10 output MCSI_CLK_negedge;
11
12 reg prev_state;
13
14 always @(posedge IntClk)
15 prev_state <= MCSI_CLK_sync;
16
17 assign MCSI_CLK_negedge = !MCSI_CLK_sync && prev_state;
18
19 endmodule