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comparison fpga/mcsi-rx/uart_tx.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * This Verilog module captures the UART output logic.
3 */
4
5 module uart_tx (IntClk, Tx_trigger, Tx_data, UART_out);
6
7 input IntClk;
8 input Tx_trigger;
9 input [15:0] Tx_data;
10 output UART_out;
11 reg UART_out;
12
13 reg tx_active;
14 reg [5:0] clk_div;
15 reg [4:0] bit_count;
16 reg [17:0] shift_reg;
17
18 initial begin
19 tx_active = 1'b0;
20 UART_out = 1'b1;
21 end
22
23 always @(posedge IntClk)
24 if (!tx_active && Tx_trigger)
25 begin
26 tx_active <= 1'b1;
27 UART_out <= 1'b0;
28 clk_div <= 6'd0;
29 shift_reg <= {Tx_data[15:8],2'b01,Tx_data[7:0]};
30 bit_count <= 5'd0;
31 end
32 else if (tx_active)
33 begin
34 clk_div <= clk_div + 6'd1;
35 if (clk_div == 6'd63)
36 begin
37 UART_out <= shift_reg[0];
38 shift_reg <= {1,shift_reg[17:1]};
39 bit_count <= bit_count + 5'd1;
40 if (bit_count == 5'd19)
41 tx_active <= 1'b0;
42 end
43 end
44
45 endmodule