--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/mcsi-rx/clk_edge.v	Fri Oct 11 21:11:24 2024 +0000
@@ -0,0 +1,19 @@
+/*
+ * This Verilog module captures the logic that detects falling edges of
+ * MCSI_CLK: it is the edge on which we have to sample data and frame sync.
+ */
+
+module clk_edge (IntClk, MCSI_CLK_sync, MCSI_CLK_negedge);
+
+input IntClk;
+input MCSI_CLK_sync;
+output MCSI_CLK_negedge;
+
+reg prev_state;
+
+always @(posedge IntClk)
+	prev_state <= MCSI_CLK_sync;
+
+assign MCSI_CLK_negedge = !MCSI_CLK_sync && prev_state;
+
+endmodule